CN114512464A - Fan-out type packaging structure and preparation method thereof - Google Patents

Fan-out type packaging structure and preparation method thereof Download PDF

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Publication number
CN114512464A
CN114512464A CN202210407062.9A CN202210407062A CN114512464A CN 114512464 A CN114512464 A CN 114512464A CN 202210407062 A CN202210407062 A CN 202210407062A CN 114512464 A CN114512464 A CN 114512464A
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layer
buffer layer
conductive
chip
fan
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CN202210407062.9A
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CN114512464B (en
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陈泽
张聪
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Yongsi Semiconductor Ningbo Co ltd
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Yongsi Semiconductor Ningbo Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
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Abstract

The embodiment of the invention provides a fan-out type packaging structure and a preparation method thereof, and relates to the technical field of semiconductor packaging. Compared with the prior art, the plastic package structure has the advantages that the buffer layer is additionally arranged, the plastic package body is partially wrapped on the buffer layer, the thermal expansion coefficient of the buffer layer is small, when a device is stressed, the buffer layer can deform in preference to the plastic package body, the structural stress of the plastic package body is absorbed, the balance of the internal stress of a product can be realized, and the problem of plastic package warpage is effectively relieved.

Description

Fan-out type packaging structure and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a fan-out type packaging structure and a preparation method of the fan-out type packaging structure.
Background
With the rapid development of the semiconductor industry, Fan-out wafer level package (FOWLP) package structures are widely used in the semiconductor industry. Generally, a single chip is cut from a wafer and then packaged on a carrier wafer, the main advantage is high-density integration, the size of a packaged product is small, the product performance is excellent, the signal transmission frequency is high, and the like.
Disclosure of Invention
The invention aims to provide a fan-out type packaging structure and a preparation method of the fan-out type packaging structure, which can balance internal stress of a product and effectively alleviate the plastic package warpage problem.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a fan-out package structure, including:
a buffer layer;
a chip attached to the buffer layer;
the plastic package body is coated outside the chip;
a first combined wiring layer disposed on the buffer layer;
and a first solder ball disposed on the first combinatorial wiring layer;
the plastic package body is partially wrapped on the buffer layer, the thermal expansion coefficient of the buffer layer is smaller than that of the plastic package body, the first solder balls are electrically connected with the first combined wiring layer, and the first combined wiring layer is electrically connected with the chip.
In an optional implementation mode, the buffer layer is provided with an accommodating groove, the depth of the accommodating groove is greater than the thickness of the chip, the chip is attached in the accommodating groove, the plastic package body at least covers the accommodating groove, and the edge of the buffer layer extends to the external space so that the side wall of the buffer layer is exposed outside.
In an optional embodiment, the buffer layer is further provided with filling through holes, the filling through holes are located on at least two sides of the accommodating groove, and the plastic package body covers the filling through holes, so that the plastic package body and the buffer layer are arranged in a staggered manner.
In an optional embodiment, the buffer layer is further provided with a filling through hole, the filling through hole is located on at least two sides of the accommodating groove, and the filling through hole is filled with an electrically conductive and thermally conductive column.
In an optional embodiment, a second combined wiring layer is further disposed on a side of the plastic package body away from the first combined wiring layer, a second solder ball is further disposed on the second combined wiring layer, the second solder ball is electrically connected to the second combined wiring layer, the second combined wiring layer is electrically connected to the conductive heat pillar, and the conductive heat pillar is electrically connected to the first combined wiring layer.
In an optional implementation manner, a positioning groove penetrating through the bottom wall of the accommodating groove to the first combined wiring layer is provided, a first conductive pillar is formed in the positioning groove, the first combined wiring layer is connected to one end of the first conductive pillar, and the chip is connected to the other end of the first conductive pillar, so that the chip is electrically connected to the first combined wiring layer.
In an optional implementation manner, the first combined wiring layer includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a circuit layer, the first dielectric layer covers the buffer layer, a first open slot corresponding to the first conductive pillar is formed in the first dielectric layer, a second conductive pillar is formed in the first open slot, the second dielectric layer covers the first dielectric layer and is provided with a second open slot corresponding to the second conductive pillar, the circuit layer is formed in the second open slot, the circuit layer is connected to the second conductive pillar, the third dielectric layer covers the second dielectric layer, a third open slot is formed in the third dielectric layer, a conductive layer is formed in the third open slot, and the first solder ball is disposed on the conductive layer.
In an alternative embodiment, the width of the first conductive pillar is greater than the width of the second conductive pillar.
In an optional implementation manner, the first combined wiring layer includes a first dielectric layer, a second dielectric layer and a circuit layer, a first open slot that is provided with on the first dielectric layer and conducts to the first conductive column, a circuit layer is formed in the first open slot, the circuit layer is connected with the first conductive column, the second dielectric layer covers on the first dielectric layer and is provided with a second open slot that conducts to the circuit layer, a conductive layer is formed in the second open slot, and the first solder ball is arranged on the conductive layer.
In a second aspect, the present invention provides a method for manufacturing a fan-out package structure, including:
forming a buffer layer on the carrier;
attaching a chip to the buffer layer;
forming a plastic package body coated outside the chip on the buffer layer;
removing the carrier and exposing the buffer layer;
forming a first combined wiring layer on the buffer layer;
forming a first solder ball on the first combined wiring layer;
the plastic package body is partially wrapped on the buffer layer, the thermal expansion coefficient of the buffer layer is smaller than that of the plastic package body, the first solder balls are electrically connected with the first combined wiring layer, and the first combined wiring layer is electrically connected with the chip.
In an alternative embodiment, the step of forming a buffer layer on the carrier includes:
mounting a buffer glue layer on the carrier;
and forming at least an accommodating groove and a positioning groove on the buffer adhesive layer by utilizing an etching process to form the buffer layer.
In an alternative embodiment, after the step of forming the first solder ball on the first combined wiring layer, the method further includes:
and cutting the buffer layers positioned on two sides of the accommodating groove along the cutting path.
The beneficial effects of the embodiment of the invention include, for example:
the embodiment of the invention provides a fan-out type packaging structure, which is characterized in that a buffer layer is arranged, a chip is attached to the buffer layer, a plastic package body wrapping the chip is arranged, a first combined wiring layer is arranged on the buffer layer, and a first welding ball is arranged on the first combined wiring layer. Compared with the prior art, the plastic package structure has the advantages that the buffer layer is additionally arranged, the plastic package body is partially wrapped on the buffer layer, the thermal expansion coefficient of the buffer layer is smaller, when a device is stressed, the buffer layer can deform in preference to the plastic package body, the structural stress of the plastic package body is absorbed, the balance of the internal stress of a product can be realized, and the problem of plastic package warping is effectively relieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a fan-out package structure according to a first embodiment of the invention;
FIG. 2 is a diagram illustrating a fan-out package structure according to a second embodiment of the present invention;
FIG. 3 is a diagram illustrating a fan-out package structure according to a third embodiment of the present invention;
FIG. 4 is a diagram illustrating a fan-out package structure according to a fourth embodiment of the present invention;
fig. 5 to 11 are process flow diagrams of a manufacturing method of a fan-out package structure according to a fifth embodiment of the invention.
Icon: 100-fan-out package structure; 110-a buffer layer; 111-a receiving recess; 113-a positioning groove; 115-fill the via; 117 — first conductive post; 120-chip; 130-plastic package body; 140-a first combined routing layer; 141-a first dielectric layer; 142-a second dielectric layer; 143-a third dielectric layer; 144-a line layer; 145-a second conductive pillar; 146-a conductive layer; 150-first solder balls; 160-a second combined wiring layer; 170-second solder balls; 180-electrically conductive, thermally conductive posts; 200-carrier.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
As disclosed in the background art, in the fan-out package structure in the prior art, a chip is generally wrapped in a plastic package body, and a wiring layer is completed on the surface of the plastic package body to form the fan-out structure.
In order to solve the above problems, the present invention provides a fan-out package structure and a method for manufacturing the fan-out package structure, and features in embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1, the embodiment provides a fan-out package structure 100, which can realize the balance of internal stress of a product, effectively reduce the problem of plastic package warpage, reduce cutting wear in the preparation process, and improve cutting efficiency.
The embodiment provides a fan-out package structure 100, which includes a buffer layer 110, a chip 120, a plastic package body 130, a first combined wiring layer 140 and first solder balls 150, wherein the chip 120 is attached to the buffer layer 110, the plastic package body 130 wraps the chip 120 and partially wraps the buffer layer 110, the first combined wiring layer 140 is disposed on the buffer layer 110, the first solder balls 150 are disposed on the first combined wiring layer 140, a thermal expansion coefficient of the buffer layer 110 is smaller than a thermal expansion coefficient of the plastic package body 130, the first solder balls 150 are electrically connected with the first combined wiring layer 140, and the first combined wiring layer 140 is electrically connected with the chip 120.
It should be noted that, in this embodiment, a carrier 200 may be used for manufacturing work, for example, a buffer layer 110 is formed on the carrier 200, patterning is performed to obtain a corresponding structure, then a chip 120 is attached to the buffer layer 110, a plastic package body 130 is formed by using a plastic packaging process, then the carrier 200 is removed, the buffer layer 110 is exposed, and finally wiring is completed on the buffer layer 110 to form a first combined wiring layer 140 and a first solder ball 150, so as to form a fan-out structure, where the buffer layer 110 may be made of a polymer composite material such as epoxy resin, polyimide, benzocyclobutene, and its thermal expansion coefficient is smaller than that of the plastic package body 130, so that the buffer layer 110 may deform in preference to the plastic package body 130 when a device is stressed, absorb a structural stress generated by the plastic package body 130, and prevent deformation.
It should be noted that, in order to conveniently strip the carrier 200, the buffer layer 110 in this embodiment may also be made of a UV material, that is, the carrier 200 may be easily stripped from the buffer layer 110 by irradiating UV light, and the flatness of the stripped surface is ensured. Of course, a UV glue layer may be additionally disposed here, that is, before the buffer layer 110 is formed, a UV glue is coated on the surface of the carrier 200, and the carrier 200 and the glue layer are peeled off by using UV light irradiation in a peeling process.
In this embodiment, the buffer layer 110 is provided with an accommodating groove 111, a depth of the accommodating groove 111 is greater than a thickness of the chip 120, the chip 120 is attached in the accommodating groove 111, the plastic package body 130 at least covers the accommodating groove 111, and an edge of the buffer layer 110 extends to an external space, so that a sidewall of the buffer layer 110 is exposed. Specifically, after the chip 120 is mounted, the plastic package material at least fills the whole accommodating groove 111, so that the size of the accommodating groove 111 on the surface buffer layer 110 of the plastic package body 130 is larger than that of the chip 120, the chip 120 is conveniently mounted in the accommodating groove 111, and meanwhile, the plastic package body 130 can completely cover the chip 120 in the plastic package process, so that the chip 120 is well protected. In addition, the side wall of the buffer layer 110 is exposed, namely, the buffer layer 110 needs to be cut during cutting, so that the plastic package body 130 is prevented from being cut, the cutting channels are distributed on the buffer layer 110, cutting abrasion can be reduced, and cutting efficiency is improved.
It should be noted that in this embodiment, a single chip 120 is disposed in the accommodating recess 111, and in other preferred embodiments, a combination of a plurality of chips 120, such as a plurality of stacked chips 120 or a plurality of tiled chips 120, may also be disposed in the accommodating recess 111, and is not limited in this respect.
In this embodiment, the buffer layer 110 is further provided with filling through holes 115, the filling through holes 115 are located on at least two sides of the accommodating groove 111, and the plastic package body 130 covers the filling through holes 115, so that the plastic package body 130 and the buffer layer 110 are arranged in a staggered manner. Specifically, the filling through hole 115 penetrates through the buffer layer 110 and is filled with the molding compound, so that the formed molding compound 130 can be staggered with the buffer layer 110, and the effect of preventing deformation is further achieved while the structural strength is enhanced. And the filling through holes 115 are located around the accommodating groove 111, so that the buffer layer 110 is formed with buffer columns around the chip 120, and meanwhile, the chip 120 is attached to the bottom wall of the accommodating groove 111, thereby not only realizing the stress balance at the position of the chip 120, but also realizing the stress balance of the whole product structure.
It should be noted that, in the embodiment, there are no filling particles inside the buffer layer 110, the design height of the buffer layer 110 is higher than the height of the chip 120, and the plastic package body 130 is flush with the buffer layer 110, so as to ensure that the plastic package body 130 completely covers the chip 120. Of course, the height of the buffer material can be adjusted according to the simulation parameters so that the buffer material does not leak out of the surface of the plastic package 130.
In the present embodiment, the bottom wall of the accommodating recess 111 is provided with a positioning groove 113 penetrating to the first combined wiring layer 140, a first conductive pillar 117 is formed in the positioning groove 113, the first combined wiring layer 140 is connected to one end of the first conductive pillar 117, and the chip 120 is connected to the other end of the first conductive pillar 117, so that the chip 120 is electrically connected to the first combined wiring layer 140. Specifically, the positioning groove 113 is used for aligning the bonding pad of the chip 120, so that the mounting accuracy of the chip 120 is improved, and meanwhile, the grooving action of the positioning groove 113 is completed before the chip 120 is mounted when the buffer layer 110 is formed, so that the laser grooving can be further avoided when the first combined wiring layer 140 is subsequently formed, the laser grooving thickness of the dielectric layer is reduced, and the laser grooving efficiency is improved.
It should be noted that, in this embodiment, by providing the positioning groove 113, when the chip 120 is mounted, the pad of the chip 120 can be covered at the groove of the positioning groove 113, so that the etching solution is prevented from gathering around the pad in the subsequent wiring process, and the pad of the chip 120 is effectively protected.
In addition, the material packing particle of plastic-sealed body 130 needs to be greater than the size of constant head tank 113, for example, the packing particle is 35um, and the size of constant head tank 113 is less than 20% of its packing (the size of constant head tank is 7um promptly) to can avoid packing in the particle gets into constant head tank 113, shutoff constant head tank 113 when avoiding the plastic envelope.
In this embodiment, the first routing combination layer 140 includes a first dielectric layer 141, a second dielectric layer 142, a third dielectric layer 143, and a circuit layer 144, where the first dielectric layer 141 covers the buffer layer 110, a first open slot corresponding to the first conductive pillar 117 is formed on the first dielectric layer 141, a second conductive pillar 145 is formed in the first open slot, the second dielectric layer 142 covers the first dielectric layer 141 and is provided with a second open slot corresponding to the second conductive pillar 145, a circuit layer 144 is formed in the second open slot, the circuit layer 144 is connected to the second conductive pillar 145, the third dielectric layer 143 covers the second dielectric layer 142, a third open slot is formed on the third dielectric layer 143, a conductive layer 146 is formed in the third open slot, and the first solder ball 150 is disposed on the conductive layer 146. Specifically, the first dielectric layer 141, the second dielectric layer 142, and the third dielectric layer 143 are made of dielectric materials, and the forming manner of the dielectric materials is the same as that of a conventional wiring manner, wherein the first conductive pillar 117 is connected to the second conductive pillar 145, the second conductive pillar 145 is connected to the circuit layer 144, and the circuit layer 144 is connected to the conductive layer 146 and the first solder ball 150, so that the overall electrical connection is completed, and the fan-out package structure 100 is implemented.
It should be noted that in the present embodiment, the first conductive pillar 117, the second conductive pillar 145, the circuit layer 144, and the conductive layer 146 may be made of a conductive metal, such as at least one of copper, titanium, gold, and silver, so as to ensure a good electrical connection effect.
In the present embodiment, the width of the first conductive pillar 117 is greater than the width of the second conductive pillar 145. Specifically, the first conductive pillar 117 may have a three-layer structure, which is respectively formed by a titanium-copper-titanium layer, that is, titanium layers are disposed on both sides close to the chip 120 and the second conductive pillar 145, and a copper layer is disposed in the middle of the titanium layer, and the titanium layers serve as an adhesion layer to improve the bonding force between the upper second conductive pillar 145 and the bonding pad of the chip 120. Moreover, the width of the first conductive pillar 117 is greater than that of the second conductive pillar 145, so that the two form an inverted T-shaped structure, and the overall structural strength of the first conductive pillar 117 and the second conductive pillar 145 is enhanced. Moreover, the opening area of the first conductive pillar 117 is larger than the area of the bonding pad on the chip 120, so that the metal on the first conductive pillar 117 can cover the periphery of the bonding pad, the bonding force between the first conductive pillar and the bonding pad is improved, the area of the second conductive pillar 145 is small, the contact area between the second conductive pillar and the upper circuit layer 144 can be reduced, the wiring density can be improved, and the miniaturization of the device is facilitated.
In summary, the present embodiment provides a fan-out package structure 100, in which a buffer layer 110 is disposed, a chip 120 is attached to the buffer layer 110, a plastic package body 130 is disposed to cover the chip 120, a first combined wiring layer 140 is disposed on the buffer layer 110, and a first solder ball 150 is disposed on the first combined wiring layer 140, where the plastic package body 130 partially covers the buffer layer 110, a thermal expansion coefficient of the buffer layer 110 is smaller than a thermal expansion coefficient of the plastic package body 130, the first solder ball 150 is electrically connected to the first combined wiring layer 140, and the first combined wiring layer 140 is electrically connected to the chip 120, thereby implementing fan-out package. In the embodiment, the buffer layer 110 is additionally arranged, and the plastic package body 130 is partially coated on the buffer layer 110, so that the thermal expansion coefficient of the buffer layer 110 is small, when a device is stressed, the buffer layer 110 can deform preferentially to the plastic package body 130, the structural stress of the plastic package body 130 is absorbed, the balance of the internal stress of a product can be realized, and the problem of plastic package warpage is effectively alleviated. Cutting way is located buffer layer 110 during cutting simultaneously, can cut along buffer layer 110, effectively reduces cutting wear, promotes cutting efficiency.
Second embodiment
Referring to fig. 2, the present embodiment provides a fan-out package structure 100, the basic structure and principle and the generated technical effect are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents in the first embodiment where nothing is mentioned in this embodiment.
In this embodiment, the fan-out package structure 100 includes a buffer layer 110, a chip 120, a plastic package body 130, a first combined wiring layer 140 and first solder balls 150, the chip 120 is attached on the buffer layer 110, the plastic package body 130 covers the chip 120 and partially covers the buffer layer 110, the first combined wiring layer 140 is disposed on the buffer layer 110, the first solder balls 150 are disposed on the first combined wiring layer 140, wherein a thermal expansion coefficient of the buffer layer 110 is smaller than a thermal expansion coefficient of the plastic package body 130, the first solder balls 150 are electrically connected to the first combined wiring layer 140, and the first combined wiring layer 140 is electrically connected to the chip 120.
In this embodiment, the buffer layer 110 is provided with an accommodating groove 111, a depth of the accommodating groove 111 is greater than a thickness of the chip 120, the chip 120 is attached in the accommodating groove 111, the plastic package body 130 at least covers the accommodating groove 111, and an edge of the buffer layer 110 extends to an external space, so that a sidewall of the buffer layer 110 is exposed. Meanwhile, the buffer layer 110 is further provided with a filling through hole 115, the filling through hole 115 is located on at least two sides of the accommodating groove 111, and the filling through hole 115 is filled with the conductive heat-conducting column 180. Specifically, the filling through hole 115 is located around the accommodating groove 111 and filled with a conductive material, such as a conductive metal, so as to form the conductive heat conducting pillar 180, after the package is completed, one end of the conductive heat conducting pillar 180 can extend to the first combined wiring layer 140, and the other end of the conductive heat conducting pillar can be exposed outside, so that heat generated by the first combined wiring layer 140 can be rapidly conducted to the outside, and the heat dissipation effect of the device is improved.
In the present embodiment, the conductive and thermal conductive pillar 180 is a copper pillar, which can be formed by electroplating in the filled via 115 after the molding compound 130 is formed. This electrically conductive heat conduction post 180 is a plurality of, and the one end and the first wiring layer 140 contact of making up of every electrically conductive heat conduction post 180, and the other end switches on with exterior space to can conduct the heat that the first combination layer produced to the outside rapidly, realize high heat dissipating. Meanwhile, the plurality of conductive heat-conducting columns 180 are located around the accommodating groove 111, so that the strength of the packaging structure can be enhanced, and the deformation can be further prevented.
It should be noted that in the embodiment, during the plastic package, the plastic package may be selectively performed to ensure that only the accommodating groove 111 is filled with the plastic package material. Of course, the size of the filling through hole 115 may also be set to be smaller than the particle size of the plastic package filler, for example, the particle size of the plastic package filler is about 35 μm, and the filling through hole 115 may be kept below 20 μm, so that the plastic package material is prevented from entering the filling through hole 115 during plastic package, and the subsequent formation of the conductive heat-conducting pillar is facilitated.
Third embodiment
Referring to fig. 3, the basic structure and principle of the fan-out package structure 100 and the technical effects thereof according to the present embodiment are the same as those of the first embodiment, and for a brief description, reference may be made to corresponding contents in the first embodiment for the sake of brevity.
In this embodiment, the fan-out package structure 100 includes a buffer layer 110, a chip 120, a plastic package body 130, a first combined wiring layer 140 and first solder balls 150, the chip 120 is attached on the buffer layer 110, the plastic package body 130 covers the chip 120 and partially covers the buffer layer 110, the first combined wiring layer 140 is disposed on the buffer layer 110, the first solder balls 150 are disposed on the first combined wiring layer 140, wherein a thermal expansion coefficient of the buffer layer 110 is smaller than a thermal expansion coefficient of the plastic package body 130, the first solder balls 150 are electrically connected to the first combined wiring layer 140, and the first combined wiring layer 140 is electrically connected to the chip 120.
In this embodiment, the buffer layer 110 is provided with an accommodating groove 111, a depth of the accommodating groove 111 is greater than a thickness of the chip 120, the chip 120 is attached in the accommodating groove 111, the plastic package body 130 at least covers the accommodating groove 111, and an edge of the buffer layer 110 extends to an external space, so that a sidewall of the buffer layer 110 is exposed. Meanwhile, the buffer layer 110 is further provided with a filling through hole 115, the filling through hole 115 is located on at least two sides of the accommodating groove 111, and the filling through hole 115 is filled with the conductive heat-conducting column 180.
In this embodiment, a second routing layer 160 is further disposed on a side of the plastic package body 130 away from the first routing layer 140, a second solder ball 170 is further disposed on the second routing layer 160, the second solder ball 170 is electrically connected to the second routing layer 160, the second routing layer 160 is electrically connected to the conductive thermal pillar 180, and the conductive thermal pillar 180 is electrically connected to the first routing layer 140.
In this embodiment, the overall package structure adopts a double-sided wiring structure, a second combined wiring layer 160 is further disposed on the plastic package body 130, and the basic structure and the manufacturing process of the second combined wiring layer 160 can refer to the first combined wiring layer 140. In contrast, the second combined wiring layer 160 is electrically connected to the conductive thermal pillar 180, and the first combined wiring layer 140 is simultaneously electrically connected to the conductive thermal pillar 180 and the chip 120.
The fan-out package structure 100 provided in this embodiment can be stacked on the other side of the plastic package body 130 by using a double-sided wiring structure, so as to increase the integration level of the functions of the chip 120.
Fourth embodiment
Referring to fig. 4, the present embodiment provides a fan-out package structure 100, the basic structure and principle and the generated technical effect are the same as those of the first embodiment, and for the sake of brief description, reference may be made to the corresponding contents in the first embodiment where nothing is mentioned in this embodiment.
In this embodiment, the fan-out package structure 100 includes a buffer layer 110, a chip 120, a plastic package body 130, a first combined wiring layer 140, and a first solder ball 150, where the chip 120 is attached on the buffer layer 110, the plastic package body 130 covers the chip 120 and partially covers the buffer layer 110, the first combined wiring layer 140 is disposed on the buffer layer 110, and the first solder ball 150 is disposed on the first combined wiring layer 140, where a thermal expansion coefficient of the buffer layer 110 is smaller than a thermal expansion coefficient of the plastic package body 130, the first solder ball 150 is electrically connected to the first combined wiring layer 140, and the first combined wiring layer 140 is electrically connected to the chip 120.
The buffer layer 110 is provided with an accommodating groove 111, the depth of the accommodating groove 111 is greater than the thickness of the chip 120, the chip 120 is attached in the accommodating groove 111, the plastic package body 130 at least covers the accommodating groove 111, and the edge of the buffer layer 110 extends to the external space, so that the side wall of the buffer layer 110 is exposed outside. A positioning groove 113 penetrating through the first combined wiring layer 140 is formed in the bottom wall of the accommodating groove 111, a first conductive pillar 117 is formed in the positioning groove 113, the first combined wiring layer 140 is connected with one end of the first conductive pillar 117, and the chip 120 is connected with the other end of the first conductive pillar 117, so that the chip 120 is electrically connected with the first combined wiring layer 140.
In this embodiment, the first routing combination layer 140 includes a first dielectric layer 141, a second dielectric layer 142, and a circuit layer 144, a first open slot that is connected to the first conductive pillar 117 is formed in the first open slot, the circuit layer 144 is connected to the first conductive pillar 117, the second dielectric layer 142 covers the first dielectric layer 141 and is provided with a second open slot that is connected to the circuit layer 144, a conductive layer 146 is formed in the second open slot, and the first solder ball 150 is disposed on the conductive layer 146. Specifically, in the present embodiment, the first conductive pillars 117 are used to electrically connect the circuit layer 144 and the chip 120, so that the package size is reduced.
Compared with the first embodiment, the fan-out package structure 100 provided by this embodiment adopts a single conductive pillar structure, that is, a structure of the second conductive pillar 145 is omitted, so that the number of layers and the thickness of the first combined wiring layer 140 are reduced, and the package size is further reduced.
Fifth embodiment
The present embodiment provides a method for manufacturing a fan-out package structure, which is used to manufacture the fan-out package structure 100 provided in the first embodiment, the second embodiment, the third embodiment and the fourth embodiment, and reference may be made to the foregoing embodiments for specific structures of the fan-out package structure 100.
The preparation method of the fan-out package structure provided by the embodiment comprises the following steps:
s1: a buffer layer 110 is formed on the carrier 200.
Referring to fig. 5 and fig. 6 in combination, in the process of forming the buffer layer 110, a carrier 200 may be provided, and a buffer glue layer is attached on the carrier 200; then, an etching process is used to form at least the accommodating recess 111 and the positioning groove 113 on the buffer layer to form the buffer layer 110. Specifically, a carrier 200 may be taken and mounted with a buffer layer and then etched, for example, 02And SF6The mixed plasma gas is subjected to a dry etching process, and regions not to be etched are protected by a protective film, thereby forming a structure in which the receiving groove 111, the positioning groove 113, and the filling through-hole 115 are formed.
In this embodiment, the carrier 200 may be made of glass, silicon oxide, metal, or the like, and the buffer layer 110 may be made of a polymer composite material such as epoxy resin, polyimide, benzocyclobutene, or the like. Meanwhile, in order to conveniently strip the carrier 200, the buffer layer 110 in this embodiment may also be made of a UV material, that is, the carrier 200 may be conveniently stripped from the buffer layer 110 by irradiating UV light, and the flatness of the stripped surface is ensured. Of course, a UV glue layer may be additionally disposed here, that is, before the buffer layer 110 is formed, a UV glue is coated on the surface of the carrier 200, and the carrier 200 and the glue layer are peeled off by using UV light irradiation in a peeling process.
S2: the chip 120 is attached on the buffer layer 110.
Referring to fig. 7 in combination, specifically, the chip 120 is placed with its bonding pad facing downward to implement mounting, and the bonding pad of the chip 120 is located in the positioning groove 113 in the receiving groove 111.
S3: a plastic package 130 is formed on the buffer layer 110 to cover the chip 120.
Referring to fig. 8, specifically, after the chip 120 is mounted, a plastic packaging process is performed, and the bottom structure is protected by using a plastic packaging body 130, wherein the plastic packaging body 130 is at least filled in the accommodating groove 111, thereby playing a role of covering the chip 120. When the fan-out package structure 100 provided in the first and fourth embodiments is prepared, the filling through hole 115 is also filled with a molding compound, and the molding compound 130 can wrap a portion of the buffer layer 110 at the same time, so that the buffer layer 110 and the molding compound 130 can be staggered, and a buffer effect is further achieved. When the fan-out package structure 100 provided in the second and third embodiments is prepared, the filling via 115 may also be filled with a conductive material, such as a conductive metal, to form the conductive and heat-conductive pillar 180.
In this embodiment, the thermal expansion coefficient of the material of the buffer layer 110 is smaller than that of the material of the plastic package body 130, and the plastic package body 130 partially covers the buffer layer 110, so that the thermal expansion coefficient of the buffer layer 110 is smaller, when a device is stressed, the buffer layer 110 can deform in preference to the plastic package body 130 to absorb the structural stress of the plastic package body 130, thereby achieving the balance of the internal stress of the product and effectively alleviating the problem of plastic package warpage.
S4: carrier 200 is removed and buffer layer 110 is exposed.
Referring to fig. 9, specifically, the carrier 200 is removed and the buffer layer 110 is exposed by UV (ultraviolet) curing or thermal curing for serving as a separation layer of the encapsulation structure of the chip 120 formed later.
S5: a first combined wiring layer 140 is formed on the buffer layer 110.
Referring to fig. 10, after the carrier 200 is peeled off, the manufactured plastic package structure is turned over, then the first combined wiring layer 140 is formed, the first combined wiring layer 140 is electrically connected to the chip 120, when the fan-out package structure 100 provided in the first embodiment is manufactured, the first dielectric layer 141, the second dielectric layer 142, and the third dielectric layer 143 may be sequentially formed, laser grooving is performed after the first dielectric layer 141 is formed, a first open groove is opened, then an electroplating process is performed to form the first conductive pillar 117 and the second conductive pillar 145, laser grooving is performed after the second dielectric layer 142 is formed, then a circuit layer 144 is formed by electroplating, laser grooving is performed after the third dielectric layer 143 is formed, and then the conductive layer 146 is formed by electroplating. It should be noted that, here, the first dielectric layer 141, the second dielectric layer 142, and the third dielectric layer 143 may be formed by depositing a dielectric material by vapor deposition, such as Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD), and the dielectric material may be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, or the like.
It should be noted that, when the first conductive pillar 117 is formed by electroplating, a three-layer structure may be adopted, that is, a titanium layer is electroplated, a copper layer is electroplated, and a titanium layer is electroplated, so that the first conductive pillar 117 forms a titanium-copper-titanium three-layer structure, where the upper and lower titanium layers can function as an adhesive layer, and the bonding force between the first conductive pillar 117 and the conductive layer 146 and between the first conductive pillar 117 and the pad is improved.
Note that when the fan-out package structure 100 provided in the fourth embodiment is prepared, the preparation of the third dielectric layer 143 and the second conductive pillars 145 may be omitted here.
Referring to fig. 11 in combination, in the preparation of the fan-out package structure 100 according to the third embodiment, after the preparation of the first combined wiring layer 140 is completed, a second combined wiring layer 160 needs to be prepared on the side of the plastic package body 130 away from the first combined wiring layer 140, and the preparation process is consistent with that of the first combined wiring layer 140.
S6: first solder balls 150 are formed on the first combinatorial wiring layer 140.
Referring to fig. 11, specifically, after the preparation of the conductive layer 146 is completed, a first solder ball 150 is formed on the conductive layer 146 by a steel mesh printing or ball-planting manner, where the first solder ball 150 is a solder ball, and the material may be SnAg, SnAgCu, or the like. The first solder balls 150 are electrically connected to the first combinatorial wiring layer 140.
S7: the buffer layer 110 on both sides of the accommodating groove 111 is cut along the cutting streets.
With reference to fig. 1, specifically, after the ball mounting operation is completed, a cutting process is performed, and during the cutting, the cutting is performed along the buffer layer 110, and since the buffer layer 110 has no filler particles, the cutting efficiency can be further improved, and the wear of the cutter can be reduced.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (12)

1. A fan-out package structure, comprising:
a buffer layer;
a chip attached to the buffer layer;
the plastic package body is coated outside the chip;
a first combined wiring layer disposed on the buffer layer;
and a first solder ball disposed on the first combinatorial wiring layer;
the plastic package body is partially wrapped on the buffer layer, the thermal expansion coefficient of the buffer layer is smaller than that of the plastic package body, the first solder balls are electrically connected with the first combined wiring layer, and the first combined wiring layer is electrically connected with the chip.
2. The fan-out package structure of claim 1, wherein the buffer layer has a receiving groove, the receiving groove has a depth greater than a thickness of the chip, the chip is mounted in the receiving groove, the molding compound at least covers the receiving groove, and an edge of the buffer layer extends to an external space, so that a sidewall of the buffer layer is exposed.
3. The fan-out package structure of claim 2, wherein the buffer layer is further provided with filling through holes, the filling through holes are located on at least two sides of the accommodating groove, and the plastic package body covers the filling through holes, so that the plastic package body and the buffer layer are arranged in a staggered manner.
4. The fan-out package structure of claim 2, wherein the buffer layer is further provided with filling through holes, the filling through holes are located on at least two sides of the accommodating groove, and the filling through holes are filled with conductive and heat-conductive columns.
5. The fan-out package structure of claim 4, wherein a second routing layer is further disposed on a side of the molding compound away from the first routing layer, a second solder ball is further disposed on the second routing layer, the second solder ball is electrically connected to the second routing layer, the second routing layer is electrically connected to the conductive heat pillar, and the conductive heat pillar is electrically connected to the first routing layer.
6. The fan-out package structure of any one of claims 2 to 5, wherein a positioning groove penetrating to the first combined wiring layer is formed in a bottom wall of the accommodating groove, a first conductive pillar is formed in the positioning groove, the first combined wiring layer is connected to one end of the first conductive pillar, and the chip is connected to the other end of the first conductive pillar, so that the chip and the first combined wiring layer are electrically connected.
7. The fan-out package structure of claim 6, wherein the first combined routing layer comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, and a routing layer, the first dielectric layer covers the buffer layer, a first open slot corresponding to the first conductive post is arranged on the first dielectric layer, a second conductive column is formed in the first open slot, the second dielectric layer covers the first dielectric layer, and is provided with a second open slot corresponding to the second conductive pole, the circuit layer is formed in the second open slot, the circuit layer is connected with the second conductive column, the third dielectric layer covers the second dielectric layer, and a third opening groove is formed in the third medium layer, a conductive layer is formed in the third opening groove, and the first solder balls are arranged on the conductive layer.
8. The fan-out package structure of claim 7, wherein a width of the first conductive post is greater than a width of the second conductive post.
9. The fan-out package structure of claim 6, wherein the first combined routing layer includes a first dielectric layer, a second dielectric layer, and a circuit layer, a first open slot that is connected to the first conductive pillar is formed in the first dielectric layer, the circuit layer is connected to the first conductive pillar, the second dielectric layer covers the first dielectric layer and is provided with a second open slot that is connected to the circuit layer, a conductive layer is formed in the second open slot, and the first solder ball is disposed on the conductive layer.
10. A preparation method of a fan-out type packaging structure is characterized by comprising the following steps:
forming a buffer layer on the carrier;
attaching a chip to the buffer layer;
forming a plastic package body coated outside the chip on the buffer layer;
removing the carrier and exposing the buffer layer;
forming a first combined wiring layer on the buffer layer;
forming a first solder ball on the first combined wiring layer;
the plastic package body is partially wrapped on the buffer layer, the thermal expansion coefficient of the buffer layer is smaller than that of the plastic package body, the first solder balls are electrically connected with the first combined wiring layer, and the first combined wiring layer is electrically connected with the chip.
11. The method of manufacturing the fan-out package structure of claim 10, wherein the step of forming the buffer layer on the submount comprises:
mounting a buffer glue layer on the carrier;
and forming at least an accommodating groove and a positioning groove on the buffer adhesive layer by utilizing an etching process to form the buffer layer.
12. The method of making a fan-out package structure of claim 11, wherein after the step of forming first solder balls on the first combined routing layer, the method further comprises:
and cutting the buffer layers positioned on two sides of the accommodating groove along the cutting path.
CN202210407062.9A 2022-04-19 2022-04-19 Fan-out type packaging structure and preparation method thereof Active CN114512464B (en)

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