CN114512458A - Chip package and MEMS device package - Google Patents

Chip package and MEMS device package Download PDF

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Publication number
CN114512458A
CN114512458A CN202210138903.0A CN202210138903A CN114512458A CN 114512458 A CN114512458 A CN 114512458A CN 202210138903 A CN202210138903 A CN 202210138903A CN 114512458 A CN114512458 A CN 114512458A
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CN
China
Prior art keywords
chip
layer
pin
mems
pins
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210138903.0A
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Chinese (zh)
Inventor
杨玉婷
张敏
梅嘉欣
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Memsensing Microsystems Suzhou China Co Ltd
Original Assignee
Memsensing Microsystems Suzhou China Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memsensing Microsystems Suzhou China Co Ltd filed Critical Memsensing Microsystems Suzhou China Co Ltd
Priority to CN202210138903.0A priority Critical patent/CN114512458A/en
Publication of CN114512458A publication Critical patent/CN114512458A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Micromachines (AREA)

Abstract

The invention provides a chip package and an MEMS device package, wherein the chip package comprises a chip and at least one wiring circuit layer, wherein the surface of the chip is provided with a plurality of initial pins and a plurality of target pins, and the initial pins and the target pins are electrically connected through the wiring circuit layer; the chip comprises four side edges, the initial pins are arranged in the areas where any two side edges are located, and the target pins are arranged in the areas where at least one of the rest two side edges is located. The invention can change the pin arrangement mode of the chip to form a new pin arrangement structure, is convenient for chip connection and routing, and is compatible with MEMS device packaging with different sizes.

Description

Chip package and MEMS device package
Technical Field
The invention relates to the technical field of semiconductors, in particular to a chip package and an MEMS device package.
Background
An Application Specific Integrated Circuit (ASIC) chip is an Integrated Circuit chip designed and manufactured according to the requirements of a Specific user and a Specific electronic system, and has the advantages of smaller volume, lower power consumption, improved reliability, improved performance, enhanced security, reduced cost, and the like compared with a general-purpose Integrated Circuit during batch production.
The arrangement of Pins (PAD) of a general ASIC chip is usually parallel up and down, or arranged in adjacent right-angled sides. In the silicon microphone package, when the size of the product in the length direction is small, the distance from the ASIC chips arranged in parallel or in a right angle to the edge of the product is small, and the routing space is limited, but if the layout of the existing ASIC PAD is redesigned, the cost of wafer (wafer) wafer is high, the routing layout of each functional layer can be influenced after the redesign, and the product performance is greatly influenced.
Therefore, there is a need to provide a novel chip package and MEMS device package to solve the above problems in the prior art.
Disclosure of Invention
The invention aims to provide a chip package and an MEMS device package, which can change the pin arrangement mode of a chip to form a new pin arrangement structure, facilitate the connection and routing of the chip and are compatible with different microphone package structures.
In order to achieve the above object, the chip package of the present invention includes a chip and at least one wiring circuit layer, wherein the surface of the chip is provided with a plurality of initial pins and a plurality of target pins, and at least some of the initial pins and the target pins are electrically connected through the wiring circuit layer;
the chip comprises four side edges, the initial pins are arranged in the areas where any two side edges are located, and the target pins are arranged in the areas where at least one of the rest two side edges is located.
The chip package provided by the embodiment of the invention has the beneficial effects that: the initial pins and the target pins are connected together through the wiring circuit layer arranged on the surface of the chip, and the target pins and the initial pins are respectively distributed in the areas where the four sides of the chip are located.
Optionally, the chip includes a chip base layer and a functional circuit layer, the functional circuit layer is disposed on the surface of the chip base layer, and a first protective layer covers the surface of the functional circuit layer.
Optionally, the wiring circuit layer is disposed within the functional circuit layer.
Optionally, a filling layer is disposed on the surface of the first protection layer, and the filling layer is used for planarizing the surface region of the first protection layer.
Optionally, a metal shielding layer is disposed on a surface of the first protection layer, the initial pin includes a first ground pin, the target pin includes a second ground pin, the first ground pin is connected to the second ground pin through the wiring circuit layer, and the metal shielding layer is connected to the first ground pin or the second ground pin.
Optionally, the metal shielding layer includes any one of aluminum, copper, silver, and iron.
Optionally, the metal shielding layer is a mesh structure.
Optionally, a separation layer located below the wiring circuit layer is disposed above the metal shielding layer, and the separation layer is used for separating the metal shielding layer from the wiring circuit layer.
Optionally, a second protective layer is disposed on the surface of the wiring circuit layer, and the second protective layer at least covers the upper surface of the wiring circuit layer.
The invention also provides an MEMS device package, which comprises the chip package, a circuit substrate and an MEMS chip, wherein the chip package and the MEMS chip are arranged on the surface of the circuit substrate, the surface of the MEMS chip is provided with chip pins, the surface of the circuit substrate is provided with circuit board pins, the chip pins are connected with the initial pins of the chip package through connecting wires, and the circuit board pins are connected with the target pins through connecting wires.
The MEMS device package has the beneficial effects that: in the MEMS device package, the chip pin of the MEMS chip is connected with the initial pin of the chip package silicon structure through the connecting wire, and the circuit board pin is connected with the target pin through the connecting wire, so that the package form can be freely changed according to the shapes and the sizes of the MEMS chip and the circuit substrate, and the MEMS device package with different sizes is compatible.
Optionally, the MEMS chip includes any one of a MEMS microphone chip, a MEMS pressure chip, a MEMS bone conduction chip, and a MEMS inertial sensor chip.
Optionally, the target pin includes a high-frequency pin, and a linear distance between the high-frequency pin and the MEMS chip is greater than a linear distance between other pins in the target pin and the MEMS chip.
Drawings
Fig. 1 is a schematic diagram of a first structure of a chip package according to an embodiment of the invention;
fig. 2 is a schematic diagram of a second structure of the chip package according to the embodiment of the invention;
fig. 3 is a schematic diagram of a package structure when a chip in the chip package is an ASIC chip according to an embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a first structure of a chip package according to an embodiment of the present invention;
FIG. 5 is a first cross-sectional view of A-A in a first configuration of a chip package according to an embodiment of the invention;
FIG. 6 is a second cross-sectional view of A-A in the first configuration of the chip package according to the embodiment of the invention;
FIG. 7 is a schematic cross-sectional view of a third cross-section A-A of the first configuration of the chip package according to the embodiment of the invention;
FIG. 8 is a fourth cross-sectional view of A-A in the first configuration of the chip package according to the embodiment of the invention;
FIG. 9 is a schematic cross-sectional view of a fifth configuration of a-A of a chip package according to an embodiment of the invention;
FIG. 10 is a schematic diagram of a first structure of a MEMS device package in accordance with an embodiment of the present invention;
fig. 11 is a schematic diagram of a second structure of a MEMS device package according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides a chip package, as shown in fig. 1, including a chip 10 and at least one wiring circuit layer 30, where a plurality of initial pins 20 and a plurality of target pins 40 are disposed on a surface of the chip 10, and the initial pins 20 and the target pins 40 are electrically connected through the wiring circuit layer 30;
the chip 10 includes four side edges 101, the initial pins 20 are disposed in the regions where any two of the side edges 101 are located, and the target pin 40 is disposed in the region where at least one of the other two side edges 101 is located.
The initial pins 20 and the target pins 40 are connected together through the wiring circuit layer 30 arranged on the surface of the chip 10, and the target pins 40 and the initial pins 20 are respectively distributed in the areas where the four sides 101 of the chip are located, so that when the chip 10 is actually packaged and wired, the target pins 40 and the initial pins 20 can be freely selected according to actual conditions for wiring connection, and thus, the packaging of different sizes can be compatible.
In this embodiment, the initial pin 20 may be disposed in the region where the two parallel side edges 101 are located, or may be disposed in the region where the two perpendicular side edges 101 are located, and the setting position of the target pin 40 is determined according to the setting position of the initial pin 20, which is not described herein again.
In fig. 1, the initial pins 20 are distributed in the areas where two parallel sides 101 of the chip are located, but the present solution is not limited thereto, and in some embodiments, referring to fig. 2, the initial pins 20 may also be distributed on two perpendicular sides 101 of the chip 10, and the target pin 40 is connected to the initial pin 20 on one of the two perpendicular sides 101 through the routing circuit layer 30, so that the target pin 40 and the remaining initial pins 20 are arranged in parallel, which is not described herein again.
It should be noted that, in the chip package structure of this embodiment, there are two preparation methods for the target pin 40 in the chip package, the first method is to design the initial pin 20 and the target pin 40 on the chip 10 during chip design, and then package the chip 10 through the wiring circuit layer 30 to connect the target pin 40 and a part of the initial pin 20, and the initial pin 20 and the target pin 40 are connected through the wiring circuit layer 30 inside the chip 10, so as to change the position of the pins in the chip package, and conveniently and flexibly select the initial pin 20 and/or the target pin 40 for routing according to different package forms.
Specifically, in the present embodiment, the initial pin 20 and the target pin 40 are both disposed inside the chip 10, so that the initial pin 20 and the target pin 40 are connected together through the wiring circuit layer 30 inside the chip 10, and routing is facilitated.
In the second mode, only the initial pin 20 is designed during the initial design of the chip 10, after the wafer manufacturing of the chip 10 is completed and before the wafer is diced, the wiring design of the wiring circuit layer 30 is performed on the surface of the chip 10, one end of the wiring circuit layer 30 is connected with at least part of the initial pin 20, and the target pin 40 is manufactured at the other end of the wiring circuit layer 30, so that the manufacturing process of the whole chip is completed, the wiring position in the chip packaging is changed through the target pin 40, the wiring through the initial pin 20 and the target pin 40 is facilitated, and the wiring is facilitated.
In this embodiment, referring to fig. 3, the chip 10 is an ASIC chip, taking as an example that the initial pins 20 of the ASIC chip are disposed on two upper and lower parallel side edges 101, because the initial pins 20 of the ASIC chip are respectively arranged in the areas where the first side edge 1011 and the second side edge 1012 are disposed, and the target pin 40 is disposed in the area where the third side edge 1013 perpendicular to the first side edge 1011 or the second side edge 1012 is disposed or the area where the fourth side edge 1014 is disposed, the target pin 40 is connected to the initial pins 20 through the wiring circuit layer 30, so that in the subsequent wiring package, for the package structures with different sizes, the initial pins 20 and the target pins 40 at different positions can be freely selected for wiring package, and different package requirements can be met.
In some embodiments, the structure of the chip on wafer is shown in fig. 4.
In some embodiments, referring to fig. 5, the chip 10 includes a chip base layer 1 and a functional circuit layer 2, the functional circuit layer 2 is disposed on a surface of the chip base layer 1, and a surface of the functional circuit layer 2 is covered with a first protection layer 3.
In the present embodiment, since the initial pin 20 on the surface of the chip 10 is connected to the functional circuit layer 2, in order to protect the functional circuit layer 2, the first protection layer 3 is disposed on the surface of the functional circuit layer 2 to protect the functional circuit layer 2.
Specifically, the first protection layer 3 is a passivation material layer.
Further, referring to fig. 6, a second protective layer 5 is disposed on a surface of the wiring circuit layer 30, and the second protective layer 5 covers at least an upper surface of the wiring circuit layer 30.
After the wiring circuit layer 30 is disposed to connect the initial pin 20 and the target pin 40, since the wiring circuit layer 30 is disposed on the surface of the chip 10, the second protection layer 5 is disposed on the surface of the wiring circuit layer 30, so as to protect the wiring circuit layer 30.
In other embodiments, referring to fig. 7, the surface of the first protection layer 3 is provided with a filling layer 6, and the filling layer 6 is used for planarizing the surface region of the first protection layer 3.
Because the functional circuit layer 2 of the ASIC chip is generally formed by stacking a plurality of different circuit patterns, a height difference, generally several to tens of micrometers, is formed on the surface of the ASIC chip, and when the height difference is large, the height difference also exists on the surface of the target pin 40 connected with the wiring circuit layer 30 after the wiring circuit layer 30 is directly formed on the surface of the chip 10, and during packaging and routing, gold balls fall off or routing is not uniform due to the uneven surface of the target pin 40.
In this embodiment, before the wiring circuit layer 30 is formed, a filling layer 6 is deposited on the surface of the first protection layer 3, the surface of the chip 10 is more planarized by the filling layer 6, and the height difference is reduced, so that the height difference between the subsequently formed wiring circuit layers 30 is reduced, and the problems of gold ball falling or wire bonding inequality during subsequent packaging and wire bonding are avoided.
Specifically, the thickness of the filling layer 6 is usually 5um or more, so as to completely fill up the grooves or protrusions formed on the surface of the chip 10.
In some embodiments, referring to fig. 8, on the basis of fig. 6, a second protective layer 5 is provided on the surface of the wiring circuit layer 30 while a filling layer 6 is provided on the surface of the first protective layer 3, and the second protective layer 5 covers at least the upper surface of the wiring circuit layer 30.
By arranging the second protective layer 5 on the wiring circuit layer 30, the whole wiring circuit layer 30 is protected, and the damage of the wiring circuit layer 30 can be reduced, in this embodiment, the second protective layer 5 is a passivation material layer or an encapsulation adhesive.
The second protective layer 5 may completely cover the surface of the chip 10 except for the target pins 40 and the initial pins 20, or may cover only the upper surface of the wiring circuit layer 30, so as to protect the wiring circuit layer 30 and save materials.
In some embodiments, referring to fig. 9, the surface of the first protection layer 3 is provided with a metal shielding layer 7, the initial pin 20 includes a first ground pin 201, the target pin 40 includes a second ground pin (not labeled), the first ground pin 201 is connected to the second ground pin through the routing circuit layer 30, and the metal shielding layer 7 is connected to the first ground pin 201 or the second ground pin.
In the process of forming the wiring circuit layer 30 on the surface of the chip 10, since the trace between the initial pin 20 and the target pin 40 may cross different functional areas of the chip, such as a speaker module, a communication module, a cache module, and a filter module, when the chip is in operation, the electrical signal in the wiring circuit layer 30 may interfere with each other, which may affect the performance of the product. For this purpose, before the wiring circuit layer 30 is formed, the metal shielding layer 7 is formed on the surface of the first protection layer 3, and the metal shielding layer 7 is connected to the first ground pin 201 or the second ground pin, and the first ground pin 201 or the second ground pin is used as a ground pin, so that the metal shielding layer 7 is grounded, and the interference of the external signal and the signal generated by the wiring circuit layer 30 to the functional circuit layer 2 inside the chip 10 is shielded by the metal shielding layer 7.
In some embodiments, the metal shielding layer 7 comprises any one of aluminum, copper, silver, and iron. The scheme is not limited to the above, and materials capable of being used for electromagnetic shielding can be used, and are not described in detail here.
In still other embodiments, the metal shielding layer 7 is a mesh structure.
In other embodiments, a separation layer 8 is disposed above the metal shielding layer 7 and below the wiring circuit layer 30, and the separation layer 8 is used for separating the metal shielding layer 7 and the wiring circuit layer 30. The separation layer 8 is a non-conductive passivation material comprising SiO2SiNx and PI.
The metal shielding layer 7 and the wiring circuit layer 30 are separated from each other by the separation layer 8, so that short circuit between the metal shielding layer 7 and the wiring circuit layer 30 is effectively avoided, and the wiring circuit layer 30 is protected.
And through set up metal shield 7 and separating layer 8 on first protective layer 3 surface, not only can play the shielding and avoid the effect of short circuit, metal shield 7 and separating layer 8 can fill up chip 10 surface moreover to reduce the difference in height between the subsequent wiring circuit layer 30 that forms, appear gold ball and drop or the routing is not equal problem when avoiding follow-up encapsulation routing.
It should be noted that, in this embodiment, although the initial pin 20 and the target pin 40 on the chip 10 are connected through the wiring circuit layer 30, the upper side of the initial pin 20 is not covered by a non-conductive material such as a protection layer, a filling layer, or a separation layer, so that in the MEMS sensor package, not only the initial pin 20 may be used for routing, but also the target pin 40 connected to the initial pin 20 may be used for routing, so as to meet the requirements of MEMS device packages of different sizes, and details are not repeated here.
The invention also provides an MEMS device package, referring to FIG. 10, comprising the chip package, a circuit substrate 50 and an MEMS chip 60, wherein the chip package and the MEMS chip 60 are both arranged on the surface of the circuit substrate 50, a chip pin 601 is arranged on the surface of the MEMS chip 60, a circuit board pin 501 is arranged on the surface of the circuit substrate 50, the chip pin 601 is connected with an initial pin 20 of the chip package through a connecting wire, and the circuit board pin 501 is connected with a target pin 40 through a connecting wire.
In this embodiment, taking the ASIC chip as an example of the chip package, the chip package and the MEMS chip 60 are both mounted on the circuit substrate 50, and the package and routing requirements of the MEMS sensing devices with different sizes can be met by using the above chip package.
Referring to fig. 10, taking the example of parallel arrangement of the pins of the ASIC chip, since the width of the circuit substrate 50 in the vertical direction is greater than the width in the horizontal direction, the MEMS chip 60 and the chip package are mounted on the circuit substrate 50 in a top-bottom wiring manner. When the circuit substrate 50 has a small size in the length direction and the chip arrangement and routing distances are limited, the initial pin 20 of the ASIC chip is connected to the target pin 40 on the side surface through the wiring circuit layer 30, when the wiring is installed, the chip pin 601 of the MEMS chip 60 located above is connected to the initial pin 20 above the ASIC chip through a connecting wire, and the circuit board pin 501 of the circuit substrate 50 is directly connected to the target pin 40 on the side surface through a connecting wire, so that the chip packaging can be completed when the size of the circuit substrate 50 is limited, and the packaging requirements of different sizes can be met.
It should be noted that the chip pin 601 of the MEMS chip 60 may be connected to the initial pin 20 of the ASIC chip, or one pin may be led out from the initial pin 20 of the ASIC chip, and then the chip pin 601 of the MEMS chip 60 is connected to the led-out pin. Because the target pins and the initial pins are on different planes and have height difference, all the target pins 40 are arranged on the same plane, so that the routing and height measurement are convenient during packaging.
In other embodiments, the MEMS chip 60 includes any one of a MEMS microphone chip, a MEMS pressure chip, a MEMS bone conduction chip, and a MEMS inertial sensor chip, which is not particularly limited in this embodiment.
In some embodiments, the target pins 40 include high frequency pins 401, and a linear distance between the high frequency pins 401 and the MEMS chip 60 is greater than a linear distance between other ones of the target pins 40 and the MEMS chip 60.
The high-frequency pins 401 correspond to the pins of the high-frequency electric signals in the initial pins 20, and comprise VDD pins, DATA pins and CLK pins, and the high-frequency pins 401 are far away from the MEMS chip 60, so that the electric signals are prevented from interfering the MEMS chip 6, and the overall product compatibility is effectively improved.
Referring to fig. 11, when the distance of the circuit substrate 50 in the width direction is small and the routing distance of the ASIC chip on the side is limited, the initial pins 20 are not covered by the non-conductive material, so that the circuit board pins 501 can be connected with the initial pins 20 below the ASIC chip, thereby facilitating routing, satisfying the packaging requirements of MEMS devices of different sizes, and reducing the process difficulty.
The invention provides a MEMS sensor device comprising the MEMS device package described above.
The MEMS sensor equipment is manufactured by adopting the MEMS device package, so that the compatibility of the MEMS sensor equipment in the packaging process can be effectively improved.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (12)

1. The chip package is characterized by comprising a chip and at least one wiring circuit layer, wherein the surface of the chip is provided with a plurality of initial pins and a plurality of target pins, and at least part of the initial pins and the target pins are electrically connected through the wiring circuit layer;
the chip comprises four side edges, the initial pins are arranged in the areas where any two side edges are located, and the target pins are arranged in the areas where at least one of the rest two side edges is located.
2. The chip package according to claim 1, wherein the chip comprises a chip base layer and a functional circuit layer, the functional circuit layer is disposed on a surface of the chip base layer, and a surface of the functional circuit layer is covered with a first protective layer.
3. The chip package of claim 2, wherein the routing circuit layer is disposed within the functional circuit layer.
4. The chip package of claim 2, wherein the first protective layer surface is provided with a filler layer for planarizing the first protective layer surface area.
5. The chip package according to claim 2, wherein the first protection layer is provided with a metal shielding layer on a surface thereof, the initial pin comprises a first ground pin, the target pin comprises a second ground pin, the first ground pin is connected to the second ground pin through the routing circuit layer, and the metal shielding layer is connected to the first ground pin or the second ground pin.
6. The chip package according to claim 5, wherein the metal shielding layer comprises any one of aluminum, copper, silver, and iron.
7. The chip package according to claim 5, wherein the metal shielding layer is a mesh structure.
8. The chip package according to claim 5, wherein a separation layer is disposed between the metal shielding layer and the wiring circuit layer, and the separation layer is used for separating the metal shielding layer and the wiring circuit layer.
9. The chip package according to any one of claims 4 to 8, wherein the surface of the wiring circuit layer is provided with a second protective layer, and the second protective layer covers at least the upper surface of the wiring circuit layer.
10. An MEMS device package, comprising the chip package according to any one of claims 1 to 9, further comprising a circuit substrate and an MEMS chip, wherein the chip package and the MEMS chip are disposed on a surface of the circuit substrate, a chip pin is disposed on a surface of the MEMS chip, a circuit board pin is disposed on a surface of the circuit substrate, the chip pin is connected to an initial pin of the chip package through a connection line, and the circuit board pin is connected to a target pin through a connection line.
11. The MEMS device package of claim 10, wherein the MEMS chip comprises any one of a MEMS microphone chip, a MEMS pressure chip, a MEMS bone conduction chip, a MEMS inertial sensor chip.
12. The MEMS device package of claim 10, wherein the target pin comprises a high frequency pin, and wherein a linear distance between the high frequency pin and the MEMS chip is greater than a linear distance between other ones of the target pin and the MEMS chip.
CN202210138903.0A 2022-02-15 2022-02-15 Chip package and MEMS device package Pending CN114512458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210138903.0A CN114512458A (en) 2022-02-15 2022-02-15 Chip package and MEMS device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210138903.0A CN114512458A (en) 2022-02-15 2022-02-15 Chip package and MEMS device package

Publications (1)

Publication Number Publication Date
CN114512458A true CN114512458A (en) 2022-05-17

Family

ID=81550903

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210138903.0A Pending CN114512458A (en) 2022-02-15 2022-02-15 Chip package and MEMS device package

Country Status (1)

Country Link
CN (1) CN114512458A (en)

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