CN114501781A

CN114501781A - Plasma etch catalytic laminate with traces and vias

Info

Publication number: CN114501781A
Application number: CN202210060248.1A
Authority: CN
Inventors: 肯尼斯·S·巴尔; 康斯坦丁·卡拉瓦克斯
Original assignee: Katram LLC
Current assignee: Katram LLC
Priority date: 2016-08-18
Filing date: 2017-08-16
Publication date: 2022-05-13
Also published as: EP3501242A4; CN109906670A; EP3501242A1; KR20220070580A; KR20190049736A; WO2018035184A1; KR102649271B1

Abstract

The present application relates to plasma etched catalytic laminates having traces and vias. The circuit board is formed from a catalytic laminate having a resin-rich surface with catalytic particles dispersed below the surface exclusion depth. The catalytic laminate is subjected to a drilling and blanket surface plasma etching operation to expose the catalytic particles, followed by an electroless plating operation to deposit a thin layer of conductive material on the surface. A photomask step then defines the circuit traces, after which a plating deposition occurs, followed by a resist strip operation and a rapid etch to remove the electroless copper previously covered by the photoresist.

Description

Plasma etch catalytic laminate with traces and vias

The present application is a divisional application of the application entitled "plasma etch catalytic laminate with traces and vias" filed as 2017, 08, 16, and application No. 201780064641.5.

Technical Field

The present invention relates to a catalytic laminate and its use in the manufacture of circuit boards. In particular, the laminate has the property of providing fine pitch circuit interconnects that may be formed on the surface of the catalytic laminate or in the grooves to form a circuit board layer having a planar surface embedded with surface conductors or having surface conductors.

Background

Prior art Printed Circuit Boards (PCBs) are formed using conductive metal interconnects (referred to as "traces") formed on a dielectric substrate, with each surface carrying conductors being referred to as a "layer". Each dielectric core has traces formed on one surface or on both surfaces, and by stacking several such dielectric cores (with traces formed in them interspersed with bare dielectric layers) and laminating them together under temperature and pressure, a multilayer printed circuit can be formed. The dielectric substrate comprises an epoxy resin embedded in a fiber matrix, such as glass fibers woven into a cloth. In one prior art fabrication method, copper is laminated onto the outer surface of a dielectric layer, the copper surface is patterned (such as with a photoresist or photosensitive film) to create masked and unmasked areas, and then etched to form a conductive trace layer on one or both sides of the core dielectric. The stack of dielectric cores with conductive traces can then be laminated together to form a multilayer board and any layer interconnects (layer interconnects) made with vias that are drilled holes plated with copper to form annular rings that provide connections from one layer to another.

Printed Circuit Boards (PCBs) are commonly used to provide electrically conductive traces between various electronic components mounted on the PCB. A through-hole device for mounting one type of electronic component on a PCB by positioning leads through one or more holes in the PCB, wherein the PCB holes include a conductive annular ring pad on each trace connection layer and the component leads are soldered to the annular ring pads of the PCB holes. Through-hole components have leads that tend to be difficult to align with the associated PCB mounting holes, but Surface Mount Technology (SMT) provides a preferred mounting system in which component leads are simply placed on the surface of a PCB pad and soldered, which is preferred for PCB assembly due to higher density and ease of mechanized assembly. The surface mount components require only surface mount pads on the outer finished PCB layer. In two or more layer PCBs, the interconnection of conductive traces from one layer to another is accomplished using vias, where the conductive traces on one trace layer lead to holes that are typically drilled through one or more dielectric layers of the PCB and plated with copper or other conductive metal to complete the trace layer connections. Holes drilled through all dielectric layers are referred to as through-holes (thru-via), holes drilled through only the outer layers (typically as part of the fabrication of the individual layers) are referred to as micro-vias (micro-via), and holes drilled through one or more inner layers are referred to as blind-vias. For any of these via types, the vias are patterned to include annular ring conductor regions on opposite trace layers of the PCB, and the bore holes are lined with conductive material that connects the annular ring conductors on either side of the laminate or PCB.

Electroplating may be used to increase the thickness of the copper before or after patterning on the printed circuit board laminate, where a PCB or dielectric layer with traces is placed in an electrolytic bath and a DC source is connected between a sacrificial anode conductor (such as a copper bar) and the existing conductive layer of the PCB. In the absence of a pre-existing conductive copper layer on the PCB for ease of electroplating (such as in the case of bare dielectric material or drilled through holes), a seed layer of copper must first be deposited. This is done using an electroless plating process that is electroless plated with a "seed" catalytic material (which enhances the deposition of certain conductive materials) deposited on the surface of the dielectric, and then the plate is placed in an electroless plating solution. For catalysts such as electroless solutions of copper and palladium, copper ions in solution are deposited on the palladium until the surface is sufficiently covered to provide uniform conductivity, after which the copper deposited using the electroless plating process provides a conductive support for subsequent addition of material using the electroplating process. Electroplating is preferred for accomplishing the electroplating operation because it has a faster deposition rate than electroless plating processes.

As electronic assemblies increase in complexity, it is desirable to increase component density on PCB assemblies, such as by using smaller trace widths (referred to as fine pitch traces) in conjunction with increasingly dense Integrated Circuit (IC) lead patterns. One problem with prior art surface mount PCB manufacturing and assembly methods is that because the traces are formed on the surface of the dielectric, for narrower conductor line widths (referred to as fine pitch traces), the adhesion between the copper traces and the underlying laminate is reduced, causing the fine pitch traces and component pads to separate (lift up) during component replacement operations, damaging the entire circuit board assembly and the expensive components thereon. Another problem with fine pitch surface traces is that when manufacturing a multilayer circuit board, the individual trace layers are laminated together under pressure in a high temperature environment. During lamination, fine pitch traces tend to migrate laterally across the surface of the dielectric. In high speed circuit designs, it is desirable to maintain a fixed impedance between the traces, especially for differential pair (edge-coupled) transmission lines. This lateral migration of the traces during lamination causes the transmission line impedance of the finished PCB differential pair to vary with the length of the traces, which causes kink and loss in the transmission line compared to a transmission line with a fixed impedance characteristic resulting from a constant pitch.

It is desirable to form the traces with a combination of catalytic prepreg material that provides a blanket etched surface that exposes catalytic particles, followed by electroless plating to provide a conductive deposition layer, followed by electroless plating to form traces of a desired thickness for fine trace linewidths and trace separations. It is also desirable to provide a catalytic prepreg for use in printed circuit processing, wherein the catalytic prepreg has a non-catalytic surface and removal of the surface of the catalytic prepreg exposes catalytic particles for forming traces in areas where the facing material has been removed.

Object of the Invention

A first object of the invention is a catalytic prepreg comprising catalytic particles, wherein the catalytic prepreg hides the catalytic particles under a resin rich outer surface that does not expose the catalytic particles unless the outer surface of the catalytic prepreg has been removed, wherein the surface removal can be accomplished using any of laser cutting, mechanical abrasion, mechanical cutting, chemical or plasma etching, or any other means of removing the outer surface of the prepreg and exposing the underlying catalytic particles below the surface of the prepreg, after which traces are formed by drilling and performing blanket etching on the surface, plating the entire surface, patterning the surface with photoresist, plating the surface without photoresist, stripping the photoresist and etching rapidly for a sufficient time to remove the exposed electroless copper plating.

A second object of the invention is a process for making a catalytic prepreg having a resin-rich outer surface free of exposed catalytic particles and a catalyst-rich layer below the resin-rich outer surface, wherein the catalytic prepreg is formed using a process having the steps of:

a fiber impregnation step in which a fiber cloth is impregnated with a catalytic resin formed by mixing a resin with catalytic particles;

a vacuum compression step performed at high temperature, whereby the outer surface of the fibre cloth impregnated with catalytic resin is subjected to an externally applied pressure in ambient vacuum conditions during a temperature ramp-up time;

a gel point step whereby an applied pressure is maintained on the outer surface of the fibre cloth impregnated with the catalytic resin to maintain a liquid/solid equilibrium for a duration sufficient for the catalytic particles to be wicked away from the outer surface;

a dwell step whereby an elevated temperature is applied to the laminate at the gel point temperature for a dwell time duration;

a cooling step whereby the fiber cloth impregnated with the catalyzed resin is cooled to a substantially flat sheet.

Summary of The Invention

In a first embodiment of the invention, the catalytic prepreg is formed by: mixing resin, volatile solvent and catalytic particles to form a catalytic resin mixture, infusing catalytic resin into a fiber fabric (such as woven glass fiber) or other fabric, to form an "a-stage" catalytic prepreg, the fibers and resin are baked together at elevated temperatures to remove most of the volatile solvents and form a partially cured "B-staged" catalyzed prepreg such as in sheet form, the B-stage prepreg is then placed in a laminator and heated at the gel point, so that the prepreg is in liquid/solid equilibrium, the prepreg is thereafter cured at elevated temperature and pressure for a residence time sufficient to allow the catalytic particles to migrate away from the outer surface of the prepreg and form a finished "C-stage" prepreg having a resin-rich surface free of exposed surface catalytic particles. The resin-rich surface is mechanically removed, thereby exposing the underlying catalytic particles to form a surface suitable for electroless plating using copper ions in solution or any suitable electroless metal ions in solution.

In a second embodiment of the invention, a single or multi-layer PCB is formed by patterning an exposed surface onto a catalytic prepreg having a resin rich surface that excludes catalytic particles from the surface, wherein the catalytic particles are distributed below the resin rich surface and are not exposed. In a first step, the catalytic particles are exposed by removing the surface of the material using any of these techniques, with or without a pattern mask, using any removal means, including laser ablation, plasma etching, chemical etching, mechanical abrasion or cutting. In a second step, the catalytic laminate is placed in an electroless plating bath, where the electroless plated metal (such as Cu) is attracted to and binds to the exposed catalytic particles (such as Pt) in the patterned areas where the resin rich surface has been removed. The second step continues until the electroless plating fills the sides and bottoms of the patterned trenches to the level of the surrounding native surface of the catalytic laminate with the electroplated metal. In an optional third step, the surface of the patterned trench is planarized, such as by polishing, grinding, machining or etching, to match the electroless plating level to the surrounding native surface of the catalytic laminate. In an optional third or fourth step, a solder mask layer is applied to cover the area of the catalytic laminate and the area of the patterned traces.

In a third embodiment of the invention, the catalytic prepreg of the first embodiment has holes formed by drilling or ablation or other means for removing material to form holes in the catalytic prepreg adjacent to the pad area where the surface of the catalytic prepreg adjacent to the holes is removed to expose the underlying catalytic particles of the catalytic prepreg in the inner surface of the holes and also the outer surface of the catalytic prepreg, which is then plated into an electroless plating bath. The resulting catalyzed prepreg then forms conductive surface traces that are electrically connected to conductive vias, which may optionally form component mounting pads. The vias may also include conductive surface traces on opposite sides of the catalytic prepreg, wherein the first surface trace, the vias, and the second surface trace are all produced in a single electroless plating step. After electroless plating, the outer surface of the catalytic laminate may be planarized such that the conductive traces are flush with the natural surface of the catalytic laminate, such that the individual layers of the catalytic laminate with traces formed thereon may be stacked and laminated into a multi-layer PCB.

In a fourth embodiment of the present invention using a conventional non-catalytic prepreg, a single or multi-layer PCB is formed by a process having a first step of applying a catalytic adhesive to one or both sides of the non-catalytic prepreg, wherein the catalytic adhesive comprises a resin mixed with catalytic particles and forms a catalytic adhesive layer on the non-catalytic prepreg. In a second step, the catalytic prepreg surface layer is selectively partially removed, such as by using a plasma cleaning or plasma etching process for a duration sufficient to expose the catalytic particles while leaving the underlying binder resin securing the catalytic particles to the non-catalytic prepreg. In a third step, the partially removed or etched catalytic binder is exposed to electroless plating using metal ions bound to the catalytic particles in solution, which is performed until a substantially continuous conductive layer of metal is deposited. In a fourth step, a pattern mask is applied, which provides open areas where traces are needed. In the fifth step, the continuous conductive layer is used as an electrode for electroplating in a metal plating solution, so that metal ions in the solution are electrodeposited onto the patterned exposed conductive layer formed in the third step electroless deposition. In a sixth step, the pattern mask is stripped away and in a seventh step, a quick etch is performed for a sufficient time to remove the electroless plating in the previously unexposed areas under the pattern mask.

In a fifth embodiment of the invention, the electrically conductive vias are formed in the non-catalytic laminate by: forming a first hole in a non-catalytic laminate (optionally adjacent to a first pad or a second pad formed by a conductor on a first surface or a second surface of the non-catalytic laminate), filling the first hole with a catalytic resin or a catalytic adhesive, allowing the catalytic resin or adhesive to cure, drilling a second hole in the first hole that is smaller in diameter than the hole, and electrolessly plating the second hole and surrounding pads, thereby forming a connection from an inner surface of the second hole to the first pad or the second pad.

In a sixth embodiment of the invention, the non-catalytic laminate layer has a catalytic adhesive applied, the catalytic adhesive comprising resin and catalytic particles, the catalytic adhesive having a thickness at least two times greater than the largest catalytic particles in the adhesive, the catalytic adhesive curing and developing a resin rich surface and an exclusion zone below the resin rich surface in which the catalytic particles are excluded, removal of the resin rich surface providing exposed catalytic particles suitable for electroless plating, the non-catalytic laminate optionally further having pores that can be filled with the catalytic adhesive and drilled to provide exposed catalytic particles for electroless plating of the drilled pores together with conductive traces formed by electroless copper deposition.

In a seventh embodiment of the invention, a catalytic laminate has a catalytic adhesive applied to at least one surface, the catalytic laminate comprising a prepreg with catalytic particles, the adhesive comprising resin and catalytic particles, the catalytic adhesive and the catalytic laminate being drilled to form through holes, traces being patterned on the surface of the catalytic adhesive by removing a surface layer of the catalytic adhesive, and thereafter forming traces by electroless plating on the patterned traces, and thereafter planarizing the at least one surface.

In an eighth embodiment of the present invention, a circuit board is formed by: blanket etching the catalytic prepreg to expose the catalytic particles below the exclusion depth, drilling through holes, electroless plating the circuit board, patterning the circuit board with photoresist, electroplating the circuit board to form traces on areas not coated with photoresist, thereafter removing the photoresist, and rapidly etching the exposed electroless copper to form the circuit board with traces.

The present application further provides the following:

1) a process for forming conductive traces on a catalytic laminate having a resin-rich surface with an insufficient density of catalytic particles for surface chemical plating, the catalytic laminate having catalytic particles dispersed below a sufficient catalytic particle exclusion depth for electroless plating when exposed, the process comprising:

drilling holes in the catalytic laminate;

etching the outer surface of the catalytic laminate until the catalytic particles are exposed;

electrolessly plating the catalytic laminate until a conductive metal is plated on the outer surface and also within the drilled hole;

applying a pattern mask to the outer surface of the catalytic laminate;

electrolessly plating an outer surface of the catalytic laminate;

stripping the pattern mask;

the circuit board is quickly etched sufficient to remove any previously masked electroless plated conductive metal.

2) The process of 1), wherein the electroless plating and the electroplating deposit copper.

3) The process of 1), wherein the thickness of the electroplated deposit is greater than the thickness of the electroless deposit.

4) The process of 1), wherein the pattern mask is a dry film.

5) The process of 1), wherein the pattern mask is a liquid photoresist.

6) The process of 1), wherein plasma etching the outer surface uses at least one of: reactive plasma, chemical etchant, laser cutting, water jet cutting, mechanical abrasion, or mechanical cutting.

7) The process of 1), wherein the exclusion depth is less than 25 u.

8) The catalytic laminate of 1), wherein the catalytic particles are non-uniform.

9) The catalytic laminate of 8), wherein the catalytic particles comprise a filler coated with a catalyst.

10) The catalytic laminate of claim 9), wherein the filler is at least one of: clay minerals, hydrated aluminosilicates, silica, kaolinite, polysilicates, members of the kaolin or china clay families or high-temperature plastics.

11) The catalytic laminate of claim 9), wherein the particle size is on the order of 3u or less than 3 u.

12) The catalytic laminate of 9), wherein the ratio of the catalytic particles to the resin by weight is in the range of 8% to 16%.

13) The catalytic laminate of claim 9), wherein the catalytic particles are silica or kaolin coated with a catalytic material.

14) The catalytic laminate of claim 9), wherein the catalyst is palladium.

15) The catalytic laminate of claim 9), wherein the catalyst is at least one of: palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu) or other compounds or salts thereof.

16) The catalytic laminate of 1), wherein the catalytic particles are uniform.

17) The catalytic laminate of claim 16), wherein the catalyst is palladium.

18) The catalytic laminate of 16), wherein the catalyst is at least one of: palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu) or other compounds or salts thereof.

19) The catalytic laminate of 16), wherein a majority of the catalytic particles have a size of less than 25 u.

Brief Description of Drawings

FIG. 1A shows a schematic of a process for forming a pristine catalytic prepreg.

FIG. 1B illustrates a vacuum laminator for forming a finished catalytic prepreg from a starting catalytic prepreg.

Figure 1C shows a vacuum lamination stage for forming the layers of catalytic prepreg during lamination.

Fig. 2 shows the processing time of the vacuum lamination step of fig. 1.

Figure 3 illustrates the process steps for forming the catalytic prepreg.

FIG. 4 shows a graph of the distribution of catalytic particles in the prepreg versus a cross-sectional view of the prepreg.

FIG. 5A shows a cross-sectional view of a natural catalytic prepreg.

Fig. 5B shows a cross-sectional view of the catalytic prepreg after the surface removal step.

Fig. 5C shows a cross-sectional view of the catalytic prepreg during the electroless plating step during a time sequence.

Fig. 5D shows a cross-sectional view of the catalytic prepreg after the surface smoothing step.

FIG. 5E shows a cross-sectional view of the catalyzed prepreg after the solder mask step.

Fig. 5F shows a cross-sectional view of a prior art etched copper trace on a non-catalytic prepreg.

Fig. 6A shows a cross-sectional view of a catalytic adhesive applied to a non-catalytic prepreg.

Fig. 6B shows the cross-sectional view of fig. 6A after a plasma etching step.

Fig. 6C shows a cross-sectional view of electroless plating on a pre-impregnated substrate.

Figure 6D shows a cross-sectional view of a mask material patterned on a prepreg substrate.

Fig. 6E shows a cross-sectional view of a copper plating on a prepreg substrate.

Fig. 6F shows a cross-sectional view of the copper plating after stripping the mask.

Fig. 6G shows a cross-sectional view of the pre-impregnated substrate after rapid etching to remove the surface copper.

Figure 7A shows a cross-sectional view of a non-catalytic prepreg with foil lamination.

Fig. 7B shows a cross-sectional view of the etched non-catalyzed prepreg after patterning.

Figure 7C shows a cross-sectional view of the non-catalytic prepreg after holes are drilled.

FIG. 7D shows a cross-sectional view of the non-catalytic prepreg after filling the holes with catalytic filler.

Figure 7E shows a cross-sectional view of the non-catalytic prepreg after drilling the second annular hole.

FIG. 7F shows a cross-sectional view of the non-catalytic prepreg after electroless plating of the annular holes.

Fig. 7G shows a perspective transparent view of a via formed using the process of fig. 7A-7F.

Fig. 8A shows a cross-sectional view of a non-catalytic pre-impregnated laminate.

Fig. 8B shows fig. 8A after application of the catalytic adhesive.

Fig. 8C shows fig. 8B after a drilling/punching operation.

Fig. 8D shows fig. 8C after a surface removal operation.

Fig. 8E shows fig. 8D after an electroless plating operation.

Fig. 9A, 9B, 9C, 9D, and 9E show various stages of cross-sectional views of catalytic adhesive applied to a catalytic laminate that has been drilled, etched, electroless plated, and planarized.

Fig. 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, and 10I show various stages of cross-sectional views of a catalytic laminate having traces formed on exposed catalytic surfaces.

Detailed description of the invention

Fig. 1A shows an example process for making prepreg (a matrix of prepreg fibers incorporated in resin). Many different materials may be used for the fibers of the prepreg, including woven fiberglass cloth, carbon fibers, or other fibers, and a variety of different materials may be used for the resin, including epoxy, polyimide, cyanate ester, PTFE (teflon) blend, or other resins. One aspect of the invention is a printed circuit board laminate capable of supporting fine pitch conductive traces on the order of 1 mil (25u), and although the description focuses on the formation of copper traces using a catalyst for electroless copper formation, it should be understood that the scope of the invention can be extended to other metals suitable for electroless plating and electroplating. For the electroless deposition of copper (Cu) channels, the element palladium (Pd) is preferred as catalyst, however selected transition metal elements of the periodic table, such as platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co) or copper (Cu), or other compounds of these, including other metals such as iron (Fe), manganese (Mn), chromium (Cr), molybdenum (Mo), tungsten (W), titanium (Ti), tin (Sn)) or mixtures or salts of any of the above may be used as catalytic particles. The present candidate list is intended to be exemplary rather than comprehensive, and other catalysts for attracting copper ions may be used as known in the art. In one example of the present invention, the catalytic particles are homogeneous catalytic particles. In another example of the invention, the catalytic particles are inorganic particles or refractory plastic particles coated with catalytic metal of a few angstroms thickness to form a non-uniform catalytic particle with a thin catalytic outer surface encapsulating a non-catalytic inner particle. This formulation may be desirable for larger catalytic particles (such as particles on the order of 25u in longest dimension). The heterogeneous catalytic particles of this formulation may include inorganic, organic or inert fillers such as silica (SiO2), inorganic clays such as kaolin, or high temperature plastic fillers coated on the surface with a catalyst such as palladium adsorbed onto the surface of the filler by vapor deposition or chemical deposition. Only a few atomic layers of catalyst are required in order for the catalytic particles to have the desired properties to facilitate electroless plating.

In one example of forming heterogeneous catalytic particles, the (organic or inorganic) filler plating solution is classified by size to include particles less than 25u in size, these classified inorganic particles are mixed in a tank into an aqueous plating solution, stirred, and then a palladium salt such as PdCl (or any other catalyst such as silver salts of other catalysts) is introduced in the presence of an acid such as HCl and in the presence of a reducing agent such as hydrazine hydrate, the mixture thereby reducing the metallic palladium coating the inorganic particles, providing a few angstroms thick Pd coated on the filler, thereby producing non-uniform catalytic particles having the catalytic properties of uniform Pd particles with greatly reduced volume requirements for Pd as compared to the use of uniform Pd metal particles, however, for very small catalytic particles, on the order of a few nm, homogeneous catalytic particles (such as pure Pd) may be preferred.

Exemplary inorganic fillers include clay minerals, such as hydrated aluminosilicates, which may contain variable amounts of iron, magnesium, alkali metals, alkaline earth metals, and other cations. Exemplary inorganic fillers of this family include silica, alumina silicate, kaolinite (Al)₂Si₂O₅(OH)₄) Polysilicates or other clay minerals belonging to the kaolin or china clay families. Example organic fillers include PTFE (teflon) and other polymers with high temperature resistance.

Examples of palladium salts are BrPd, CL₂Pd、Pd(CN)₂、I₂Pd、Pd(NO₃)₂*2H₂O、Pd(NO3)₂、PdSO₄、Pd(NH₃)4Br₂、Pd(NH₃)4Cl₂H₂And O. The catalytic powder of the invention may also comprise a mixture of non-homogeneous catalytic particles (e.g. catalytic material coated on inorganic filler particles), homogeneous catalytic particles (such as elemental palladium) and non-catalytic particles (selected from the inorganic filler family).

Among the catalysts, palladium is the preferred catalyst due to comparative economy, availability and mechanical properties, but other catalysts may also be used.

Fig. 1A shows a roll of fabric cloth 102 (such as woven glass fibers) being fed through as a set of rollers direct the fabric into a tank 108, the tank 108 being filled with an epoxy resin mixed with catalytic particles and mixed with a volatile liquid to reduce viscosity, thereby forming a stage a (liquid) prepreg.

The resin may be a mixture of polyimide resin, epoxy resin and cyanide ester (which provides curing at high temperatures) or any other suitable resin formulation having an optional viscosity during coating and a thermoset upon cooling. Flame retardants may be added, for example, to meet flammability standards or to be compatible with one of the standard FR families of prepregs, such as FR-4 or FR-10. Additional requirements for high speed circuits are the dielectric constant epsilon (permittivity), which is often about 4 and controls the characteristic impedance of the transmission line formed on the dielectric, and the loss tangent delta, which is a measure of the frequency dependent energy absorption over a distance, whereby the loss tangent is a measure of how the dielectric interacts with the high frequency electric field to undesirably reduce the signal amplitude by a calculable amount of dB/cm of the length of the transmission line. The resin is mixed with catalytic particles classified by size. In one example formulation, the catalytic particles comprise at least one of uniform catalytic particles (metallic palladium) or non-uniform catalytic particles (palladium coated on inorganic particles or high temperature plastics), and for either formulation, the catalytic particles preferably have a maximum range of less than 25u, and 50% of the total number of particles have a particle size between 12u and 25u or in the range of 1-25u or less. These are illustrative catalytic particle size examples, which are not intended to limit the scope of the invention. In one exemplary embodiment, the catalytic particles (uniform or non-uniform) are in the size range of 1u-25 u. In another example of the present invention, uniform catalytic particles are formed by grinding metallic palladium into particles and passing the resulting particles through a screen having a mesh with 25u rectangular openings. In another example, catalyzed resin mixture 106 is formed by mixing uniform or non-uniform catalytic particles into a pre-impregnated resin by weight ratio, such as a ratio of substantially 12% by weight of catalytic particles to the weight of resin. The ratio by weight of the catalytic particles in the resin mixture may optionally be in the range of 8-16% by weight of the catalytic particles relative to the total weight of the resin. It will be appreciated that other mixing ratios may be used, and that the use of smaller particles may be preferred. In one example of the invention, the catalytic particle density is selected to provide an average distance between catalytic particles on the order of 3u-5 u.

After immersing the fabric in the catalytic resin bath 106 with the roller 104, the catalytic resin impregnated cloth is directed to the roller 110, the roller 110 establishing the thickness of the uncured liquid stage a prepreg 105, which also establishes the percentage of resin in terms of resin/glass + resin ratio. The A stage prepreg 105 then passes through an oven 103, the oven 103 dislodging the organic and other volatile compounds of the A stage prepreg and substantially reducing the liquid content to form a tack free B stage prepreg 107 that is transported by rollers 111. In an exemplary embodiment, oven 103 dries the volatile compounds from about 80% solvent ratio for the a-stage prepreg to less than about 0.1% solvent ratio for the B-stage prepreg. The resulting B-staged prepreg 107 is provided to a material handling device 111 and may be cut into sheets for ease of handling and storage and then placed into a laminator 126 of fig. 1B that applies pressure under vacuum across the surface of the sheet, changing the temperature profile while the prepreg core is in the laminator, following the temperature profile 202 shown in fig. 2. In one example of the invention, to produce a resin rich surface, a prepreg sheet located near the outer surface (which will later have the surface removed to expose the underlying catalytic particles) is selected to have greater than 65% resin (such as glass 106 (71% resin), glass 1067, or glass 1035 (65% resin)), and an inner prepreg sheet (which is not subjected to surface removal) is selected to have less than 65% resin. Furthermore, in order to reduce the likelihood of glass fibers being present near the surface of the catalytic prepreg, woven glass fibers may be used with the inner prepreg layer, and flat non-woven glass fibers may be used in the outer resin-rich prepreg layer. The combination of resin rich prepreg and flat non-woven glass fibers on the outer surface layer results in an exclusion zone between the outer surface and the encapsulating glass fibers of 0.7 mils (17u) to 0.9 mils (23 u). Glass types 106, 1035, and 1067 are preferred for use on resin rich exterior surfaces because the glass fiber thickness (1.3-1.4 mils/33-35 u) is less than that found in typical prepreg sheets having greater than 65% resin used in the center region of the laminate, such as glass type 2116 with 3.7 mils (94u) fibers. These values are given as examples, and the smallest commercially available glass fiber is expected to continue to decrease in diameter. The temperature versus time curve 202 is modified in the present invention so that the catalytic particles and glass fibers migrate away from the outer surface of the laminate and are repelled by the surface tension of the epoxy during the liquid state at the gel point temperature. After the cooling cycle of curve 202, the cured C-stage prepreg sheet is unloaded 114. The process of forming the cured C-staged prepreg sheet may use a single or multiple sheets of fiber fabric to vary the finished product thickness, which may vary from 2 mils (51u) to 60 mils (1.5 mm).

Fig. 3 shows a flow diagram of a process for making a pre-impregnated laminate sheet with impregnated but excluded catalytic particles from the outer surface of the prepreg. Step 302 is to mix catalytic particles into the resin, and organic volatiles are often added to reduce the viscosity of the mixture, which forms the catalyzed resin 106 that is placed in the reservoir 108. Step 304 is infusing catalytic resin into the fabric (such as the roll 104 of fig. 1 may provide to form a stage a prepreg), and step 306 is initially rolling the catalyzed resin infused fabric into a stage B prepreg, for example by the roll 110, step 307 is a baking step for removing organic solvent to form a stage B prepreg, and step 308 is pressing the catalyzed resin infused fabric 130 into a sheet of catalyzed C stage prepreg in the laminator 126, which follows the temperature cycle of the curve 202, and the vacuum pump 128 evacuates the chamber 124 throughout the lamination process to remove air bubbles from the epoxy and reduce any voids that may form in the epoxy. The cooled finished catalytic C-stage prepreg sheets are cut and stored for later use.

The temperature versus time curve 202 of fig. 2 shows the temperature profile of the prepreg in the laminator 112, which is critical for the formation of a catalytic prepreg having surface properties of catalytic particles excluded from but present just below the resin-rich outer surface. The resin is in a liquid state in reservoir 108 and the prepreg is in stage a after the resin has been impregnated into the glass fibers and the prepreg has passed through rollers 110. The prepreg is in a B-stage after baking 103, where volatile organics are baked out, with an initial resin hardening that will convert the prepreg in the B-stage to become a C-stage prepreg at the end of the lamination cycle (e.g., the cool down stage of fig. 2). The B-stage prepreg was placed into the laminator and a vacuum was pulled to prevent the formation of trapped air between the laminate layers. Heat is applied during the temperature ramp-up time 204 to reach a temperature and pressure determined pre-impregnated gel point 205 (gel point is defined as a state where the liquid and solid states are close to equilibrium with each other) for a duration of about 10-15 seconds, which is critical for the process of migrating the catalytic particles away from the surface, after which the temperature of the pre-preg is maintained at a residence temperature and residence time 206, which may be in the range of 60-90 minutes, followed by a cooling cycle 208. The residence temperature and gel point temperature are pressure and resin related and are in the exemplary range of 120 c (for epoxy resins) to 350 c (for teflon/polyimide resins). Holding the prepreg at the gel point 205 for too short a duration will result in the undesirable presence of catalytic particles or glass fibers at the surface of the finished prepreg.

Fig. 4 shows the resulting catalytic prepreg 402 formed by the processes of fig. 1, 2 and 3, wherein catalytic particles 414 are uniformly distributed within a central region of the prepreg 402, but are not present beneath the border region 408 beneath the first surface 404, or beneath the border region 410 beneath the second surface 406. For an exemplary particle distribution of particles smaller than 25u, the catalytic particle boundaries are typically 10-12u (about half the particle size) below the surface, so in order for the embedded catalytic particles to be available for electroless plating, surface material at this depth or greater must be removed.

The prior art catalytic laminates have an activated surface that must be masked to prevent unwanted electroless plating on the activated surface of the catalytic laminate. In contrast, the catalytic laminate of the present invention, which excludes catalytic particles in the thickness range from the first surface 404 to the first boundary 408 and from the second surface 406 to the second boundary 410, provides the benefit that a separate masking layer to prevent contact with the catalytic particles is not required for electroless plating, as it is in the prior art. Thus, removal of surface material from the first surface 404 to the depth or greater of the boundary layer 408 or from the second surface 406 to the second boundary 410 results in exposure of catalytic material available for electroless plating. It is also desirable for processes that provide a resin rich surface to exclude not only the catalyst but also the fiber fabric, since in subsequent steps leading to exposure of the fibers, removal of the surface layer requires an additional cleaning step, and therefore surface removal is only preferred for the resin in order to expose the underlying catalytic particles. This is achieved by using a combination of resin rich outer prepreg layers and flat non-woven glass fibre layers with smaller diameter fibres on the outer layers. Another advantage of forming traces in vias using electroless plating is that the traces are mechanically supported on three sides, which provides greatly improved trace adhesion to the dielectric laminate.

The sequence of fig. 5A through 5E illustrate process steps identifying various structures (but not to scale), and provide a simplified view of the process steps merely for understanding the present invention. Fig. 5A shows an enlarged cross-sectional view of catalytic prepreg 508 formed by the processes of fig. 1, 2, and 3. The catalytic particles 502 may be in the size range of 25u and smaller, which in this example are shown in the range of 12u to 25u for clarity. As previously mentioned, the catalytic particles may comprise non-uniform catalytic particles (organic or inorganic particles having a catalytic surface coating) or uniform particles (catalytic metal particles). First boundary 504 is about 25u below first surface 506. A second surface 505 and a second surface boundary 503 on the opposite surface are shown for reference, but may be formed in the same manner as described for the sequence of fig. 5A to 5E. Also shown is a borehole 511 that will provide a connection between the traces on the first layer 506 and the traces on the second layer 505.

Fig. 5B shows the laminate of fig. 5A with vias 510 formed by removing the surface layer 506 in areas where traces are desired. The prepreg is also removed in an annular ring 513 around the via at the same or different depth as the trace channels 510. The facing material may be removed by laser ablation, wherein the temperature of the catalytic prepreg is immediately raised until the catalytic prepreg is evaporated, while keeping the surrounding prepreg structurally unchanged, keeping the catalytic particles exposed. For the prepreg material being ablated, it may be preferable to use a laser having a wavelength with low reflectivity, such as an Ultraviolet (UV) wavelength, and high absorption at this optical wavelength. Examples of such UV lasers are UV excimer lasers or Yttrium Aluminum Garnet (YAG) lasers, which are also good choices due to the narrow beam range and high available power for forming channels with precise mechanical depth and well-defined sidewalls. An exemplary laser can remove material at a 0.9-1.1 mil (23u to 28u) diameter width with a depth controlled by the laser power and speed of movement across the surface. Another surface removal technique for forming the channels 510 and annular ring 513 is plasma etching, which may be done locally or by preparing the surface with a patterned mask (such as a dry film photoresist or other mask material having a low etch rate compared to the etch rate of the catalyzed prepreg) that excludes plasma from the

surface layer

506 or 505. The photoresist thickness is typically selected based on the epoxy/photoresist etch selectivity (so that the plasma etch used to remove the cured epoxy to the desired depth leaves sufficient photoresist at the end of the etch), or in the case of photoresist used as a plating mask, according to the desired deposition thickness. Typical dry film thicknesses range from 0.8 to 2.5 mils (20-64 u). Is suitable for etchingThe plasma of the surface of the resin includes oxygen (O) and CF mixed with an inert gas such as nitrogen (N)₄A mixture of plasma, or argon (Ar) may be added as a carrier gas of the reaction gas. The mask pattern may also be formed using a dry film mask, a metal mask, or any other type of mask having holes. In the case of a mechanical mask, the resist may be applied using any method of photolithography, screen printing, stencil printing, brushing with a squeegee, or applying a resist. Another method for removing the surface layer of the prepreg is mechanical grinding, such as a linear or rotary cutting tool. In this example, the prepreg may be fixed in a vacuum plate chuck and a rotating cutter (or a fixed cutter with a movable vacuum plate) may advance a pattern defining a trace such as that defined by the x, y coordinate pair of a Gerber format photo file. In another example of removing surface material, a water cutting tool may be used, wherein a water jet stream having abrasive particles entrained in the stream may impinge on the surface, thereby removing material below the first boundary 504. Any of these methods may be used alone or in combination to remove surface material from prepreg 508 and form a channel 510, preferably extending below first boundary 504. Thus, the minimum channel depth is the depth required to expose the underlying catalytic particles (which are characteristic of the cured prepreg). Because the catalyzing material is uniformly dispersed throughout the cured prepreg below the exclusion boundary 504, the maximum channel depth is limited by the depth of the woven fabric of fibers (such as glass fibers), which tends to complicate channel cleaning as the fibers may break and redeposit in channels intended for electroless plating, or otherwise interfere with subsequent process steps. Typical channel depths are 1 mil (25u) to 2 mils (70 u). The final step after removing surface material to form the channels 510 is to clean off any particles of the removed material, which may be accomplished using ultrasonic cleaning, a water jet mixed with a surfactant, or any other cleaning means that does not cause material of the surface 506 around the channels to be removed.

Fig. 5C shows a contour plot of the progress of electroless plating over time in which the catalytic prepreg of fig. 5B is placed in an electroless plating bath using a dissolved reducing agent to reduce metal ions on the catalytic prepreg to a metallic state. One exemplary electroless copper plating bath formulation uses a mixture of rochelle salt as a complexing agent, copper sulfate as a copper metal source, formaldehyde as a reducing agent, and sodium hydroxide as a reactant. In this example, for ease of waste disposal, a tartrate (rochelle salt) bath is preferred; rochelle salts do not chelate as strongly as alternatives such as EDTA or ethylenediamine. In this example, tartrate (rochelle salt) is the finishing agent, copper sulfate is the metal source, formaldehyde is the reducing agent, and sodium hydroxide is the reactant. Other electroless plating formulations are also possible, and this example is given for reference. Electroless plating initially forms on the surfaces of the exposed catalytic particles as shown in the shaded pattern 520 at time t1 and the matching shaded pattern in the vias 535. As the electroless plating proceeds to the hash regions for the deposition shown at subsequent times t 2522, t 3524, and t 4526, copper deposition progresses, at which point the deposition 526 may extend above the surface 506 and the via 535 is also filled with copper.

One key advantage of electroless plating with etched channels in the catalytic material is that the electroless plating progresses simultaneously on all three sides compared to electroplating processed from only the bottom (initially plated) layer.

Fig. 5D shows the result of a surface smoothing operation in which the completed electroless plated trace 534 and via 535 are coplanar with surface 532. Surface smoothing can be achieved in many different ways, for example using 420 to 1200 grit abrasives coated on a flat surface with gentle pressure and linear or rotational agitation between the plate and the flat surface to provide the abrading operation. Other methods for planarizing surfaces may be used including milling or machining using chemical processes, mechanical processes, or other methods for forming a planar surface. Fig. 5E shows a solder mask 536, which may be screen printed for isolation and protection on the traces 534, such as the finished outer layer of a multi-layer board.

Fig. 5F shows a prior art etched copper trace for comparison purposes. The traces 554 are formed using a prior art subtractive etching process, where the traces 554 are what remains after etching the remaining portion of the copper present on the surface layer on the non-catalytic prepreg 550. The copper outer layer is patterned with a photoresist (such as a dry film) and then the surface is etched, which results in a trapezoidal cross-sectional profile of the trace 554, as the top of the trace undergoes a greater lateral etch than the bottom of the trace adjacent to the non-catalytic prepreg 550. Another advantage of the additive process of the present invention is that for traces formed using prior art processes that etch all copper except the desired trace copper, surface contamination on the surface causes adjacent traces to short, which does not occur in the additive electroless plating of the present invention, because the copper bridge (where contamination is present on the surface of the copper) remains. Solder mask 552 is also shown for comparison with the figures of the present invention. As seen in the figure, trace 554 is supported only by adhesion to substrate 550, while trace 534 of fig. 5E is supported on three sides and locked into its associated channel in catalytic prepreg 508.

Fig. 6A to 6G show another embodiment of the invention using a non-catalytic prepreg 602, which may be a conventional prepreg that does not contain catalytic particles. In this example of fig. 6A, a via 603 is first punched or drilled into the non-catalytic prepreg 602. The catalytic binder is formulated by mixing resin and catalytic particles, which may be in the same proportions and manner as the catalytic resin described previously (although for certain surface coating applications (such as by painting with a squeegee), it may have a higher viscosity), the main difference being that the catalytic binder is applied to a (typically) non-catalytic substrate, although it may also be applied to a catalytic substrate. For use in a catalytic binder, the catalytic particles are agitated until sufficiently wetted so that the catalytic binder 604 ensures that the catalytic particles 606 are not exposed until a subsequent surface coating 604 removal operation (such as the plasma clean of fig. 6B). In this example, the catalyzed resin is sprayed or brushed with a squeegee onto the surface of the non-catalyzed prepreg 602 and into the through holes 603 as shown in FIG. 6A. The catalyzed binder includes a resin 604 that contains a distribution of catalytic particles 604 (such as palladium particles less than 25u), or in one example of the invention, 50% by number of the particles fall within the range of 12-25u in longest particle dimension or have a range of particles from 1-25u as possible examples. The catalyzed binder may be formed using a ratio of catalyst weight to resin weight of 8-16%, with 12% being a preferred value, as previously described for catalyzed resins. The resulting catalyzed adhesive may then be applied to a non-catalyzed substrate and both baked to cure the catalyzed adhesive to the non-catalyzed pre-impregnated substrate 602. In one application method, catalytic adhesive is applied to the leading edge of a mechanical squeegee, which leading edge comprises a flexible blade carrying the catalytic adhesive and passing over the surface of the non-catalytic laminate, and the pressure and spacing between the flexible blade and the non-catalytic laminate is adjusted so that any drilled holes are filled by the catalytic laminate and a catalytic laminate of a desired thickness is arranged uniformly over the surface of the non-catalytic laminate in a single pass of the squeegee. Typically the catalytic adhesive is 12-75u thick. The catalytic binder thickness should be at least 2 times thicker than the largest catalytic particles to ensure that the catalytic particles remain below the surface of the catalytic binder.

The surface of fig. 6A is then subjected to a plasma cleaning step that strips the resin from the area above the surface of the catalyzed particles and non-catalyzed resin, leaving catalyzed particles 606 adhered to the surface of the non-catalyzed prepreg 602 as shown in fig. 6B. Fig. 6C shows the results of placing the plasma cleaned surface of fig. 6B in an electroless plating bath, which is completed in a sufficient amount of time to form a thin but continuous coating of electroless copper deposit 608 that initially forms on the catalytic particles 606 and spreads over the entire top surface. Fig. 6D illustrates the addition of a pattern mask 610 on the electroless plating 608. Because the electroless plating now covers the surface of the non-catalytic prepreg 602, a plating operation may then occur to plate additional copper onto the exposed patterned areas, as shown by trace 612 of fig. 6E, which may deposit copper 612 to a level below or above the mask 610. A mask stripping operation is shown in fig. 6F, which removes the pattern mask 610, leaving copper traces 612 and electroless copper layer 608. Fig. 6G shows the result of the rapid etch that removes the surface of the thin layer of electroless copper 608 and an equal amount of trace 612, leaving a trace comprising a uniform trace comprising electroplated copper 612 and the underlying electroless copper deposition 608, thereby providing a conductive circuit trace.

Fig. 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, and 10I illustrate a series of steps that may be performed on the catalytic laminate previously described in fig. 4, having catalytic particles 414 distributed throughout the catalytic laminate and having a catalytic particle exclusion depth 418 below

surfaces

404 and 406 such that electroless plating does not occur unless either

surface

406 or 404 is removed below the exclusion depth 418, thereby exposing the catalytic particles.

Fig. 10A shows a prepreg 1006 associated with the

exterior surfaces

1004 and 1008, the

exterior surfaces

1004 and 1008 being free of catalytic particles until the exterior surfaces are removed to a

depth

1002 and 1010, respectively, sufficient to expose underlying catalytic particles below the exclusion depth.

Fig. 10B shows an example through-hole or via 1012 that, when drilled, exposes catalytic particles on an inner surface 1014 of the borehole 1012.

Fig. 10C shows the catalytic laminate 1006 after blanket etching the entire outer surface of the catalytic laminate 1006 below the exclusion depth, resulting in an outer surface 1018 with exposed catalytic particles. The original pre-etched catalytic laminate surface 1016 is shown for reference. The sequence of operations of fig. 10B for the drilling of holes/vias 1012 and the blanket etching of the outer surface of fig. 10C may be performed in any order. The blanket etch may preferably be performed using reactive plasma, chemical etchant, however laser cutting, water jet cutting, mechanical abrasion, mechanical cutting or any other means of uniformly etching the outer surface of the prepreg and exposing the underlying catalytic particles below the surface and into the exclusion depth may be used. The step of fig. 10C is performed without any pattern mask of a previous catalytic laminate etching operation, as the goal is to remove the resin-rich surface below the exclusion depth to expose the catalytic particles on the entire surface of the catalytic laminate 1006.

The deposition of surface conductors, such as copper, may be performed on the surface using two different electroplating techniques. In a first electroless plating technique, the dielectric layer 1006 with exposed catalytic particles (such as palladium) is immersed in a plating solution containing metal ions (such as copper). The rate of electroless deposition of metallic copper onto the catalytic surface is slower than the rate of galvanic deposition of metallic copper, but electroless plating occurs on all surfaces with exposed catalytic particles, and also on surfaces with copper. Electroplating requires a uniform conductive surface, and therefore electroless plating is used as a pre-indicator of electroplating. Electroplating also requires an external voltage source, resulting in a faster rate of copper deposition than electroless deposition. A sacrificial copper anode having a positive voltage is placed in the electrolyte bath and the conductive surface to be plated is connected to a negative voltage. The anode copper migrates from the anode as metal ions and passes through the electrolyte to the cathode surface where the metal ions are deposited. In this example, the cathode surface is the PCB that needs to be plated with copper. Electroplating requires that all surfaces have a common potential, which is typically achieved by using a copper foil or electroless plating step on a dielectric surface with exposed catalytic particles until a continuous conductivity across the plate allows the plate to function as an anode, as required for a cathodic copper source.

Fig. 10D shows the completion of the electroless plating step, where the drilled and surface etched catalytic laminate 1006 is placed in an electroless plating bath of metal ions (typically copper) that are deposited onto the outer surface of the laminate 1018 and inside the drilled hole 1014 of fig. 10C to create a continuous conductive surface 1020 that is required for subsequent plating operations. The thickness of the electroless copper 1020 should be the minimum thickness required to ensure continuous coverage for successful plating, and is typically on the order of 0.15 mils.

Fig. 10E shows a subsequent step of applying a patterned photoresist 1024 over the previously applied electroless copper 1020, where the photoresist 1024 covers all areas except where traces or loop conductors around the drilled holes or vias 1012 are needed. The patterned photoresist 1024 has the effect of isolating the patterned areas from subsequent plating.

Fig. 10F shows a subsequent step of electroplating copper 1022 on the electroless copper 1020, the electroless copper 1020 serving as an electrode in the electroplating operation. The plating thickness 1022 may be of any thickness, preferably less than the thickness of the resist 1024 and greater than 1 times (or preferably 2 times or more) the thickness of the electroless metal deposit 1020.

Fig. 10G shows a subsequent step of stripping the resist 1024 of fig. 10F, thereby exposing the initially applied thin electroless copper areas 1026. Preferably, the thickness of the electroplated copper 1022 is greater than the thickness of the electroless copper 1020, such that the rapid etching step of fig. 10H preferentially removes the exposed electroless copper regions 1026 and leaves substantially all of the electroplated copper 1022.

Fig. 10I shows the completed process. In understanding the present invention and the processing steps, the boundary between electroless copper 1020 and electroplated copper 1022 is presented at the front for clarity. When electroplated copper 1022 is deposited on the exposed electroless copper 1020 during the step of fig. 10F, the resulting via plating around hole 1012 and trace 1020/1022 of fig. 10I is continuous copper, as shown.

The series of fig. 7A to 7G show cross-sectional views of a series of steps for forming vias in a conventional non-catalytic prepreg 702 having an upper foil laminate 704 and a lower foil laminate 706. Fig. 7G shows a perspective view of the finished via, while fig. 7A to 7F are cross-sectional views through a-a of fig. 7G at the end of various intermediate processing steps.

Fig. 7B shows a cross-sectional view of the upper layer 704 and the lower layer 706 after patterning, where the traces 704 are to be connected to the traces 706 on opposite surfaces of the non-catalyst dielectric 702. Fig. 7B shows a via 708 that may be formed by punching or drilling, the via 708 being located in the center of an annular ring of pads 716 formed by the upper trace 704 and pads 718 formed by the lower trace 706. Fig. 7D shows a catalytic filler 710, such as a plugged through hole formulation with catalytic particles. The catalytic filler 710 is typically a thick fluid having a viscosity in the range of 70,000-80,000 centipoise (cP) that is placed in the through hole 708 of fig. 7C, and fig. 7E shows secondary holes 712 drilled in the catalytic filler 710 that expose the catalytic filler particles present in the catalytic filler 710, thereby making the catalyst available for electroless plating operations. An electroless copper deposition step follows, and electroless copper Cu + + forms a conductive deposition layer 714 on the top trace 704, the annular ring top pad 716, through the secondary hole 712 with exposed catalytic particles, on the lower pad 718, and on the lower trace 706, which completes the circuit from the upper trace 704 through the via structure 710/714 to the lower trace 704. As will be clear to those skilled in the art, although an annular ring conductor is shown on each connection surface, the traces may connect directly into the vias with or without an annular ring.

Fig. 8A shows another method for electroless plating of traces onto a laminate using a non-catalytic substrate or prepreg 802, with optional holes 804 drilled or punched for layer-to-layer connection. Fig. 8B illustrates the application of the catalytic adhesive 806, such as using a squeegee, screen printing, stencil, or any other method as previously described for fig. 6A. In this coating operation, the holes 804 are also filled with a catalytic adhesive 806. Fig. 8C shows a secondary bore 808 in the annular ring of holes 804 that activates the catalytic binder 806 in the bore 808 by exposing the catalytic particles. Fig. 8D shows the removal 814 of the surface layer 806 sufficient to expose the catalytic particles used to form the electroless conductive traces, pads and vias. Fig. 8E shows the completion of electroless plating, where copper 816 is plated onto the catalytic adhesive that has been drilled, etched, or otherwise removed. As described for fig. 5D, planarization may optionally be performed, or a solder resist layer applied. In certain applications, such as high frequency applications where dielectric loss tangent is critical, it may be desirable to use a heterogeneous mixture of non-catalytic laminate 802 (such as PTFE) and a resin-based catalytic laminate. In this case, it may be necessary to roughen the surface of the non-catalytic laminate 802 (such as PTFE) using plasma etching, chemical etching, or other methods known in the art for destroying long chain polymer molecules, to provide better adhesion for the catalytic adhesive at the catalytic adhesive/PTFE boundary. In one example of the invention, the PTFE non-catalytic substrate 802 is homogeneous PTFE, in another example it is a laminate, and in either case, the substrate 802 may or may not include fiber (such as fiberglass) reinforcement.

A variation of the laminate structure of fig. 8A-8E is shown in fig. 9A-9E, where a catalytic adhesive 906 is used on the catalytic laminate 902. This approach has several advantages. One advantage is that the application of the catalytic adhesive 906 does not require pre-drilling of the through-holes 908 prior to the application of the catalytic adhesive as shown in 804 of figure 8A. Another advantage is that the resin-rich surface can be formed by the catalytic adhesive 906 instead of the catalytic substrate 904, so that the catalytic particles of the substrate 902 need not have an exclusion zone near the surface as shown in fig. 4, as this is now provided by the catalytic adhesive 906 applied to one or both sides of the substrate 902. Fig. 9C shows a cross-sectional view after hole 908 is drilled, step 9D shows surface removal 914, and fig. 9E shows electroless plating 916 using the methods described previously.

The foregoing description provides examples of the invention merely for the understanding of the underlying mechanisms and structures used, and is not intended to limit the scope of the invention to only the particular methods or structures shown. For example, the sequence of fig. 5A-5E and 6A-6G show a single-sided structure with trace lanes cut only on the first surface, while the same structure and method can be applied to the second surface 505 without loss of generality, since the electroless plating step can be applied to the lanes or exposed catalyst on both sides of the board in a single step. Furthermore, the layers as fabricated in fig. 5A to 5E, 6A to 6G, 8A to 8E, 9A to 9E, 10A to 10I and the vias of fig. 7A to 7F may be formed on separate layers which are then laminated together as a single board with a mixed layer of catalytic and non-catalytic prepregs, and the scope of the claims relating to "multilayer PCB" will be construed to include such a structure. Similarly, although the trace structures and via structures of fig. 5A-5E, 6A-6G, 8A-8E, and 7A-7F are shown in combination because they typically appear on a PCB, these examples are for illustration only and are not intended to limit the invention to these structures. For example, according to novel aspects of the process, the mounting holes of the through-hole features without electrical connections can be formed without connecting traces or annular rings.

In the present specification, "approximately" is understood to mean less than 4 times or more or less, and "substantially" is understood to mean less than 2 times or more or less. An "order of magnitude" of a value includes a range from 0.1 times the value to 10 times the value.

Certain post-processing operations that are common to printed circuit board manufacture are not shown and can be performed using prior art methods on boards produced according to the new process. Such operations include tin plating for improved solder flow, gold flash for improved conductivity and reduced etching, solder mask operations, screen printing information (part numbers, reference indicators, etc.) on the circuit board, scribing the finished board or providing separating tabs, etc. Certain of these operations may produce improved results when performed on a planarizing plate of certain aspects of the present invention. For example, screen printed lettering on traces or vias has traditionally been split due to trace and via thickness on the circuit board surface, and these operations would provide excellent results on flat surfaces.

Claims

1. A catalytic laminate having at least one surface enriched in resin compared to other regions of the catalytic laminate;

the catalytic laminate having catalytic particles having a maximum catalytic particle range;

the catalytic laminate having a catalytic particle exclusion zone of at least the maximum extent 1/2 below the at least one surface, the catalytic particles not being present in the catalytic particle exclusion zone;

whereby electroless plating deposits metal on the at least one surface from which surface material is removed and electroless plating deposition does not occur on other portions of the at least one surface.

2. The catalytic laminate of claim 1, wherein the catalytic particles are non-uniform.

3. The catalytic laminate of claim 2, wherein the catalytic particles comprise a filler coated with a catalyst.

4. The catalytic laminate of claim 3, wherein the filler is at least one of: clay minerals, hydrated aluminosilicates, silica, kaolinite, polysilicates, members of the kaolin or china clay families, or high temperature plastics.

5. Catalytic laminate according to claim 3, wherein the particle size is in the order of 3u or less than 3 u.

6. The catalytic laminate of claim 3, wherein the ratio of the catalytic particles to the resin is in the range of 8% to 16% by weight.

7. The catalytic laminate of claim 3, wherein the catalytic particles are silica or kaolin coated with a catalytic material.

8. The catalytic laminate of claim 3, wherein the catalyst is palladium.

9. The catalytic laminate of claim 3, wherein the catalyst is at least one of: palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or other compounds or salts thereof.

10. The catalytic laminate of claim 1, wherein the catalytic particles are uniform.

11. The catalytic laminate of claim 10, wherein the catalyst is palladium.

12. The catalytic laminate of claim 10, wherein the catalyst is at least one of: palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or other compounds or salts thereof.

13. The catalytic laminate of claim 10, wherein the ratio of the catalytic particles to the resin is in the range of 8% to 16% by weight.

14. The catalytic laminate of claim 10, wherein a majority of the catalytic particles have a size of less than 25 u.

15. A process for forming a catalyzed pre-impregnated laminate having a resin-rich surface that excludes catalytic particles at an exclusion depth below the resin-rich surface, the process comprising:

forming a catalyzed resin by blending the catalytic particles into a resin and a solvent;

infusing the catalyzed resin into the fabric;

rolling the fabric impregnated with the catalyzed resin to a desired first thickness;

baking the resin impregnated with the catalyst until most of the solvent is removed;

placing the baked catalytic prepreg into a laminator having a substantially flat pressure surface;

heating the catalytic prepreg under vacuum while applying lamination pressure, changing the temperature of the laminator to provide heating ramped up to a residence temperature that maintains the gel point, maintaining the residence temperature for a residence time sufficient to migrate the catalytic particles away from the outer surface of the catalytic prepreg, and thereafter reducing the temperature in a cooling cycle;

wherein the residence time, residence temperature, and lamination pressure are selected such that the catalytic particles are excluded in a region below the resin-rich surface.

16. The method of claim 15, wherein the catalytic particle is at least one of: palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or a compound or salt thereof.

17. The method of claim 15, wherein the resin comprises at least one of: epoxy resin, polyimide resin, cyanate ester resin, or teflon blend resin.

18. The method of claim 15, wherein the gel temperature is in the range of 120 ℃ to 350 ℃.

19. The method of claim 15, wherein the gel time is in a range of 5 seconds to 15 seconds during a temperature ramp time interval.

20. A catalytic prepreg comprising:

a fabric impregnated with a resin having catalytic particles of less than 25 u;

the prepreg having at least a first planar surface and the catalytic particles being substantially uniformly distributed in an interior region of the prepreg, the prepreg further having a resin-rich surface excluding the catalytic particles, the resin-rich surface having a depth of at least two times a median catalytic particle size;

thus, removing material from the resin-rich surface exposes some of the catalytic particles sufficient for electroless plating to occur.

21. The catalytic prepreg of claim 20, wherein the glass fibers are formed from woven glass fibers.

22. The catalytic prepreg of claim 20, wherein the catalytic particles comprise at least one of: palladium (Pd), platinum (Pt), rhodium (Rh), iridium (Ir), nickel (Ni), gold (Au), silver (Ag), cobalt (Co), or copper (Cu), or a salt thereof.

23. The catalytic prepreg of claim 20, wherein the catalytic particles are blended into the resin in a proportion in the range of 8% to 16% by weight of the resin.

24. A method for forming a via in a non-catalytic dielectric material having a first copper layer applied to a first surface of the non-catalytic dielectric material and an optional second copper layer applied to a surface opposite the first surface, the first copper layer optionally being patterned to include at least one trace and at least one pad formed thereon, the method comprising:

forming a hole having a first diameter through the first copper layer and the dielectric and optionally through the second copper layer;

placing a catalyzed resin in the formed pores, the catalyzed resin comprising a resin mixed with catalytic particles;

forming second pores in the catalyzed resin, the second pores having a diameter smaller than the first pores, the second pores thereby exposing the catalyzed particles of the catalyzed resin;

placing the non-catalytic dielectric within an electroless copper plating bath, the electroless copper plating bath thereby depositing copper (Cu) on the first copper layer, the first layer pad, an inner surface of the second hole, and optionally the second copper layer.

25. A circuit board, comprising:

a non-catalytic dielectric having a copper layer applied to at least one surface;

the copper layer includes a hole having an inner diameter;

the inner diameter of the hole and the copper layer having a deposited film of copper forming an electrical connection;

the inner diameter is surrounded by an annular ring of catalytic material formed between the inner diameter and a hole in the non-catalytic dielectric.