CN114499528A

CN114499528A - Digital driver, feedback circuit for analog-to-digital converter, and digital-to-analog converter

Info

Publication number: CN114499528A
Application number: CN202210142142.6A
Authority: CN
Inventors: 郭铭强; 冼世荣; 肖刚军; 赵伟兵; 许登科; 马许愿
Original assignee: Um Zhuhai Research Institute; University of Macau; Zhuhai Amicro Semiconductor Co Ltd
Current assignee: Um Zhuhai Research Institute; University of Macau; Zhuhai Amicro Semiconductor Co Ltd
Priority date: 2022-02-16
Filing date: 2022-02-16
Publication date: 2022-05-13

Abstract

An embodiment of the present application provides a digital driver, including: the input terminal, the output terminal, the first, the second, the third and the fourth PMOS tubes, the first, the second, the third and the fourth NMOS tubes; the input terminal, the first PMOS tube and the first NMOS tube are connected; the first PMOS tube, the first NMOS tube, the second PMOS tube and the second NMOS tube are connected to a first node; the second PMOS tube, the second NMOS tube, the third PMOS tube and the third NMOS tube are connected to a second node; the third PMOS tube, the third NMOS tube, the fourth PMOS tube and the fourth NMOS tube are connected to a third node; the fourth PMOS tube and the fourth NMOS tube are connected with the output terminal; the widths of the PMOS tubes and the NMOS tubes are determined according to the mobility and a preset reduction coefficient. Thus, the delay time and power consumption can be reduced by adjusting the size of the transistor by a predetermined reduction factor.

Description

Digital driver, feedback circuit for analog-to-digital converter, and digital-to-analog converter

Technical Field

The present application relates to the field of electronic technologies, and in particular, to a digital driver, a feedback circuit for an analog-to-digital converter, and a digital-to-analog converter.

Background

The conventional Successive Approximation Analog-to-Digital Converter (SAR ADC) includes a tracking sample-and-hold circuit (T/H), a comparator, a SAR logic circuit, and a capacitive Digital-to-Analog Converter (DAC), and has the advantages of low complexity, low power consumption, and a high energy efficiency topology with reduced process technology, so that the conventional structure has wide applications in high-speed applications, for example, the conventional structure can be used in a time-interleaved Successive Approximation Analog-to-Digital Converter (TI-SAR ADC). Some existing schemes speed up the conversion of SAR ADCs by improving the one-bit-per-cycle topology, such as the structure of SAR that employs multiple-bit-per-cycle SAR and N-bit N comparators. However, the one-bit-per-cycle topology of the conventional architecture still has significant advantages in terms of low complexity, less parasitics, and less detuning. Therefore, most high-speed TI-SAR ADCs still prefer the conventional one-bit-per-cycle architecture. The architecture with redundant bits employed in high-speed SAR ADCs allows the setup time required for the DAC to be very short. However, the slow speed is still a major bottleneck of the SAR ADC of the conventional architecture, limited by the delay time of the digital SAR logic per cycle.

Disclosure of Invention

In order to solve the above technical problem, embodiments of the present application provide a digital driver, a feedback circuit for an analog-to-digital converter, a digital-to-analog converter and an electronic device.

In a first aspect, an embodiment of the present application provides an analog-to-digital converter, including:

an input terminal, an output terminal, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

the input terminal is connected with the gate of the first PMOS transistor and the gate of the first NMOS transistor;

the drain electrode of the first PMOS transistor, the drain electrode of the first NMOS transistor, the grid electrode of the second PMOS transistor and the grid electrode of the second NMOS transistor are connected to a first node;

the drain electrode of the second PMOS transistor, the drain electrode of the second NMOS transistor, the grid electrode of the third PMOS transistor and the grid electrode of the third NMOS transistor are connected to a second node;

the drain electrode of the third PMOS transistor, the drain electrode of the third NMOS transistor, the grid electrode of the fourth PMOS transistor and the grid electrode of the fourth NMOS transistor are connected to a third node;

a drain of the fourth PMOS transistor, a drain of the fourth NMOS transistor, and the output terminal are connected; the widths of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are determined according to the mobility of the PMOS transistors, the mobility of the NMOS transistors and a preset reduction coefficient, and the value range of the preset reduction coefficient is (0, 1).

In a second aspect, an embodiment of the present application provides a feedback circuit for an analog-to-digital converter, including:

the capacitive DAC circuit comprises a capacitive DAC, a comparison circuit, an asynchronous logic control circuit and a DAC switch control circuit;

the capacitive DAC comprises a plurality of capacitors and a plurality of digital drivers, each of the digital drivers being the digital driver provided in the first aspect;

the asynchronous logic control circuit and the DAC switch control circuit respectively comprise a plurality of triggers;

each capacitor is connected with an input terminal of a corresponding digital driver, and an output end of the capacitive DAC is connected with an input end of the comparison circuit;

the output end of the comparison circuit is connected with the input end of each trigger of the asynchronous logic control circuit;

the output end of each trigger of the asynchronous logic control circuit is connected with the input end of the corresponding trigger of the DAC switch control circuit;

and the output end of each trigger of the DAC switch control circuit is connected with the input end of the corresponding digital driver.

In a third aspect, the present application provides an analog-to-digital converter, including the feedback circuit for an analog-to-digital converter provided in the second aspect.

In a fourth aspect, the present application provides an electronic device, including the analog-to-digital converter provided in the third aspect.

The digital driver, the feedback circuit for the analog-to-digital converter, the digital-to-analog converter and the electronic device provided by the application adopt the preset reduction factor to adjust the sizes of the NMOS transistor and the PMOS transistor, so that the delay time and the power consumption can be reduced.

Drawings

In order to more clearly explain the technical solutions of the present application, the drawings needed to be used in the embodiments are briefly introduced below, and it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope of protection of the present application. Like components are numbered similarly in the various figures.

Fig. 1 is a schematic structural diagram of a digital driver according to an embodiment of the present application;

FIG. 2 is a schematic diagram illustrating a time delay comparison provided by an embodiment of the present application;

FIG. 3 is a diagram illustrating simulation results of a digital driver provided by an embodiment of the present application;

fig. 4A is a schematic diagram illustrating another structure of a feedback circuit for an analog-to-digital converter according to an embodiment of the present application;

FIG. 4B is a schematic diagram of a signal variation provided by an embodiment of the present application;

fig. 5A shows another schematic structural diagram of a feedback circuit for an analog-to-digital converter provided in an embodiment of the present application;

FIG. 5B is a schematic diagram of another signal variation provided by an embodiment of the present application;

fig. 6 shows a simulation diagram of a flip-flop provided in the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.

The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present application, are intended to indicate only specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.

Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the present application belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments.

Example 1

The disclosed embodiments provide a digital driver.

Specifically, referring to fig. 1, fig. 1 is a schematic structural diagram of a digital driver 10, where the digital driver 10 includes: an input terminal IN, an output terminal OUT, a first P-Metal-Oxide-Semiconductor (PMOS) transistor M_P1A second PMOS transistor M_P2A third PMOS transistor M_P3A fourth PMOS transistor M_P4A first N-Metal-Oxide-Semiconductor (NMOS) transistor M_N1A second NMOS transistor M_N2A third NMOS transistor M_N3And a fourth NMOS transistor M_N4；

the first PMOS transistor M_P1The first NMOS transistor M_N1Drain electrode of the second PMOS transistor M_P2And the second NMOS transistor M_N2The gate of the first transistor is connected to a first node A;

the second PMOS transistor M_P2The drain electrode of the second NMOS transistor M_N2The drain of the first PMOS transistor, the gate of the first NMOS transistor and the gate of the first NMOS transistor are connected to a first node B;

the third PMOS transistor M_P3The drain electrode of the third NMOS transistor M_N3Drain electrode of the fourth PMOS transistor M_P4And the fourth NMOS transistor M_N4The gate of which is connected to the third node C;

the fourth PMOS transistor M_P4The drain electrode of the fourth NMOS transistor M_N4Is connected to the output terminal; wherein the first PMOS transistor M_P1The second PMOS transistor M_P2The third PMOS transistorM_P3The fourth PMOS transistor M_P4The first NMOS transistor M_N1The second NMOS transistor M_N2The third NMOS transistor M_N3The fourth NMOS transistor M_N4The width of the scaling factor is determined according to the mobility of the PMOS transistor, the mobility of the NMOS transistor and a preset scaling factor, and the value range of the preset scaling factor is (0, 1).

In this embodiment, the NMOS transistor and the PMOS transistor may be referred to as NMOS transistor and PMOS transistor, respectively, and the digital driver 10 may be understood as an unbalanced driver due to the introduction of the predetermined reduction factor. In a conventional digital driver, the aspect ratio of the NMOS transistor and the PMOS transistor is approximately equal to the ratio of the NMOS transistor mobility and the PMOS transistor mobility. For example, when the digital driver 10 shown in fig. 1 does not use the predetermined reduction factor provided by the present embodiment, the second PMOS transistor M_P2The second NMOS transistor M_N2The following relation 1 exists between the widths of (a):

wherein, W_P2Denotes a second PMOS transistor M_P2Width of (W)_N2Denotes a second NMOS transistor M_N2Width of (d), μ_pDenotes the mobility, μ, of the PMOS transistor_nRepresenting the mobility of the NMOS transistor. The third PMOS transistor M_P3The third NMOS transistor M_N3The following relation 2 exists between the widths of (a):

wherein, W_N3Denotes a third NMOS transistor M_N3Width of (W)_P3Denotes a third PMOS transistor W_P3Width of (d), μ_pDenotes the mobility, μ, of the PMOS transistor_nRepresenting the mobility of the NMOS transistor.

In this embodiment, the widths of the corresponding NMOS transistor and PMOS transistor are reduced by using the predetermined reduction factor. For example, in FIG. 1, a second PMOS transistor M_P2The second NMOS transistor M_N2Is wide byThe third PMOS transistor M is determined by the following equation 1_P3The third NMOS transistor M_N3Is determined by the following equation 2.

Equation 1:

wherein, W_P2Denotes a second PMOS transistor M_P2Width of (W)_N2Denotes a second NMOS transistor M_N2Width of (d), μ_pDenotes the mobility, μ, of the PMOS transistor_nRepresents the mobility of the NMOS transistor; α represents a preset reduction factor.

Equation 2:

wherein, W_N3Denotes a third NMOS transistor M_N3Width of (W)_P3Denotes a third PMOS transistor W_P3Width of (d), μ_pDenotes the mobility, μ, of the PMOS transistor_nRepresents the mobility of the NMOS transistor; α represents a preset reduction factor.

In addition, the first NMOS transistor M_N1And the first PMOS transistor M_P1Is approximately equal to

And the fourth PMOS transistor M_P4And the fourth NMOS transistor M_N4Is approximately equal to

With reference to the digital driver 10 of fig. 1, if the preset scaling factor provided by the present embodiment is not adopted, the delay time for the input terminal IN to pull the first node a from the low level to the high level toward the first node a based on the edge direction IN the first node a is determined by the following formula 3.

The delay time for pulling the second B point from the high level to the low level from the first node a to the second node B is determined by the following equation 4.

Equation 3: t is t_pLH,A≈0.69R_eqP,AC_L,A；

Wherein R is_eqP,AIs a first PMOS transistor M_P1The equivalent on-resistance of the capacitor (c),

l denotes a first PMOS transistor M_P1Length of (d) represents PMOS transistor mobility, W_P1Denotes a first PMOS transistor M_P1The width of (d); c_L,AIs the equivalent load capacitance of the first node A, C_L,A∝(W_N2+W_P2)L，W_N2Denotes a second NMOS transistor M_N2Width of (W)_P2Denotes a second PMOS transistor M_P2L denotes a second NMOS transistor M_N2Length of or second PMOS transistor M_P2Length of (d); t is t_pLH,AWhich represents a delay time for the input terminal IN to pull the first node a from a low level to a high level toward the first node a.

Equation 4: t is t_pHL,B≈0.69R_eqN,BC_L,B；

Wherein R is_eqN,BIs a first PMOS transistor M_P1The equivalent on-resistance of the capacitor (c),

l denotes a second NMOS transistor M_N2Length of (d), mu_NDenotes NMOS transistor mobility, W_N2Denotes a second NMOS transistor M_N2The width of (d); c_L,BIs the equivalent load capacitance of the E second node B, C_L,B∝(W_N3+W_P3)L，W_N3Denotes a third NMOS transistor M_N3Width of (W)_P3Denotes a third PMOS transistor M_P3L denotes a third NMOS transistor M_N3Length of or third PMOS transistor M_P3Length of (d); t is t_pHL,BWhich represents the delay time for the first node a to pull the second node B from high to low towards the second node B.

It can be seen that, for the digital driver 10 of fig. 1, if the preset reduction factor provided by the present embodiment is not adopted, the corresponding delay time can be determined by the following formula 5.

Equation 5:

wherein, T_{delay-regular}Represents the time delay of the digital driver 10 shown in fig. 1 when the preset reduction factor provided by the present embodiment is not employed; t is t_pLH,AA delay time representing a time during which the input terminal IN is pulled to the first node A from a low level to a high level; t is t_pHL,BThe delay time for pulling the second node B point from high level to low level from the first node A to the second node B is represented; w in equation 5_P1、W_P2、W_P3、W_N2、W_N3、μ_P、μ_NThe meaning of the above is the same as that of the above, and the description is omitted here.

For the digital driver 10 of fig. 1, if the preset reduction factor provided by the present embodiment is not adopted, the corresponding power consumption can be determined by the following equation 6.

Equation 6: p_regular∝[(W_N2+W_P2)+(W_N3+W_P3)]；

Wherein, P_regularThe digital driver 10 of fig. 1 is shown, if the preset reduction factor provided by the present embodiment is not adopted, the corresponding power consumption is shown. W_P2、W_P3、W_N2、W_N3The meaning of the above is the same as that of the above, and the description is omitted here.

The embodiment adopts a preset reduction factor, and the second PMOS transistor M_P2The second PMOS transistor M is reduced by a predetermined reduction factor alpha_P2Width W of_P2Thereby reducing C_L,AThus, after the digital driver 10 shown in fig. 1 adopts the preset reduction factor α, the delay time of the digital driver 10 can be determined according to the following equation 7.

Equation 7:

wherein, T_{delay-proposed}Indicating the delay time, T, after the digital driver 10 has adopted the preset reduction factor alpha_{delay-regular}Indicating the delay time when the digital driver 10 does not employ the preset reduction factor alpha. α represents a preset reduction factor.

It should be noted that the delay time after the digital driver 10 adopts the preset reduction factor α is in positive correlation with the preset reduction factor. Specifically, it can be known from formula 7 that the larger the preset reduction factor α is, the larger the delay time after the preset reduction factor α is adopted is, and the smaller the preset reduction factor α is, the smaller the delay time after the preset reduction factor α is adopted is. Referring to fig. 2, fig. 2 is a schematic diagram of the delay of the digital driver, in fig. 2, T_{delay-proposed}Indicating the delay time, T, after the digital driver 10 has adopted the preset reduction factor alpha_{delay-regular}Indicates the delay time when the digital driver 10 does not employ the preset reduction factor α, where T_{delay-proposed}Less than T_{delay-regular}。

In addition, after the digital driver 10 shown in fig. 1 adopts the preset reduction factor α, the power of the digital driver 10 can be determined according to the following equation 8.

Equation 8:

wherein, P_proposedRepresents the power of the digital driver 10 after the preset reduction factor α is adopted; p_regularRepresents the power at which the digital driver 10 does not employ the preset reduction factor α; α represents a preset reduction factor.

Referring to fig. 3, fig. 3 is a schematic diagram of simulation results, and if the predetermined reduction factor α is 0.25, as shown in the histogram of fig. 3, the delay time of the actual circuit is reduced by 31.3% in the post-simulation of the layout. In addition, the load capacitance and power consumption of each node of the logic transmission path are also decreased by (1+ α)/2.

It should be noted that this scheme of reducing delay and power consumption by using unbalanced NMOS and PMOS transistor sizes can also be extended to other digital logic circuits, such as NAND gates, NOR gates, and logic gates in flip-flops (DFFs).

The digital driver provided by the embodiment adopts the preset reduction factor, and the sizes of the NMOS transistor and the PMOS transistor are adjusted, so that the delay time and the power consumption can be reduced.

Example 2

The embodiment of the disclosure also provides a feedback circuit for the analog-digital converter.

Specifically, referring to fig. 4A, fig. 4A is a schematic diagram illustrating a structure of a feedback circuit for an analog-to-digital converter, where the feedback circuit 40 for the analog-to-digital converter includes:

a capacitive DAC401, a comparison circuit 402, an asynchronous logic control circuit 403, and a DAC switch control circuit 404;

the capacitive DAC comprises a plurality of capacitors C₁、C₂、...、C_iA plurality of digital drivers 4011, each of the digital drivers 4011 being the digital driver provided in embodiment 1;

the asynchronous logic control circuit 403 comprises a plurality of flip-flops DFF_A(ii) a The DAC switch control circuit 404 includes a plurality of flip-flops DFF_D；

Each capacitor C_iThe output end of the capacitance type DAC401 is connected with the input end of the comparison circuit 402;

the output terminal of the comparison circuit 402 and each flip-flop DFF of the asynchronous logic control circuit 403_AThe input ends of the two-way valve are connected;

each flip-flop DFF of the asynchronous logic control circuit 403_AAnd the corresponding flip-flop DFF of the DAC switch control circuit 404_DThe input ends of the two-way valve are connected;

each flip-flop DFF of the DAC switch control circuit 404_DIs connected to the input of a corresponding digital driver 4011.

In this embodiment, each of the digital drivers 4011 is the digital driver provided in embodiment 1, and has the structure and advantages of the digital driver in embodiment 1. The digital driver 4011 is composed of unbalanced NMOS transistors and PMOS transistors, and widths of the NMOS transistors and the PMOS transistors are adjusted according to a preset reduction factor, so as to reduce SAR logic delay, thereby overcoming a speed bottleneck of a one-pass SAR ADC.

In this embodiment, the analog-to-digital converter may be a monotonic capacitor switch SAR ADC having the characteristic of switching only in a unidirectional switch DAC, and the delay from the comparator to the DAC may be reduced by unilaterally adjusting the sizes of the NMOS transistor and the PMOS transistor of the logic gate. The digital driver of the embodiment adopts a preset scale-down factor, provides the dimensions of unbalanced NMOS transistors and PMOS transistors, improves the logic speed on the key edge conversion, and reduces the transistor dimensions in the direction of the non-key edge.

Therefore, the speed can be improved, and the power consumption and the area of the SAR ADC can be reduced at the same time, so that the limiting factor that the SAR ADC needs to carry out compromise selection between power consumption and delay is broken. More importantly, this scheme does not change the classical one-bit-per-cycle (1b/cycle) structure, which makes it all the advantages of the conventional architecture. The 10-bit 550MS/s SAR ADC of the present embodiment is implemented in CMOS process, and at a speed of 550MS/s, the signal-to-noise-and-distortion ratios (SNDR) of the SAR ADC at the Nyquist input signal frequency reach 56.0dB respectively, and the corresponding consumption is 1.37mW, so that the Walden optimum (Walden FoM) is 4.78fJ/conv-step respectively (femtoJoule per conversion).

The use of the feedback circuit for an analog-to-digital converter is described below in conjunction with fig. 4A.

During the sampling phase, each digital driver 4011 switches each capacitor C of the capacitive DAC401_iThe bottom plate of which is reset to VDD. Followed by a digital Output (OUT) from the comparison circuit 402_P/OUT_N) And corresponding logic Clock (CLK) of SAR_i) Capacitor C of each bit_iThe bottom plate switches to GND (critical edge direction) or will remain at VDD unchanged (non-critical edge direction). As shown in fig. 1, for the ith bit capacitor C_iThe critical speed edge of the bottom plate is always the falling edge, and the corresponding DAC switch control signal (c)DAC_i) The critical speed edge of (a) is always a rising edge. Similarly, asynchronously controlled SAR logic Clock (CLK)_i) The corresponding critical speed edge is also always a rising edge, and applies to all DFFs in the asynchronous control logic_AReset during the sampling phase. In combination with the above analysis, it can be concluded from capacitor C_iDAC switch control signals (DAC) output by the bottom plate-to-digital driver 4011 and the DAC switch control circuit 404_i) And SAR logic Clock (CLK) output from asynchronous logic control circuit 403_i) Is always determined, in a single direction.

In most cases, the use of transconductance (g) is employed_m) A balanced N/P-MOS digital buffer drives the switches of the capacitive DAC to ensure that the digital buffer has substantially symmetrical rising and falling edges, and similar N/P delay times. However, for a logic driver of a monotonic capacitive DAC switch, it is unidirectional every cycle in every SAR conversion. This means that critical data transmission only needs to be optimized in a single direction. The digital driver 4011 in fig. 4A is the digital driver provided in embodiment 1, and it can be known from the digital driver 10 shown in fig. 1 that the digital driver is composed of unbalanced N/P-MOS transistors and serves as the capacitor C in the conversion stage_iThe node "OUT" of the bottom plate switches to GND or remains unchanged. Therefore, the critical edges in the output terminal OUT, the third node C, the second node B, the first node a are always falling/rising/falling/rising edges, respectively. The structure and implementation principle of the digital driver 4011 in fig. 4A can refer to the description of the digital driver 10 in embodiment 1, and are not described herein again.

Referring again to fig. 4A, the comparison circuit 402 comprises: a comparator 4021, a NOR gate 4022, and a first inverter 4023, wherein an input terminal of the comparator 4021 is connected to an output terminal of the capacitive DAC401, an output terminal of the comparator 4021 is connected to an input terminal of the NOR gate 4022, an output terminal of the NOR gate 4022 is connected to an input terminal of the first inverter 4023, and an output terminal of the first inverter 4023 is connected to an input terminal of each flip-flop of the asynchronous logic control circuit 403.

Please refer to the drawings4B，OUT_P/OUT_NRespectively, two corresponding output signals of the fully differential comparator, and the Ready signal represents an effective signal in the asynchronous SAR logic conversion. Phi_compIndicating the clock signal, CLK, of the comparator_iAsynchronous control clock, CLK, representing SAR logic_iIs to indicate that the cycle of the ith SAR is being switched. DAC_iRepresenting the digital-to-analog conversion information of the ith DAC, fig. 4B shows that the first curve 41 and the second curve 42 represent that the next rising/falling edge is triggered by the previous rising/falling edge. The first arrow line segment 43 indicates a rising edge and the second arrow line segment 44 indicates a falling edge.

Referring to fig. 5A, the difference between the feedback circuit for analog-to-digital converter shown in fig. 5A and the feedback circuit for analog-to-digital converter shown in fig. 4A is that the comparison circuit 402 further includes: a second inverter 4024 and a NAND gate 4025, a first input terminal and a second input terminal of the NAND gate are respectively connected to the output terminal of the NOR gate 4022 and the output terminal of the second inverter 4024, an output terminal of the NAND gate 4025 is connected to a control terminal of the comparator 4021, and an input terminal of the second inverter 4024 is configured to receive a sampling signal.

In one embodiment, each flip-flop DFF of the asynchronous logic control circuit 403_AComprising a digital driver, flip-flops DFF_AThe digital driver of (1) is the digital driver provided in embodiment 1.

Thus, each flip-flop DFF_AThe digital driver of (1) is the digital driver provided in embodiment 1, each flip-flop DFF_ARespective flip-flops DFF having the structures and advantages of the digital driver in embodiment 1_AThe digital driver consists of unbalanced NMOS transistors and PMOS transistors, the widths of the NMOS transistors and the PMOS transistors are adjusted according to preset reduction factors, SAR logic delay is reduced, and the speed bottleneck of a single-pass SAR ADC can be overcome.

In one embodiment, each flip-flop DFF of the DAC switch control circuit 404_DComprising a digital driver, flip-flops DFF_DThe digital driver of (1) is the digital driver provided in embodiment 1.

Thus, each flip-flop DFF_DThe digital driver of (1) is the digital driver provided in embodiment 1, each flip-flop DFF_DAccordingly, the structure and advantages of the digital driver in embodiment 1, flip-flops DFF_DThe digital driver consists of unbalanced NMOS transistors and PMOS transistors, the widths of the NMOS transistors and the PMOS transistors are adjusted according to preset reduction factors, SAR logic delay is reduced, and the speed bottleneck of a single-pass SAR ADC can be overcome.

In one embodiment, the predetermined reduction factor of each digital driver of the capacitive DAC401 is [0.25, 0.5 ].

In one embodiment, the predetermined reduction factor of the digital driver of each flip-flop is in the range of [0.1, 0.25 ].

The value range of the preset reduction factor is described below with reference to fig. 5A.

For the SAR ADC, values of the corresponding preset reduction factors α are set according to different positions of the logic gate in the feedback path. As shown in fig. 5A, the feedback loop of the SAR ADC is divided into 3 critical delay paths, path 1, path 2, and path 3. Path 1 shows the path for the gating and resetting of the transition phase comparison module 402. In path 1, the rising and falling edges control the reset and strobe of the comparator, respectively, both of which are critical to the overall slew rate. Conventional size logic is used in this path 1, such as selecting NAND gates, NOR gates to ensure similar rising and falling edges. Path 2 shows the path between the comparator 4021, the asynchronous logic control circuit 403, and the DAC switch control circuit 404, outputting the generated "Ready" signal from the comparator 4021 to the asynchronously controlled SAR logic clock CLK_i. Path 3 shows the path from DAC switch control logic DAC 404 to digital driver 4011_iTo capacitor C_iBetween the bottom plates.

Please refer to fig. 5B, phi_SA clock representing a signal sample; SAR conversion represents a clock for performing successive approximation conversion on the obtained signal after sampling is completed; phi_compIndicating comparator clock signals, Ready signal tablesThe valid signal is shown at the asynchronous logic control circuit. CLK₁Representing a first SAR clock generated by asynchronous control logic in the conversion process of successive approximation; DAC₁Representing the digital-to-analog conversion (DAC) signal corresponding to the first clock cycle generated by the asynchronous control logic during the conversion process of successive approximation. Similarly, CLK_iRepresenting the ith SAR clock generated by asynchronous control logic in the conversion process of successive approximation; DAC_iRepresents the digital-to-analog conversion (DAC) signal corresponding to the ith clock cycle generated by the asynchronous control logic during the conversion process of successive approximation. For this example, the directionality of the critical edges as shown is common, e.g., CLK_iAnd DAC_iThe critical edge of (c) is always a rising edge.

In this embodiment, non-critical edges are placed in the sampling phase and critical edges are placed in the conversion phase of the SAR. SAR logic clock CLK with asynchronous control_iFor example, CLK may be used without affecting the performance of the ADC_iThere is as much time as more than the entire sampling phase to complete the non-critical edge transition (reset). The preset reduction factor α on path 2 may thus be as small as possible, for example, the preset reduction factor α may be chosen between 0.1 and 0.25.

In SAR logic feedback loops, registers such as DFFs typically occupy a significant portion of the delay time and power consumption. The DFF can be redesigned to optimize using a scheme that unbalances the size of the N/P-MOS transistors. In one aspect, the number of logic gates required for critical propagation paths in a DFF is reduced. On the other hand, the critical path delay is further reduced by using logic gates of unbalanced N/P-MOS size. Referring to fig. 6, compared with the conventional flip-flop, the delay time of the post simulation of the layout of the flip-flop (DFF) provided in this embodiment is reduced by more than 77%. For path 3, special attention needs to be paid to capacitor C when performing one-sided optimization_iA reset condition of (1). In fact, the capacitor C_iToo slow a reset may affect the sampling accuracy of the ADC. In this scheme, as shown in FIG. 5A, a sampling clock φ is used_SDirect reset DAC switch control signal DAC_i. In path 3, the predetermined reduction factor α can be selected between 0.25 and 0.5 to improve the transitionThe one-way high-speed propagation of the switching phase is realized, and the moderate reset capability of the DAC is kept in the sampling phase. In addition, the unbalanced N/P-MOS sizing approach not only reduces the load capacitance of the various nodes on the critical path, but also significantly reduces the number of buffers required to drive them, thereby further reducing logic delay and power consumption.

By adopting the feedback circuit for the analog-to-digital converter provided by the embodiment, a 10-bit SAR ADC is manufactured in a 28nmCMOS process, and the effective area of the SAR ADC is 0.0023mm². The 10-Bit SAR ADC has 11 periods, wherein the 11 periods comprise 1-Bit redundancy, the first two Most Significant Bits (MSB) adopt a split monotonic switched capacitor structure, and the rest bits adopt a pure monotonic switched capacitor structure. A custom designed metal-oxide-metal (MOM) capacitor array is used as the input capacitance of the SAR ADC with a single-sided input capacitance of 180fF, so that the Integrated Nonlinearity (INL) reaches-0.51/+ 0.60 Least Significant Bits (LSB) at 10 bits. The SAR ADC has a test result under a power supply voltage of 0.9V, and the Nyquist signal-to-noise-and-distortion ratio (SNDR)/the Spurious Free Dynamic Range (SFDR) of the SAR ADC are respectively 56.0dB and 71.5dB when the SAR ADC works at 550 MS/s.

The SAR ADC provided by the present embodiment breaks the physical speed limit of single-channel 10b SAR, and achieves higher f than operation with similar Waldens optimal values (FOMW) without any calibration_snyqSimultaneously comparing all f_snyq>FOM for 501MHz operation_WAt least 2 times lower/1.8 times lower. In addition, it should be noted that the feedback circuit for the analog-to-digital converter provided by the present embodiment is fully applicable to many SAR variants, such as time-interleaved SAR (TI-SAR), Pipelined SAR (Pipelined SAR), and Noise-Shaping SAR (Noise-Shaping-SAR).

Example 3

In addition, the disclosed embodiment provides an analog-to-digital converter including the feedback circuit for an analog-to-digital converter provided in embodiment 2.

The analog-to-digital converter provided in this embodiment includes the feedback circuit for the analog-to-digital converter provided in embodiment 2, so that the analog-to-digital converter has the corresponding structure, function, and beneficial effects of the feedback circuit for the analog-to-digital converter provided in embodiment 2, and further description is omitted here to avoid repetition.

Example 4

In addition, the disclosed embodiments provide an electronic device comprising the analog-to-digital converter provided in embodiment 3.

The electronic device provided in this embodiment includes the analog-to-digital converter provided in embodiment 3, and thus has the corresponding structure, function, and beneficial effects of the analog-to-digital converter provided in embodiment 3, and is not described herein again to avoid repetition.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A digital driver, comprising: an input terminal, an output terminal, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

2. The digital driver of claim 1, wherein the delay time of the digital driver is positively correlated with the preset reduction factor.

3. A feedback circuit for an analog-to-digital converter, comprising: the capacitive DAC circuit comprises a capacitive DAC, a comparison circuit, an asynchronous logic control circuit and a DAC switch control circuit;

the capacitive DAC comprising a plurality of capacitors and a plurality of digital drivers, each of the digital drivers being as claimed in claim 1 or 2;

4. The feedback circuit for an analog-to-digital converter according to claim 3, wherein the comparison circuit comprises: the input end of the comparator is connected with the output end of the capacitance type DAC, the output end of the comparator is connected with the input end of the NOR gate, the output end of the NOR gate is connected with the input end of the first phase inverter, and the output end of the first phase inverter is connected with the input end of each trigger of the asynchronous logic control circuit.

5. The feedback circuit for an analog-to-digital converter according to claim 4, wherein the comparison circuit further comprises: the first input end and the second input end of the NAND gate are respectively connected with the output end of the NOR gate and the output end of the second inverter, the output end of the NAND gate is connected with the control end of the comparator, and the input end of the second inverter is used for receiving a sampling signal.

6. A feedback circuit for an analog to digital converter according to claim 3, wherein each flip-flop comprises a digital driver, the digital driver of each flip-flop being the digital driver of claim 1 or 2.

7. The feedback circuit for an analog-to-digital converter according to claim 3, wherein the preset reduction factor of each digital driver of the capacitive DAC is [0.25, 0.5 ].

8. The feedback circuit for an analog-to-digital converter according to claim 6, wherein the preset reduction factor of the digital driver of each flip-flop is in a range of [0.1, 0.25 ].

9. An analog-to-digital converter, characterized in that it comprises a feedback circuit for an analog-to-digital converter according to any one of claims 3-8.

10. An electronic device, characterized in that it comprises an analog-to-digital converter as claimed in claim 9.