CN114499528A - Digital driver, feedback circuit for analog-to-digital converter, and digital-to-analog converter - Google Patents

Abstract

An embodiment of the present application provides a digital driver, including: an input terminal, an output terminal, first, second, third, and fourth PMOS transistors, and first, second, third, and fourth NMOS transistors; an input terminal, a first PMOS transistor, and a third An NMOS tube is connected; the first PMOS tube, the first NMOS tube, the second PMOS tube and the second NMOS tube are connected to the first node; the second PMOS tube, the second NMOS tube, the third PMOS tube and the third NMOS tube are connected at the second node; the third PMOS tube, the third NMOS tube, the fourth PMOS tube and the fourth NMOS tube are connected to the third node; the fourth PMOS tube, the fourth NMOS tube and the output terminal are connected; each PMOS tube, each NMOS tube The width of the tube is determined according to the mobility and a preset reduction factor. In this way, by adjusting the size of the transistors with a preset shrink factor, the delay time and power consumption can be reduced.

Description

Digital drivers, feedback circuits for analog-to-digital converters, digital-to-analog converters

technical field

The present application relates to the field of electronic technology, and in particular, to a digital driver, a feedback circuit for an analog-to-digital converter, and a digital-to-analog converter.

Background technique

The existing traditional successive approximation analog-to-digital converter (Successive Approximation Register Analog-to-Digital Converter, SAR ADC) includes a tracking sample and hold circuit (T/H), a comparator, SAR logic circuit and a capacitive digital-to-analog converter (Digital-to-Analog Converter, DAC), this traditional structure has the advantages of low complexity, low power consumption and high-efficiency topology with reduced process technology, which makes the traditional structure widely used in high-speed applications. For example, the traditional structure can be used with in a time-interleaved successive approximation analog-to-digital converter (TI-SAR ADC). Some existing solutions speed up the conversion of the SAR ADC by improving the topology of one bit per cycle, such as the structure of a SAR with multiple bits per cycle and a SAR with N bits and N comparators. However, the bit-per-cycle topology of the traditional structure still has clear advantages in terms of low complexity, less parasitics, and less misalignment. Therefore, most high-speed TI-SAR ADCs still prefer the traditional one-bit-per-cycle structure. The use of an architecture with redundant bits in a high-speed SAR ADC allows the settling time required for the DAC to be very short. However, limited by the digital SAR logic delay time per cycle, slow speed is still the main bottleneck of SAR ADCs with traditional architectures.

SUMMARY OF THE INVENTION

In order to solve the above technical problems, embodiments of the present application provide a digital driver, a feedback circuit for an analog-to-digital converter, a digital-to-analog converter, and an electronic device.

In a first aspect, an embodiment of the present application provides an analog-to-digital converter, including:

an input terminal, an output terminal, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

the input terminal is connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor;

The drain of the first PMOS transistor, the drain of the first NMOS transistor, the gate of the second PMOS transistor and the gate of the second NMOS transistor are connected to the first node;

The drain of the second PMOS transistor, the drain of the second NMOS transistor, the gate of the third PMOS transistor and the gate of the third NMOS transistor are connected to the second node;

The drain of the third PMOS transistor, the drain of the third NMOS transistor, the gate of the fourth PMOS transistor and the gate of the fourth NMOS transistor are connected to the third node;

The drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are connected to the output terminal; wherein the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the The widths of the fourth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are based on the PMOS transistor mobility, the NMOS transistor mobility, and a preset scaling factor It is determined that the value range of the preset reduction coefficient is (0, 1).

In a second aspect, an embodiment of the present application provides a feedback circuit for an analog-to-digital converter, where the feedback circuit for the analog-to-digital converter includes:

Capacitive DAC, comparison circuit, asynchronous logic control circuit and DAC switch control circuit;

The capacitive DAC includes a plurality of capacitors and a plurality of digital drivers, and each of the digital drivers is the digital driver provided by the first aspect;

The asynchronous logic control circuit and the DAC switch control circuit respectively include a plurality of flip-flops;

Each capacitor is connected to the input terminal of the corresponding digital driver, and the output terminal of the capacitive DAC is connected to the input terminal of the comparison circuit;

The output end of the comparison circuit is connected with the input end of each flip-flop of the asynchronous logic control circuit;

The output end of each trigger of the asynchronous logic control circuit is connected with the input end of the corresponding trigger of the DAC switch control circuit;

The output end of each flip-flop of the DAC switch control circuit is connected with the input end of the corresponding digital driver.

In a third aspect, an embodiment of the present application provides an analog-to-digital converter, including the feedback circuit for the analog-to-digital converter provided in the second aspect.

In a fourth aspect, an embodiment of the present application provides an electronic device, including the analog-to-digital converter provided in the third aspect.

The above-mentioned digital driver, feedback circuit for analog-to-digital converter, digital-to-analog converter and electronic equipment provided by the present application can adjust the size of NMOS transistors and PMOS transistors by a preset reduction factor, which can reduce delay time and power consumption.

Description of drawings

In order to illustrate the technical solutions of the present application more clearly, the following briefly introduces the accompanying drawings used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be It is regarded as a limitation on the protection scope of this application. In the various figures, similar components are numbered similarly.

FIG. 1 shows a schematic structural diagram of a digital driver provided by an embodiment of the present application;

FIG. 2 shows a schematic diagram of a time delay comparison provided by an embodiment of the present application;

3 shows a schematic diagram of a simulation result of a digital driver provided by an embodiment of the present application;

4A shows another schematic structural diagram of a feedback circuit for an analog-to-digital converter provided by an embodiment of the present application;

FIG. 4B shows a schematic diagram of a signal change provided by an embodiment of the present application;

FIG. 5A shows another schematic structural diagram of a feedback circuit for an analog-to-digital converter provided by an embodiment of the present application;

FIG. 5B shows another schematic diagram of signal change provided by an embodiment of the present application;

FIG. 6 shows a schematic diagram of a simulation of a flip-flop provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Thus, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

Hereinafter, the terms "comprising", "having" and their cognates, which may be used in various embodiments of the present application, are only intended to denote particular features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the presence or addition of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing or the possibility of a combination of the foregoing.

Furthermore, the terms "first", "second", "third", etc. are only used to differentiate the description and should not be construed as indicating or implying relative importance.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application belong. The terms (such as those defined in commonly used dictionaries) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized or overly formal meaning, unless explicitly defined in the various embodiments of the present application.

Example 1

Embodiments of the present disclosure provide a digital driver.

Specifically, referring to FIG. 1, FIG. 1 shows a schematic structural diagram of a digital driver 10. The digital driver 10 includes: an input terminal IN, an output terminal OUT, a first P-Metal-Oxide-Semiconductor (P-Metal-Oxide-Semiconductor, PMOS) transistor M _P1 , second PMOS transistor M _P2 , third PMOS transistor M _P3 , fourth PMOS transistor M _P4 , first N-Metal-Oxide-Semiconductor (NMOS) transistor M _N1 , the second NMOS transistor _MN2 , the third NMOS transistor _MN3 and the fourth NMOS transistor _MN4 ;

the input terminal is connected to the gate of the first PMOS transistor and the gate of the first NMOS transistor;

The drain of the first PMOS transistor M _P1 , the drain of the first NMOS transistor M _N1 , the gate of the second PMOS transistor M _P2 and the gate of the second NMOS transistor M _N2 are connected to the first node A;

The drain of the second PMOS transistor M _P2 , the drain of the second NMOS transistor M _N2 , the gate of the third PMOS transistor and the gate of the third NMOS transistor are connected to the second node B;

The drain of the third PMOS transistor M _P3 , the drain of the third NMOS transistor M _N3 , the gate of the fourth PMOS transistor M _P4 and the gate of the fourth NMOS transistor M _N4 are connected to the third node C;

The drain of the fourth PMOS transistor M _P4 and the drain of the fourth NMOS transistor M _N4 are connected to the output terminal; wherein the first PMOS transistor M _P1 , the second PMOS transistor M _P2 , the the third PMOS transistor M _P3 , the fourth PMOS transistor M _P4 , the first NMOS transistor M _N1 , the second NMOS transistor M _N2 , the third NMOS transistor M _N3 , the fourth NMOS The width of the transistor _MN4 is determined according to the mobility of the PMOS transistor, the mobility of the NMOS transistor, and a preset scaling factor, and the preset scaling factor has a value range of (0, 1).

其中，W_P2表示第二PMOS晶体管M_P2的宽度，W_N2表示第二NMOS晶体管M_N2的宽度，μ_p表示PMOS晶体管的迁移率，μ_n表示NMOS晶体管的迁移率。所述第三PMOS晶体管M_P3、所述第三NMOS晶体管M_N3的宽度之间存在以下关系式2：

其中，W_N3表示第三NMOS晶体管M_N3的宽度，W_P3表示第三PMOS晶体管W_P3的宽度，μ_p表示PMOS晶体管的迁移率，μ_n表示NMOS晶体管的迁移率。In this embodiment, the NMOS transistor and the PMOS transistor may be referred to as NMOS transistors and PMOS transistors for short. Due to the introduction of the preset scaling factor, the digital driver 10 can be understood as an unbalanced driver. In a conventional digital driver, the aspect ratio of the NMOS transistor and the PMOS transistor is approximately equal to the ratio of the mobility of the NMOS transistor to the mobility of the PMOS transistor. For example, when the digital driver 10 shown in FIG. 1 does not use the preset scaling factor provided by this embodiment, the following relational expression 1 exists between the widths of the second _PMOS transistor MP2 and the second NMOS transistor _MN2 :

Wherein, W _P2 represents the width of the second PMOS transistor _MP2 , W _N2 represents the width of the second NMOS transistor _MN2 , μ _p represents the mobility of the PMOS transistor, and μ _n represents the mobility of the NMOS transistor. The following relational formula 2 exists between the widths of the third PMOS transistor M _P3 and the third NMOS transistor M _N3 :

Wherein, W _N3 represents the width of the third NMOS transistor _MN3 , W _P3 represents the width of the third PMOS transistor _WP3 , μ _p represents the mobility of the PMOS transistor, and μ _n represents the mobility of the NMOS transistor.

In this embodiment, the widths of the corresponding NMOS transistors and PMOS transistors are reduced by using a preset reduction factor. For example, in FIG. 1 , the widths of the second _PMOS transistor MP2 and the second NMOS transistor _MN2 are determined by the following formula 1, and the widths of the third PMOS transistor _{MP3 and the third NMOS transistor MN3 are} determined by The following formula 2 is determined.

Formula 1:

Wherein, W _P2 represents the width of the second PMOS transistor _MP2 , W _N2 represents the width of the second NMOS transistor _MN2 , μ _p represents the mobility of the PMOS transistor, μ _n represents the mobility of the NMOS transistor; α represents a preset scaling factor .

Formula 2:

Wherein, W _N3 represents the width of the third NMOS transistor _MN3 , W _P3 represents the width of the third PMOS transistor _WP3 , μ _p represents the mobility of the PMOS transistor, μ _n represents the mobility of the NMOS transistor; α represents the preset scaling factor .

而所述第四PMOS晶体管M_P4和所述第四NMOS晶体管M_N4之间的宽度比值约等于

It should be noted that the width ratio between the first NMOS transistor M _N1 and the first PMOS transistor M _P1 is approximately equal to

And the width ratio between the fourth PMOS transistor _MP4 and the fourth NMOS transistor _MN4 is approximately equal to

With reference to the digital driver 10 of FIG. 1 , if the preset reduction factor provided in this embodiment is not adopted, based on the edge direction in the first node A, the input terminal IN is directed to the first node A, and the first node A is changed from a low level to a low level. The pull-to-high delay time is determined by Equation 3 below.

From the first node A to the second node B, the delay time for pulling the second point B from a high level to a low level is determined by the following formula 4.

Formula 3: t _pLH,A ≈ _{0.69R eqP,A} C _L,A ;

L表示第一PMOS晶体管M_P1的长度，表示PMOS晶体管迁移率，W_P1表示第一PMOS晶体管M_P1的宽度；C_L,A是第一节点A的等效负载电容，C_L,A∝(W_N2+W_P2)L，W_N2表示第二NMOS晶体管M_N2的宽度，W_P2表示第二PMOS晶体管M_P2的宽度，L表示第二NMOS晶体管M_N2的长度或者第二PMOS晶体管M_P2的长度；t_pLH,A表示输入端子IN向第一节点A，将第一节点A由低电平拉到高电平的延迟时间。Wherein, R _eqP,A is the equivalent on-resistance of the first PMOS transistor M _P1 ,

L represents the length of the first PMOS transistor M _P1 , represents the mobility of the PMOS transistor, W _P1 represents the width of the first PMOS transistor M _P1 ; C _L,A is the equivalent load capacitance of the first node A, C _L,A ∝( W _N2 +W _P2 )L, W _N2 represents the width of the second NMOS transistor M _N2 , W _P2 represents the width of the second PMOS transistor M _P2 , L represents the length of the second NMOS transistor M _N2 or the length of the second PMOS transistor M _P2 Length; t _pLH,A represents the delay time for the input terminal IN to the first node A to pull the first node A from a low level to a high level.

Formula 4: t _pHL,B ≈ 0.69R _eqN,B C _L,B ;

L表示第二NMOS晶体管M_N2的长度,μ_N表示NMOS晶体管迁移率，W_N2表示第二NMOS晶体管M_N2的宽度；C_L,B是第E二节点B的等效负载电容，C_L,B∝(W_N3+W_P3)L，W_N3表示第三NMOS晶体管M_N3的宽度，W_P3表示第三PMOS晶体管M_P3的宽度，L表示第三NMOS晶体管M_N3的长度或者第三PMOS晶体管M_P3的长度；t_pHL,B表示第一节点A向第二节点B，将第二节点B点由高电平拉到低电平的延迟时间。Wherein, R _eqN,B is the equivalent on-resistance of the first PMOS transistor M _P1 ,

L represents the length of the second NMOS transistor MN2, μ _N represents the mobility of the NMOS transistor, W _N2 represents the width of the second NMOS transistor _MN2 ; _{CL , B} is the equivalent load capacitance of the second node B of E, _{CL, B} ∝(W _N3 +W _P3 )L, W _N3 represents the width of the third NMOS transistor _MN3 , W _P3 represents the width of the third PMOS transistor M _P3 , L represents the length of the third NMOS transistor _MN3 or the third PMOS transistor The length of M _P3 ; t _pHL,B represents the delay time from the first node A to the second node B, and the second node B is pulled from the high level to the low level.

It can be seen that, for the digital driver 10 in FIG. 1 , if the preset reduction factor provided in this embodiment is not used, the corresponding delay time can be determined by the following formula 5.

Formula 5:

Wherein, T _{delay-regular} represents the time delay of the digital driver 10 shown in FIG. 1 when the preset reduction factor provided in this embodiment is not used; t _pLH,A represents the input terminal IN to the first node A, the first node A The delay time from the low level to the high level; t _pHL,B represents the delay time from the first node A to the second node B, and the second node B is pulled from the high level to the low level; in formula 5 The meanings of W _P1 , W _P2 , W _P3 , W _N2 , W _N3 , μ _P , and μ _N are the same as those described above, and will not be repeated here.

For the digital driver 10 in FIG. 1 , if the preset reduction factor provided in this embodiment is not used, the corresponding power consumption can be determined by the following formula 6.

Formula 6: P _regular ∝[(W _N2 +W _P2 )+(W _N3 +W _P3 )];

Wherein, P _regular represents the corresponding power consumption of the digital driver 10 in FIG. 1 if the preset reduction factor provided in this embodiment is not used. The meanings of W _P2 , W _P3 , W _N2 , and W _N3 are the same as those described above, and are not repeated here.

This embodiment adopts a preset reduction factor, and the second PMOS transistor _MP2 adopts a preset reduction factor α to reduce the width W _P2 of the second PMOS transistor _MP2 , thereby reducing _CL,A , so that as shown in FIG. 1 , After the digital driver 10 adopts the preset reduction factor α, the delay time of the digital driver 10 can be determined according to the following formula 7.

Formula 7:

Wherein, T _{delay-proposed} represents the delay time after the digital driver 10 adopts the preset reduction factor α, and T _{delay-regular} represents the delay time when the digital driver 10 does not use the preset reduction factor α. α represents a preset reduction factor.

It is added that the delay time after the digital driver 10 adopts the preset reduction factor α is positively correlated with the preset reduction factor. Specifically, according to formula 7, it can be seen that the larger the preset reduction factor α is, the longer the delay time after the preset reduction factor α is adopted, and the smaller the preset reduction factor α is, the longer the delay time after the preset reduction factor α is adopted. Small. Please refer to FIG. 2. FIG. 2 shows a schematic diagram of the delay time of the digital driver. In FIG. 2, T _{delay-proposed} represents the delay time after the digital driver 10 adopts the preset reduction factor α, and T _{delay-regular} represents that the digital driver 10 does not The delay time when the preset reduction factor α is adopted, wherein T _{delay-proposed} is less than T _{delay-regular} .

In addition, after the digital driver 10 shown in FIG. 1 adopts the preset reduction factor α, the power of the digital driver 10 can be determined according to the following formula 8.

Formula 8:

Wherein, P _proposed represents the power after the digital driver 10 adopts the preset reduction factor α; P _regular represents the power when the digital driver 10 does not use the preset reduction factor α; α represents the preset reduction factor.

Please refer to Figure 3. Figure 3 shows a schematic diagram of the simulation results. If the preset reduction factor α=0.25, as shown in the histogram in Figure 3, the delay time of the actual circuit is reduced by 31.3% in the post-simulation of the layout. . In addition, the load capacitance and power consumption of each node of the logic transmission path are also reduced by (1+α)/2.

It should be noted that this scheme of using unbalanced NMOS transistor and PMOS transistor sizes to reduce delay and power consumption can also be extended to other digital logic circuits, such as NAND gates, NOR gates, and flip-flops (DFFs). logic gates, etc.

The digital driver provided in this embodiment adopts a preset reduction factor to adjust the size of the NMOS transistor and the PMOS transistor, which can reduce delay time and power consumption.

Example 2

Embodiments of the present disclosure also provide a feedback circuit for an analog-to-digital converter.

Specifically, referring to FIG. 4A, FIG. 4A shows a schematic structural diagram of a feedback circuit for an analog-to-digital converter. The feedback circuit 40 for the analog-to-digital converter includes:

Capacitive DAC 401, comparison circuit 402, asynchronous logic control circuit 403 and DAC switch control circuit 404;

The capacitive DAC includes a plurality of capacitors C ₁ , C ₂ , . . . , C _i , .

The asynchronous logic control circuit 403 includes a plurality of flip-flops DFF _A ; the DAC switch control circuit 404 includes a plurality of flip-flops DFF _D ;

Each capacitor C _i is connected to the input terminal of the corresponding digital driver 4011 , and the output terminal of the capacitive DAC 401 is connected to the input terminal of the comparison circuit 402 ;

The output end of the comparison circuit 402 is connected to the input end of each flip-flop DFF _A of the asynchronous logic control circuit 403;

The output terminal of each flip-flop DFF _A of the asynchronous logic control circuit 403 is connected to the input terminal of the corresponding flip-flop DFF _D of the DAC switch control circuit 404;

The output end of each flip-flop DFF _D of the DAC switch control circuit 404 is connected to the input end of the corresponding digital driver 4011 .

In this embodiment, each of the digital drivers 4011 is the digital driver provided in the first embodiment, and has the structure and advantages of the digital driver in the first embodiment. The digital driver 4011 is composed of unbalanced NMOS transistors and PMOS transistors. The widths of the NMOS transistors and PMOS transistors are adjusted according to a preset scaling factor to reduce the SAR logic delay to overcome the speed bottleneck of the single-pass SAR ADC.

In this embodiment, the analog-to-digital converter may be a monotonic capacitive switch SAR ADC, and the monotonic capacitive switch SAR ADC has the characteristics of switching only in a one-way switch DAC. Comparator-to-DAC delay can be reduced. The digital driver of this embodiment adopts a preset scaling factor, proposes the sizes of unbalanced NMOS transistors and PMOS transistors, improves the logic speed on critical edge transitions, and reduces the transistor size in non-critical edge directions.

This increases speed while simultaneously reducing power and area of the SAR ADC, thereby breaking the limiting factor that SAR ADCs need to trade off between power and latency. More importantly, this scheme does not change the classic one-bit-per-cycle (1b/cycle) structure, which makes it have all the advantages of the traditional architecture. The 10-bit 550MS/s SAR ADC of this embodiment is implemented in a CMOS process. At a speed of 550MS/s, the signal-to-noise and distortion ratio (SNDR) of the SAR ADC at the input signal frequency of Nyquist reaches 56.0dB, respectively. The consumption was 1.37 mW, resulting in Walden figures of merit (Walden FoM) of 4.78 fJ/conv-step (femtojoules per conversion), respectively.

The following describes the use process of the feedback circuit for the analog-to-digital converter with reference to FIG. 4A .

During the sampling phase, each digital driver 4011 resets the bottom plate of each capacitor C _i of the capacitive DAC 401 to VDD. The bottom plate of capacitor _{C i} for each bit is then switched to _{GND (} critical edge direction) or will remain unchanged at VDD (non-critical edge direction). As shown in Figure 1, for the bottom plate of the ith capacitor C _i , the critical speed edge is always the falling edge, and the critical speed edge of the corresponding DAC switch control signal (DAC _i ) is always the rising edge. Likewise, the critical speed edge corresponding to the asynchronously controlled SAR logic clock (CLK _i ) is always a rising edge, and all DFF _A applied to the asynchronous control logic are reset during the sampling phase. Combined with the above analysis, it can be concluded that from the bottom plate of the capacitor C _i to the digital driver 4011 , the DAC switch control signal (DAC _i ) output by the DAC switch control circuit 404 , and the SAR logic clock (CLK _i ) output by the asynchronous logic control circuit 403 The critical velocity edge is always deterministic and is in a single direction.

In most cases, N/P-MOS digital buffers that are balanced using transconductance (g _m ) are used to drive the switches of the capacitive DAC to ensure that the digital buffers have substantially symmetrical rising and falling edges, and similar N /P delay time. However, for the logic driver of a monotonic capacitive DAC switch, it is unidirectional every cycle in every SAR conversion. This means that only critical data transfers need to be optimized in one direction. The digital driver 4011 in FIG. 4A is the digital driver provided in Embodiment 1. Combining with the digital driver 10 shown in FIG. 1 , it can be known that the digital driver is composed of _unbalanced N/P-MOS transistors. The node "OUT" of the plate is switched to GND or left unchanged. Therefore, the critical edges in the output terminal OUT, the third node C, the second node B, and the first node A are always falling/rising/falling/rising edges, respectively. For the structure and implementation principle of the digital driver 4011 in FIG. 4A , reference may be made to the related description of the digital driver 10 in Embodiment 1, which will not be repeated here.

Please refer to FIG. 4A again, the comparison circuit 402 includes: a comparator 4021, a NOR gate 4022 and a first inverter 4023, the input end of the comparator 4021 is connected to the output end of the capacitive DAC 401, and the comparison The output terminal of the inverter 4021 is connected to the input terminal of the NOR gate 4022, the output terminal of the NOR gate 4022 is connected to the input terminal of the first inverter 4023, and the output terminal of the first inverter 4023 is connected to the input terminal of the first inverter 4023. The input ends of each flip-flop of the asynchronous logic control circuit 403 are connected.

Referring to FIG. 4B, OUT _P /OUT _N respectively represent the two corresponding output signals of the fully differential comparator, and the Ready signal represents the valid signal in the asynchronous SAR logic conversion. Φ _comp represents the clock signal of the comparator, CLK _i represents the asynchronous control clock of the SAR logic, and the function of CLK _i is to indicate that the cycle of the i-th SAR is being converted. DAC _i represents the digital-to-analog conversion information of the i-th DAC. In FIG. 4B , the first curve 41 and the second curve 42 represent that the next rising/falling edge is triggered by the previous rising/falling edge. The first arrow line segment 43 represents the rising edge, and the second arrow line segment 44 represents the falling edge.

Please refer to FIG. 5A. The difference between the feedback circuit for the analog-to-digital converter shown in FIG. 5A and the feedback circuit for the analog-to-digital converter shown in FIG. 4A is that the comparison circuit 402 further includes: a second Inverter 4024 and NAND gate 4025, the first input terminal and the second input terminal of the NAND gate are respectively connected with the output terminal of the NOR gate 4022 and the output terminal of the second inverter 4024, the NAND gate The output terminal of the gate 4025 is connected to the control terminal of the comparator 4021, and the input terminal of the second inverter 4024 is used for receiving the sampling signal.

In one embodiment, each flip-flop DFF _A of the asynchronous logic control circuit 403 includes a digital driver, and the digital driver of each flip-flop DFF _A is the digital driver provided in Embodiment 1.

In this way, the digital driver of each flip-flop DFF _A is the digital driver provided in Embodiment 1, and each flip-flop DFF _A correspondingly has the structure and advantages of the digital driver in Embodiment 1. The digital driver of each flip-flop DFF _A is composed of an unbalanced It consists of NMOS transistors and PMOS transistors. The widths of the NMOS transistors and PMOS transistors are adjusted according to the preset scaling factor to reduce the SAR logic delay and overcome the speed bottleneck of the single-pass SAR ADC.

In one embodiment, each flip-flop DFF _D of the DAC switch control circuit 404 includes a digital driver, and the digital driver of each flip-flop DFF _D is the digital driver provided in Embodiment 1.

In this way, the digital driver of each flip-flop DFF _D is the digital driver provided in Embodiment 1, and each flip-flop DFF _D has the structure and advantages of the digital driver in Embodiment 1 correspondingly, and the digital driver of each flip-flop DFF _D is composed of unbalanced digital drivers. It is composed of NMOS transistor and PMOS transistor. The width of NMOS transistor and PMOS transistor is adjusted according to the preset reduction factor, which reduces the SAR logic delay and can overcome the speed bottleneck of single-pass SAR ADC.

In one embodiment, the value range of the preset scaling factor of each digital driver of the capacitive DAC 401 is [0.25, 0.5].

In one embodiment, the value range of the preset reduction factor of the digital driver of each flip-flop is [0.1, 0.25].

The value range of the preset reduction factor will be described below with reference to FIG. 5A .

For the SAR ADC, the value of the corresponding preset reduction factor α is set according to different positions of the logic gate in the feedback path. As shown in Figure 5A, the feedback loop of the SAR ADC is divided into three key delay paths, namely Path 1, Path 2, and Path 3. Path 1 shows the strobe and reset path of the compare module 402 during the conversion phase. In Path 1, since the rising and falling edges control the reset and strobe of the comparator, respectively, both are critical to the overall slew rate. So use traditional regular size logic in this path 1, eg select NAND gates, NOR gates to ensure similar rising and falling edges. Path 2 shows the path between the comparator 4021, the asynchronous logic control circuit 403 and the DAC switch control circuit 404, from which the generated "Ready" signal is output to the asynchronously controlled SAR logic clock _CLKi . Path 3 shows the path between the DAC switch control circuit 404 to the digital driver 4011, from the DAC switch control logic DAC _i to the bottom plate of capacitor C _i .

Please refer to Fig. 5B, Φ _S represents the signal sampling clock; SAR conversion represents the clock for successive approximation conversion of the obtained signal after the sampling is completed; Φ _comp represents the comparator clock signal, and the Ready signal represents the effective signal in the asynchronous logic control circuit Signal. CLK ₁ represents the first SAR clock generated by the asynchronous control logic in the successive approximation conversion process; DAC ₁ represents the digital-to-analog conversion (DAC) corresponding to the first clock cycle generated by the asynchronous control logic in the successive approximation conversion process Signal. Similarly, CLK _i represents the i-th SAR clock generated by the asynchronous control logic in the successive approximation conversion process; DAC _i represents the digital-to-analog conversion corresponding to the i-th clock cycle generated by the asynchronous control logic in the successive approximation conversion process (DAC) signal. For this example, the directionality of the critical edges shown in the figure is universal, such as the critical edges of CLK _i and DAC _i are always rising edges.

In this embodiment, the non-critical edges are placed in the sampling stage, and the critical edges are placed in the conversion stage of the SAR. Taking the asynchronously controlled SAR logic clock CLK _i as an example, CLK _i has as much as more than the entire sampling phase to complete non-critical edge transitions (resets) without affecting the performance of the ADC. Therefore, the preset reduction factor α on path 2 can be as small as possible, for example, the preset reduction factor α can be selected between 0.1 and 0.25.

In the SAR logic feedback loop, registers such as DFF generally occupy a major part of the delay time and power consumption. The DFF can be redesigned to optimize the size of the N/P-MOS transistors using an unbalanced approach. On the one hand, reducing the number of logic gates required for the critical propagation path in the DFF. On the other hand, using unbalanced N/P-MOS size logic gates further reduces critical path delays. Referring to FIG. 6 , compared with the conventional flip-flop, the delay time of the flip-flop (DFF) provided in this embodiment is reduced by more than 77% in the post-simulation of the layout. For path 3, special attention needs to be paid to the reset of capacitor C _i when performing unilateral optimization. In fact, too slow reset of the capacitor C _i will affect the sampling accuracy of the ADC. In this solution, as shown in FIG. 5A , the DAC switch control signal DAC _i is directly reset by using the sampling clock φ _S . In path 3, the preset reduction factor α can be selected between 0.25 and 0.5 to improve the one-way high-speed propagation in the conversion stage, while maintaining the moderate reset capability of the DAC in the sampling stage. In addition, the unbalanced N/P-MOS sizing method not only reduces the load capacitance of individual nodes on the critical path, but also significantly reduces the number of buffers required to drive them, which further reduces logic latency and power consumption.

Using the feedback circuit for the analog-to-digital converter provided in this embodiment, a 10-bit SAR ADC is fabricated in a 28 nm CMOS process, and its effective area is 0.0023 mm ² . The 10-bit SAR ADC has 11 cycles, and the 11 cycles include 1-bit redundancy. The first two Most Significant Bits (MSBs) use a split monotonic switched capacitor structure, and the remaining bits use a pure monotonic switched capacitor structure. A custom-designed metal-oxide-metal (MOM) capacitor array is used as the input capacitance of the SARADC with a single-sided input capacitance of 180fF, which enables Integral Nonlinearity (INL) to reach -0.51/+ at 10 bits 0.60 Least Significant Bit (LSB). The SAR ADC is tested at 0.9V supply voltage. When operating at 550MS/s, its Nyquist signal-to-noise and distortion ratio (SNDR)/spurious free dynamic range (SFDR) are 56.0dB and 71.5dB, respectively.

The SAR ADC provided by this embodiment breaks through the physical speed limit of a single-channel 10b SAR, and without any calibration, achieves a higher fsnyq than work with similar Walden figure of merit ( _FOMW ), while All _fsnyq >501MHz operation have at least 2x/1.8x lower FOM _W. In addition, it should be noted that the feedback circuit for the analog-to-digital converter provided in this embodiment is fully applicable to many SAR variants, such as time-interleaved SAR (TI-SAR), pipelined SAR (Pipelined-SAR), and noise Shaping SAR (Noise-Shaping-SAR).

Example 3

In addition, an embodiment of the present disclosure provides an analog-to-digital converter, where the analog-to-digital converter includes the feedback circuit for the analog-to-digital converter provided in Embodiment 2.

The analog-to-digital converter provided in this embodiment includes the feedback circuit for the analog-to-digital converter provided in the second embodiment, and therefore has the corresponding structure and function of the feedback circuit for the analog-to-digital converter provided in the second embodiment and beneficial effects, in order to avoid repetition, no further description is given here.

Example 4

In addition, an embodiment of the present disclosure provides an electronic device, and the electronic device includes the analog-to-digital converter provided in Embodiment 3.

The electronic device provided in this embodiment includes the analog-to-digital converter provided in the third embodiment, and therefore has the corresponding structure, function and beneficial effects of the analog-to-digital converter provided in the third embodiment. Repeat.

The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical scope disclosed by the present invention can easily think of changes or substitutions. All should be included within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. A digital driver, comprising: an input terminal, an output terminal, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;

the input terminal is connected with the gate of the first PMOS transistor and the gate of the first NMOS transistor;

the drain electrode of the first PMOS transistor, the drain electrode of the first NMOS transistor, the grid electrode of the second PMOS transistor and the grid electrode of the second NMOS transistor are connected to a first node;

the drain electrode of the second PMOS transistor, the drain electrode of the second NMOS transistor, the grid electrode of the third PMOS transistor and the grid electrode of the third NMOS transistor are connected to a second node;

the drain electrode of the third PMOS transistor, the drain electrode of the third NMOS transistor, the grid electrode of the fourth PMOS transistor and the grid electrode of the fourth NMOS transistor are connected to a third node;

a drain of the fourth PMOS transistor, a drain of the fourth NMOS transistor, and the output terminal are connected; the widths of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are determined according to the mobility of the PMOS transistors, the mobility of the NMOS transistors and a preset reduction coefficient, and the value range of the preset reduction coefficient is (0, 1).

2. The digital driver of claim 1, wherein the delay time of the digital driver is positively correlated with the preset reduction factor.

3. A feedback circuit for an analog-to-digital converter, comprising: the capacitive DAC circuit comprises a capacitive DAC, a comparison circuit, an asynchronous logic control circuit and a DAC switch control circuit;

the capacitive DAC comprising a plurality of capacitors and a plurality of digital drivers, each of the digital drivers being as claimed in claim 1 or 2;

the asynchronous logic control circuit and the DAC switch control circuit respectively comprise a plurality of triggers;

each capacitor is connected with an input terminal of a corresponding digital driver, and an output end of the capacitive DAC is connected with an input end of the comparison circuit;

the output end of the comparison circuit is connected with the input end of each trigger of the asynchronous logic control circuit;

the output end of each trigger of the asynchronous logic control circuit is connected with the input end of the corresponding trigger of the DAC switch control circuit;

and the output end of each trigger of the DAC switch control circuit is connected with the input end of the corresponding digital driver.

4. The feedback circuit for an analog-to-digital converter according to claim 3, wherein the comparison circuit comprises: the input end of the comparator is connected with the output end of the capacitance type DAC, the output end of the comparator is connected with the input end of the NOR gate, the output end of the NOR gate is connected with the input end of the first phase inverter, and the output end of the first phase inverter is connected with the input end of each trigger of the asynchronous logic control circuit.

5. The feedback circuit for an analog-to-digital converter according to claim 4, wherein the comparison circuit further comprises: the first input end and the second input end of the NAND gate are respectively connected with the output end of the NOR gate and the output end of the second inverter, the output end of the NAND gate is connected with the control end of the comparator, and the input end of the second inverter is used for receiving a sampling signal.

6. A feedback circuit for an analog to digital converter according to claim 3, wherein each flip-flop comprises a digital driver, the digital driver of each flip-flop being the digital driver of claim 1 or 2.

7. The feedback circuit for an analog-to-digital converter according to claim 3, wherein the preset reduction factor of each digital driver of the capacitive DAC is [0.25, 0.5 ].

8. The feedback circuit for an analog-to-digital converter according to claim 6, wherein the preset reduction factor of the digital driver of each flip-flop is in a range of [0.1, 0.25 ].

9. An analog-to-digital converter, characterized in that it comprises a feedback circuit for an analog-to-digital converter according to any one of claims 3-8.

10. An electronic device, characterized in that it comprises an analog-to-digital converter as claimed in claim 9.

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