CN114499477A - GaN driver with dual protection function - Google Patents

Abstract

The invention belongs to the technical field of electronic circuits, and in particular relates to a GaN half-bridge driver with dual protection functions. The driver is based on the negative pressure generated by traditional capacitive coupling, and uses the high-K dielectric power device to switch to the corresponding working mode according to different control signals, making it suitable for driving of various voltage levels. The control signal controls the working mode of the high-K dielectric power device and the charging and discharging of the coupling capacitor, so that the first coupling capacitor can stably generate a negative voltage and effectively prevent the GaN power tube from being turned on by mistake. It overcomes the problem that when negative pressure is generated by traditional capacitive coupling, the capacitive charge is easily disturbed and the negative pressure disappears. And the present invention does not need external negative pressure or internal buck converter integration, on the one hand, it avoids the large power consumption and the stability problem caused by switching interference caused by the traditional external negative pressure, on the other hand, it reduces the structural complexity and saves money. Layout area, reduce cost.

Description

A GaN driver with dual protection

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to a GaN driver with dual protection functions.

Background technique

Gallium nitride (GaN) power transistors have a high mobility electron gas, which can achieve current density and switching speed far exceeding traditional silicon-based devices, and has a wide range of applications. In motor drive, high-side drive, power conversion, electric vehicle drive and other applications involving GaN half-bridge switches, the cooperation of pull-up and pull-down devices is required, but the development of pull-up P-channel GaN transistors lags behind. All-GaN integrated circuits have great difficulties, mainly because the threshold voltage of the GaN half-bridge switch is very low (generally lower than 1.5V, and the minimum value is as low as 0.7V). In the actual circuit, the low threshold voltage of the GaN half-bridge switch itself It will bring serious reliability problems to most applications, such as false opening.

In order to overcome this problem, existing literatures have proposed corresponding driving schemes for different applications, which can be divided into two categories: non-negative voltage gate driving and negative voltage gate driving. Among them, the non-negative voltage gate drive is similar to the traditional CMOS power tube driving method, and its switching is realized by driving the GaN gate voltage above zero volts; the negative voltage gate driving is to use negative voltage to drive the gate of the GaN power tube. , through the drive circuit to generate a negative voltage to reduce the gate voltage of the GaN power transistor to be below the ground level, so as to avoid false opening of the gate of the GaN power transistor.

The traditional negative voltage gate drive circuit realizes the driving of GaN power transistors by external negative voltage, or using an internal buck converter to generate negative voltage, or generating negative voltage based on capacitive coupling. Generating negative pressure through external negative pressure or using an internal buck converter will result in additional power consumption and cost; generating negative pressure through capacitive coupling, when the GaN power transistor is turned on, first charge the capacitor, and when the GaN power transistor needs When it is turned off, one end of the capacitor is grounded, so that the voltage difference on the capacitor directly acts on the gate of the GaN power tube to realize negative pressure driving. This driving method cannot provide a stable negative voltage for the gate of the GaN power tube. When a large disturbance occurs, the charge of the coupling capacitor is easily disturbed and the negative pressure disappears, which increases the gate voltage of the GaN power tube, and the negative pressure generated by the capacitive coupling method will be destroyed, causing the GaN power tube to turn on by mistake.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a GaN driver with dual protection functions, so as to solve the problem of inability to provide stable negative voltage for the gate of the GaN power tube in the traditional way of driving GaN power tubes based on capacitive coupling to generate negative pressure.

To achieve the above object, the following technical solutions adopted in the present invention:

A GaN driver with dual protection functions, comprising a first die and a load, one end of the load is connected to the output end G1 of the first die, and the other end is grounded;

The first die includes a first high-K dielectric power device S1, a first coupling capacitor C1, a first NMOS transistor M1, a power supply Vcc and a second NMOS transistor M2;

The first high-K dielectric power device S1 has a main gate, a slave gate, an anode and a cathode. The main gate is connected to the externally input control signal 1, the slave gate is connected to the externally input control signal 2, and the anode is connected to the first NMOS transistor. The source of M1 and the drain of the second NMOS transistor M2, the cathode is grounded and the source of the second NMOS transistor M2;

One end of the first coupling capacitor C1 is connected to the slave gate of the first high-K dielectric power device S1, and the other end is connected to the source of the first NMOS transistor M1 and the drain of the second NMOS transistor M2;

The gate of the first NMOS transistor M1 is connected to the externally input control signal 3, the drain is connected to the power supply Vcc, and the source is connected to the drain of the second NMOS transistor M2 to form the output end G1 of the first die;

The gate of the second NMOS transistor M2 is connected to the externally input control signal 4, and the source is grounded;

The on-off of the first NMOS transistor M1 and the second NMOS transistor M2 is controlled by the high and low levels of the externally inputted control signal 3 and the control signal 4; The working mode of the high-K dielectric power device S1 is controlled, and the charge and discharge of the first coupling capacitor C1 are controlled to stably generate negative pressure.

Further, the process of stably generating negative pressure of the GaN driver with dual protection functions is:

When the low-level control signal 3 and the low-level control signal 4 are inputted externally, the first NMOS transistor M1 and the second NMOS transistor M2 are turned off; the external input high-level control signal 2 turns off the gate of the high-K dielectric power device S1 Set to high level, when the external input level control signal sets the main gate to low level, the high-K dielectric power device S1 is in the off mode, and the first coupling capacitor C1 is connected to one end of the slave gate to charge positive charges, The other end is charged with negative charge, and when negative pressure needs to be generated, the external input high-level control signal 4 turns on the second NMOS transistor M2, which can pull down G1 to ground potential to prepare for the generation of negative pressure;

When the external input low level control signal 4 turns off the second NMOS transistor M2, the external input low level control signal 2 changes the gate input of the high-K dielectric power device from high level to low level, and the external input high level As soon as the level control signal changes the input of the main gate from low level to high level, the high-K dielectric power device S1 is turned on and works in the state of strong current pull-down capability. Because the first coupling capacitor C1 is connected to the ground from one end of the gate level, the other end of the first coupling capacitor C1 will generate a negative voltage.

Further, the load is a GaN power transistor M3, the gate of which is connected to the output terminal G1 of the first die, the drain is connected to the positive power supply HV, and the source is grounded.

A GaN driver with dual protection functions, comprising a high-side GaN transistor M5, a low-side GaN transistor M6, a first die and a second die;

The gate of the high-side GaN transistor M5 is connected to the output G1 of the first die, the drain is connected to the positive power supply HV, and the source is connected to the floating potential SW; the gate of the low-side GaN transistor M6 is connected to the output G2 of the die 2, and the drain is connected to the floating potential SW. The floating potential SW, the source is connected to the ground;

The first die is composed of a first power supply Vcc1, a first NMOS transistor M1, a second NMOS transistor M2, a first coupling capacitor C1 and a first high-K dielectric power device S1; the first power supply Vcc1 is connected to the drain of the first NMOS transistor M1. The gate of the first NMOS transistor M1 is connected to the external input control signal 7, and the source is connected to the drain of the second NMOS transistor M2 to form the output end G1 of the first die; the gate of the second NMOS transistor M2 is connected to the external Input control signal eight, the source is connected to the cathode of the first high-K dielectric power device S1 and the floating potential SW; one end of the first coupling capacitor C1 is connected to the output end G1 and the anode of the first high-K dielectric power device S1, and the other end is connected to the first high-K dielectric power device S1. A slave gate of the high-K dielectric power device S1; the main gate of the first high-K dielectric power device S1 is connected to the external input control signal VI, and the slave gate is connected to the external input control signal V;

The second die is composed of a second power supply Vcc2, a third NMOS transistor M3, a fourth NMOS transistor M4, a second coupling capacitor C2 and a second high-K dielectric power device S2; the second power supply Vcc2 is connected to the drain of the third NMOS transistor M3 The gate of the third NMOS tube M3 is connected to the external input control signal 9, and the source is connected to the drain of the fourth NMOS tube M4 to form the output end G2 of the second die; the gate of the fourth NMOS tube M4 is connected to the external Input control signal ten, the source is connected to the cathode of the second high-K dielectric power device S2, the source and ground of the low-side GaN transistor M6; one end of the second coupling capacitor C2 is connected to the output end G2 and the second high-K dielectric power device S2 The anode of the second high-K dielectric power device S2 is connected to the other end; the main gate of the second high-K dielectric power device S2 is connected to the external input control signal twelve, and the slave gate is connected to the external input control signal eleven.

The high-K dielectric power device is a power device developed on the basis of the technical accumulation of high-K devices. The device has three operating modes: standard LIGBT, enhanced double conduction and PMOS. For different voltage levels, please refer to the content disclosed in Patent No. ZL201510998522.X.

The invention provides a GaN driver with dual protection functions, which provides the first heavy negative pressure protection on the basis of negative pressure generated by traditional capacitive coupling, and uses high-K dielectric power devices to switch to corresponding working modes according to different control signals. It is suitable for driving of various voltage levels, and the high-K dielectric power device is controlled to work in a state of strong pull-down capability through an externally input control signal, so that the gate voltage of the GaN power tube is lower than 0.7V, providing a second layer of power. Protection, through capacitive coupling and high-K dielectric power devices, to effectively prevent GaN power tubes from being turned on by mistake. In the present invention, one end of the coupling capacitor is connected to the slave gate of the high-K dielectric power device, and the other end is connected to the output end of the die and the anode of the high-K dielectric power device. When a voltage is applied to the coupling capacitor, it is connected to the slave gate. One end of the pole accumulates a positive charge under the action of the electric field force, and the other end accumulates a negative charge. That is to say, under the coupling action of the coupling capacitor, the negative charge accumulated by the coupling capacitor is different from the negative voltage in the traditional sense. When the external input of the high-level control signal 4 enables the second NMOS transistor M2 to be turned on, the output terminal G1 can be pulled down to become the ground potential. There is a transition stage in the entire negative pressure generation process, which effectively reduces the power consumption of the driver. When a large current disturbance occurs, the high-k power device is controlled to enter the enhanced twin conduction mode. At this time, the high-k power device has a strong current pull-down capability, and the high-k power device's strong current pull-down capability is used to discharge the large current of the output terminal G1 in time. , the gate potential is clamped at 0.7V to prevent the GaN tube from being turned on by mistake.

Compared with the prior art, the present invention has the following advantages:

1. The present invention does not require external negative pressure or internal buck converter integration. On the one hand, it avoids the large power consumption caused by traditional external negative pressure and the stability problem caused by switching interference, on the other hand, it reduces the structural complexity. Save layout area and reduce cost.

2. The working mode of the high-K dielectric power device and the charging and discharging of the coupling capacitor are controlled by the external input control signal, which overcomes the problem that the negative pressure is easily disturbed when the negative pressure is generated by the traditional capacitive coupling.

Description of drawings

Fig. 1 is the structural representation of the present invention;

Fig. 2 is the structural representation of embodiment 1;

Fig. 3 is the timing chart of embodiment 1;

Fig. 4 is the structural representation of embodiment 2:

FIG. 5 is a timing chart of Embodiment 2. FIG.

Detailed ways

The GaN half-bridge driver with dual protection functions of the present invention will be described in detail below with reference to the accompanying drawings and embodiments.

Example 1

FIG. 4 provides a first embodiment of the present invention. As shown in FIG. 4 , a GaN driver with dual protection functions includes a first die and a load;

The first die includes a first high-K dielectric power device S1, a power supply Vcc, a first coupling capacitor C1, a first NMOS transistor M1 and a second NMOS transistor M2. The first high-K dielectric power device S1 has a main gate 4, a slave gate 3, an anode 7 and a cathode 8; the main gate 4 of the high-K dielectric power device S1 is connected to the external input control signal-5, and the slave gate 3 is connected to the outside Input control signal 2 6, the anode 7 is connected to the source of the first NMOS transistor M1 and the drain of the second NMOS transistor M2, the first coupling capacitor C1 is connected between the gate and the anode, and the cathode is grounded and connected to the second NMOS transistor M2. source; the gate of the first NMOS transistor M1 is connected to the external input control signal 31, the drain is connected to the power supply Vcc, and the source is connected to the drain of the second NMOS transistor M2 to form the output end G1 of the first die; the second The gate of the NMOS transistor M2 is connected to the external input control signal 42, and the source is grounded.

The load is a GaN power transistor M3, the gate of the GaN power transistor M3 is connected to the output end G1 of the first die, the drain is connected to the positive power supply HV, and the source is grounded.

As shown in FIG. 5, at time t0-t1, the external input control signal 31 is set to a high level to turn on the first NMOS transistor M1, and the external input control signal 42 is set to a low level to turn off the second NMOS transistor M2 ; Set the external input control signal 2 6 to a high level, and the external input control signal 1 5 to a low level, so that the first high-K dielectric power device S1 is completely turned off; at this time, the first coupling capacitor C1 is connected to the gate One end of the pole 3 is charged with positive charge, and the other end is charged with negative charge. Through the pull-up action of the first NMOS transistor M1, the voltage at point G1 is pulled up, and the GaN power transistor M3 is turned on.

When the GaN power transistor M3 needs to be turned off at time t1, the external input signal 31 is set to a low level to turn off the first NMOS transistor M1, and the external input signal 42 is set to a low level to turn off the second NMOS transistor M2; t2 At the moment, the external input signal 15 provides a high level to the main gate 4. At this time, the first high-K dielectric power device S1 works in the typical double conduction mode of the standard traditional LIGBT, and at the same time, the external input signal 42 provides a high level to turn the first high-K dielectric power device S1. The two NMOS transistors M2 are turned on, and the G1 point drops to the ground potential. At time t3, the external input signal 42 is set to a low level to turn off the second NMOS transistor, and the external input signal 26 is set to a low level, because the slave gate 3 of the first high-K dielectric power device S1 is low at this time. If it is flat, the right side of the first coupling capacitor C1 will realize a negative pressure, and the GaN power transistor M3 will be completely turned off. Even if the circuit is disturbed and the potential of G1 rises, since the high-K dielectric power device S1 works in the state of strong current pull-down capability at this time, it can quickly absorb the current at point G1, so that the potential of this point drops, and because of the high-K dielectric power device S1 at this time. There is a voltage difference of 0.7V between the anode 7 and the cathode 8 of the dielectric power device S1, which can ensure that the gate voltage of the GaN power transistor M3 does not exceed 0.7V under the worst condition, providing double protection for negative voltage.

Example 2

FIG. 2 provides a second embodiment of the present invention. As shown in FIG. 2 , a GaN driver with dual protection functions provided by this embodiment includes: a first die, a second die, and a high-side GaN transistor M5 and low-side GaN transistor M6, positive power supply HV. The gate G1 of the high-side GaN transistor M5 is connected to the output of die 1, the drain of M5 is connected to the positive power supply HV, and the source of M5 is connected to the floating potential SW. The gate G2 of the low-side GaN transistor M6 is connected to the output of the die 2, the drain of the M6 is connected to the floating potential SW, and the source of the M6 is connected to the ground.

The die 1 includes: a high-k dielectric power device S1, a first NMOS transistor M1, a second NMOS transistor M2, a first coupling capacitor C1, an external input control signal five 11, an external input control signal six 12, an external input control signal seven 7 , the external input control signal 88, the positive power supply Vcc1. The gate of the first NMOS transistor (M1) is connected to the external input control signal 77, the gate of the second NMOS transistor M2 is connected to the external input control signal 88, and the main gate 10 of the high-K dielectric power device S1 is connected to the external input control signal 612 , the gate 9 is connected to the external input control signal V11, the left side of the first coupling capacitor C1 is connected to the external input control signal V11, and the right side is connected to G1. The drain of the first NMOS transistor M1 is connected to the power supply Vcc1, and the source is connected to G1. The drain of the second NMOS transistor is connected to G1, and the source is connected to the floating potential SW.

The die 2 includes: a high-K dielectric power device S2, a third NMOS transistor M3, a fourth NMOS transistor M4, a second coupling capacitor C2, an external input control signal nine 15, an external input control signal ten 16, and an external input control signal eleven 17, external input control signal twelve 18, positive power supply Vcc2. The gate of the third NMOS transistor M3 is connected to the external input control signal 15, the gate of the fourth NMOS transistor M4 is connected to the external input control signal 16, and the gate of the high-K dielectric power device S2 is connected to the external input control signal 19 from the gate 19. One 17, the main gate 20 is connected to the external input control signal twelve 18, the left side of the second coupling capacitor C2 is connected to the external input control signal eleven 17, and the right side is connected to G2. The drain of the third NMOS transistor M3 is connected to the power supply Vcc2, and the source is connected to G2. The drain of the fourth NMOS transistor is connected to G2 and the source is connected to ground.

As shown in the standard operating timing diagram shown in FIG. 3, when the high-side GaN transistor M5 needs to be turned off, at time t1, the gate level of the first NMOS is pulled down, and M1 is turned off; then at time t2, the internal The gate level of the second NMOS transistor is set to a high level, and M2 is turned on. At the same time, the external input control signal six 12 sets the main gate 10 of the high-k dielectric power device S1 to a high level, while the external input control signal five 11 keeps unchanged from gate 9 high. At this time, the second NMOS transistor M2 pulls down G1 to the level of the floating potential SW point, the gate-source voltage of the high-side GaN transistor M5 is zero, and will be in an off state.

During the switching dead time of t2 and t3, since the main gate 10 and the slave gate 9 of the high-K dielectric power device S1 are at high level at the same time, the high-K dielectric power device S1 will be in the standard LIGBT working mode at this time, Since the second NMOS transistor M2 pulls the voltage of point G1 to the floating potential SW voltage, the voltage between the anode 13 and the cathode 14 of the high-K dielectric power device S1 is lower than 0.7V, so that no current flows in the high-K dielectric power device S1, However, due to the strong current pull-down capability of the LIGBT, if there is a large disturbance at this time, the voltage at point G1 will increase rapidly, and the strong current pull-down capability of the high-K dielectric power device S1 will quickly absorb the disturbance current to ensure that the voltage at point G1 does not increase. If it exceeds 0.7V, the false turn-on of the high-side GaN transistor M5 is avoided. At this time, since the secondary gate 9 of the high-K dielectric power device S1 is high and G1 is low, the first coupling capacitor C1 will charge positive charges on the left plate and negative charges on the right plate.

When the dead time from t2 to t3 ends, the low-side GaN transistor M6 needs to be turned on. Before t3, the high-K dielectric power device S2 works in a state of strong current pull-down capability, and G2 is a negative voltage. At time t3, the external input control signal eleven 17 sets the slave gate 19 of the high-k dielectric power device S2 to a high level, and the external input control signal twelve 18 sets the main gate 20 to a low level to completely turn off the high-k Dielectric power device S2. When the low-side GaN transistor M6 is turned off, the second coupling capacitor C2 has leakage, so that the voltage difference on C2 is reduced, so when the high-K dielectric power device S2 rises from the voltage on the gate 19 to the high-level voltage, G2 A positive voltage will be created, thereby opening the low-side GaN tube M6. Since the voltage of the high-K dielectric power device S2 rising rapidly from the gate 19 is coupled to the point G2 through the second coupling capacitor C2, the delay is small, and the low-side GaN transistor M6 will be turned on extremely quickly. At the same time, the external input control signal 88 becomes a low level, and M2 in the die 1 is turned off. When the external input control signal 511 sets the slave gate 9 of the high-K dielectric power device S1 from high to low, there is a left-to-right voltage on the first coupling capacitor C1, and the right side G1 of the first coupling capacitor C1 will realize a negative pressure to completely turn off the high-side GaN tube M5.

Since the high-K dielectric power device S2 has been turned off at time t3. At time t4, the external input control signal 915 becomes high, turning on the third NMOS transistor M3 without generating short-circuit current. When M3 is turned on, it will provide a stable active positive voltage for G2, thereby maintaining the low-side GaN transistor. Turn on the M6. When it is necessary to turn off the low-side GaN transistor M6 and turn on the high-side GaN transistor M5, at time t5, the external input control signal 915 first sets the gate of the third NMOS transistor in the die 2 to a low level to turn off M3 to avoid short circuit . Then at time t6, the external input control signal 1218 sets the main gate 20 of the high-K dielectric power device S2 in the die 2 to a high level, and the external input control signal 1216 sets the gate of the fourth NMOS transistor M4 to a high level. Set to high level, and M4 pulls point G2 to ground level, similar to the high-K dielectric power device S1 in die 1 at t2. At this time, the high-K dielectric power device S2 will enter the standard LIGBT working mode and can be discharged Large current disturbance at point G2. At the same time, the secondary gate 19 of the high-K dielectric power device S2 is high and the G2 point is low, and the second coupling capacitor C2 will be positively charged on the left plate and negatively charged on the right plate. At time t7, the main gate 10 and the slave gate 9 of the high-K dielectric power device S1 are set to a low level and a high level, respectively, to completely turn off the new high-K dielectric multifunctional device S1, and the rise of the slave gate 9 is used. The voltage, through the capacitive coupling of the first coupling capacitor C1, quickly turns on the high-side GaN transistor M5. At the same time, the external input control signal 16 changes to a low level, and the fourth NMOS transistor M4 in the die 2 is turned off. The external input control signal eleven 17 sets the slave gate 19 of the high-K dielectric power device S2 from high to low. Since there is a left-to-right voltage on the second coupling capacitor C2, when the gate 19 is at the ground level, the point G2 will achieve a negative voltage.

At time t8, the external input control signal 77 sets the gate of the first NMOS transistor in the die 1 to a high level, turns on the first NMOS transistor M1, keeps the voltage at point G1 high, and makes the high-side GaN transistor M5 continue turn on, enabling high-side switching operation.

It can be seen from this that the present invention can also realize negative pressure driving without integrating an external negative pressure and an internal buck converter. Compared with the traditional method of generating negative voltage to drive GaN power transistors by capacitive coupling, this embodiment provides a new idea. In this embodiment, the high-K dielectric power device and the coupling capacitor are controlled to generate a negative pressure, so as to realize the driving of the GaN power transistor, which overcomes the capacitive charge existing in the traditional capacitively coupled negative pressure drive and is easily disturbed to cause the negative pressure to disappear, or the negative pressure in the circuit disappears. When the disturbance is too large, it may lead to a positive voltage on the GaN gate, causing the GaN gate that should be turned off to continue to be turned on. In this embodiment, the working mode of the high-K dielectric power device is switched, and the coupling capacitor is controlled to generate a negative voltage, so that the high-K dielectric power device is in a state of strong current pull-down capability, which can fully absorb the peak current caused by large disturbances and ensure that The worst-case GaN gate voltage does not exceed 0.7V, thus providing high reliability double protection for GaN.

Claims (4)

1. A GaN driver with double protection function comprises a first die and a load, one end of the load is connected with an output end G1 of the first die, and the other end of the load is grounded, and the GaN driver is characterized in that:

the first die comprises a first high-K dielectric power device S1, a first coupling capacitor C1, a first NMOS transistor M1, a power supply Vcc and a second NMOS transistor M2;

the first high-K dielectric power device S1 comprises a main grid, a secondary grid, an anode and a cathode, wherein the main grid is connected with a first control signal input from the outside, the secondary grid is connected with a second control signal input from the outside, the anode is connected with the source electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2, and the cathode is connected with the ground and the source electrode of the second NMOS tube M2;

one end of the first coupling capacitor C1 is connected with the slave gate of the first high-K dielectric power device S1, and the other end is connected with the source electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2;

the grid electrode of the first NMOS tube M1 is connected with a control signal III input from the outside, the drain electrode is connected with a power supply Vcc, and the source electrode is connected with the drain electrode of the second NMOS tube M2 to form an output end G1 of the first tube core;

the grid electrode of the second NMOS tube M2 is connected with a control signal IV input from the outside, and the source electrode is grounded;

the on/off of the first NMOS transistor M1 and the second NMOS transistor M2 is controlled by the high and low levels of the externally input control signal three and the control signal four; the working mode of the high-K dielectric power device S1 is controlled by the high and low levels of the control signal I and the control signal II which are input externally, so that the charging and discharging of the first coupling capacitor C1 are controlled, and negative voltage is generated stably.

2. The GaN driver with dual protection as claimed in claim 1, wherein: the process of stably generating negative pressure of the GaN driver with the double protection function comprises the following steps:

when the low level control signal three and the low level control signal four are input externally, the first NMOS transistor M1 and the second NMOS transistor M2 are turned off; when a high-level control signal II is input from the outside, a slave grid of the high-K dielectric power device S1 is set to be high level, when a main grid of the level control signal I input from the outside is set to be low level, the high-K dielectric power device S1 is in a turn-off mode, one end of a first coupling capacitor C1 connected with the slave grid is charged with positive charges, the other end of the first coupling capacitor C1 is charged with negative charges, when negative pressure needs to be generated, a high-level control signal IV is input from the outside to enable a second NMOS tube M2 to be turned on, namely G1 can be pulled down to be ground potential, and preparation is made for generating the negative pressure;

when the external input low level control signal four turns off the second NMOS transistor M2, the external input low level control signal two turns the slave gate input of the high-K dielectric power device from high level to low level, the external input high level control signal one turns the master gate input from low level to high level, the high-K dielectric power device S1 is turned on, and operates in a strong current pull-down capability state, and since one end of the first coupling capacitor C1, which is connected with the slave gate, is at ground level, the other end of the first coupling capacitor C1 generates a negative voltage.

3. A GaN driver with dual protection function as claimed in claim 1 or 2, wherein: the load is a GaN power tube M3, the gate of which is connected to the output end G1 of the first die, the drain of which is connected to the positive power supply HV, and the source of which is grounded.

4. A GaN driver with dual protection function, comprising a high-side GaN tube M5, a low-side GaN tube M6, a first die, and a second die, characterized in that:

the gate of the high-side GaN tube M5 is connected with the output G1 of the first tube core, the drain is connected with a positive power supply HV, and the source is connected with a floating potential SW; the grid electrode of the low-side GaN tube M6 is connected with the output G2 of the tube core 2, the drain electrode is connected with the floating potential SW, and the source electrode is connected with the ground;

the first die is composed of a first power supply Vcc1, a first NMOS tube M1, a second NMOS tube M2, a first coupling capacitor C1 and a first high-K medium power device S1; the first power supply Vcc1 is connected to the drain of the first NMOS transistor M1; the grid electrode of the first NMOS tube M1 is connected with an external input control signal seven, and the source electrode of the first NMOS tube M2 is connected with the drain electrode of the second NMOS tube M to form an output end G1 of the first tube core; the grid electrode of the second NMOS tube M2 is connected with an external input control signal eight, and the source electrode is connected with the cathode of the first high-K dielectric power device S1 and the floating potential SW; one end of the first coupling capacitor C1 is connected with the output end G1 and the anode of the first high-K dielectric power device S1, and the other end is connected with the slave gate of the first high-K dielectric power device S1; the main grid of the first high-K dielectric power device S1 is connected with an external input control signal six, and the auxiliary grid is connected with an external input control signal five;

the second die is composed of a second power supply Vcc2, a third NMOS transistor M3, a fourth NMOS transistor M4, a second coupling capacitor C2 and a second high-K dielectric power device S2; the second power supply Vcc2 is connected to the drain of the third NMOS transistor M3; the grid electrode of the third NMOS tube M3 is connected with an external input control signal nine, and the source electrode of the third NMOS tube M3578 is connected with the drain electrode of the fourth NMOS tube M4 to form an output end G2 of the second tube core; the grid electrode of the fourth NMOS tube M4 is connected with an external input control signal ten, and the source electrode is connected with the cathode electrode of the second high-K dielectric power device S2, the source electrode of the low-side GaN tube M6 and the ground; one end of the second coupling capacitor C2 is connected with the output end G2 and the anode of the second high-K dielectric power device S2, and the other end is connected with the slave gate of the second high-K dielectric power device S2; the main gate of the second high-K dielectric power device S2 is connected to the external input control signal twelve, and the slave gate is connected to the external input control signal eleven.

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