CN114499477A - GaN driver with dual protection function - Google Patents
GaN driver with dual protection function Download PDFInfo
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- CN114499477A CN114499477A CN202210048233.3A CN202210048233A CN114499477A CN 114499477 A CN114499477 A CN 114499477A CN 202210048233 A CN202210048233 A CN 202210048233A CN 114499477 A CN114499477 A CN 114499477A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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Abstract
The invention belongs to the technical field of electronic circuits, and particularly relates to a GaN half-bridge driver with a dual protection function. The driver is characterized in that a high-K dielectric power device can be switched to a corresponding working mode according to different control signals on the basis that negative pressure is generated by traditional capacitive coupling, and the driver is suitable for driving of various voltage levels. The problem that negative voltage disappears due to the fact that capacitance charges are easily disturbed when negative voltage is generated by traditional capacitance coupling is solved. In addition, external negative pressure or internal buck converter integration is not needed, so that the problems of high power consumption and stability caused by switching interference caused by the traditional external negative pressure are solved, the structural complexity is reduced, the layout area is saved, and the cost is reduced.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to a GaN driver with a dual-protection function.
Background
The gallium nitride (GaN) power tube has high mobility of electron gas, can realize current density and switching speed far exceeding those of traditional silicon-based devices, and has wide applicability. In the applications of motor drive, high-side drive, power conversion, electric vehicle drive and the like relating to GaN half-bridge switches, the matching of pull-up and pull-down devices is needed, but the development of pull-up P-channel GaN transistors is relatively lagged, so that a full GaN integrated circuit is difficult to realize, which is mainly reflected in that the threshold voltage of the GaN half-bridge switches is very low (generally lower than 1.5V, and the minimum value is as low as 0.7V), and the low threshold voltage of the GaN half-bridge switches in practical circuits can bring serious reliability problems to most applications, such as mistaken opening and the like.
To overcome this problem, the prior art proposes corresponding driving schemes for different applications, which can be classified into non-negative voltage gate driving and negative voltage gate driving. The non-negative voltage grid electrode driving is similar to the driving mode of a traditional CMOS power tube, and the GaN is driven by grid electrode voltage of more than zero volt to realize the switching of the GaN; the negative voltage grid drive is to drive the grid of the GaN power tube by using negative voltage, and the grid voltage for closing the GaN power tube is reduced to be lower than the ground level by generating the negative voltage through the drive circuit, so that the grid of the GaN power tube is prevented from being opened by mistake.
The traditional negative-voltage grid driving circuit realizes the driving of the GaN power tube by externally connecting negative voltage, or generating the negative voltage by using an internal buck converter, or generating the negative voltage based on capacitive coupling. Generating negative pressure by external negative pressure or using an internal buck converter results in additional power consumption and cost; the negative pressure is generated in a capacitive coupling mode, when a GaN power tube is conducted, the capacitor is charged firstly, when the GaN power tube needs to be turned off, one end of the capacitor is grounded, the voltage difference on the capacitor directly acts on a grid electrode of the GaN power tube, negative pressure driving is achieved, the driving mode cannot provide stable negative pressure for the grid electrode of the GaN power tube, large disturbance occurs in a circuit, the charge of the coupling capacitor is disturbed easily, negative pressure disappears, the grid voltage of the GaN power tube is increased, the negative pressure generated in the capacitive coupling mode is destroyed, and the GaN power tube is opened mistakenly.
Disclosure of Invention
The invention aims to provide a GaN driver with a double protection function, and aims to solve the problem that stable negative voltage cannot be provided for a GaN power tube grid electrode in the traditional GaN power tube driving mode based on negative voltage generated by capacitive coupling.
In order to achieve the purpose, the invention adopts the following technical scheme:
a GaN driver with double protection function comprises a first die and a load, wherein one end of the load is connected with an output end G1 of the first die, and the other end of the load is grounded;
the first die comprises a first high-K dielectric power device S1, a first coupling capacitor C1, a first NMOS transistor M1, a power supply Vcc and a second NMOS transistor M2;
the first high-K dielectric power device S1 comprises a main grid, a secondary grid, an anode and a cathode, wherein the main grid is connected with a first control signal input from the outside, the secondary grid is connected with a second control signal input from the outside, the anode is connected with the source electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2, and the cathode is connected with the ground and the source electrode of the second NMOS tube M2;
one end of the first coupling capacitor C1 is connected with the slave gate of the first high-K dielectric power device S1, and the other end is connected with the source electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2;
the grid electrode of the first NMOS tube M1 is connected with a control signal III input from the outside, the drain electrode is connected with a power supply Vcc, and the source electrode is connected with the drain electrode of the second NMOS tube M2 to form an output end G1 of the first tube core;
the grid electrode of the second NMOS tube M2 is connected with a control signal IV input from the outside, and the source electrode is grounded;
the on/off of the first NMOS transistor M1 and the second NMOS transistor M2 is controlled by the high and low levels of the externally input control signal three and the control signal four; the working mode of the high-K dielectric power device S1 is controlled by the high and low levels of the control signal I and the control signal II which are input externally, so that the charging and discharging of the first coupling capacitor C1 are controlled, and negative voltage is generated stably.
Further, the process of stably generating the negative pressure of the GaN driver with the dual protection function is as follows:
when the low level control signal three and the low level control signal four are input externally, the first NMOS transistor M1 and the second NMOS transistor M2 are turned off; when the external input high-level control signal II sets the slave grid of the high-K dielectric power device S1 to be high level, and when the external input level control signal I sets the master grid to be low level, the high-K dielectric power device S1 is in a turn-off mode, one end of the first coupling capacitor C1, which is connected with the slave grid, is positively charged, and the other end of the first coupling capacitor C1 is negatively charged, and when negative voltage needs to be generated, the external input high-level control signal IV enables the second NMOS tube M2 to be turned on, namely G1 is pulled down to be ground potential, so that preparation is made for generating the negative voltage;
when the external input low level control signal four turns off the second NMOS transistor M2, the external input low level control signal two turns the slave gate input of the high-K dielectric power device from high level to low level, the external input high level control signal one turns the master gate input from low level to high level, the high-K dielectric power device S1 is turned on, and operates in a strong current pull-down capability state, and since one end of the first coupling capacitor C1, which is connected with the slave gate, is at ground level, the other end of the first coupling capacitor C1 generates a negative voltage.
Further, the load is a GaN power transistor M3, the gate of which is connected to the output terminal G1 of the first die, the drain of which is connected to the positive power source HV, and the source of which is grounded.
A GaN driver with double protection function comprises a high-side GaN tube M5, a low-side GaN tube M6, a first die and a second die;
the gate of the high-side GaN tube M5 is connected with the output G1 of the first tube core, the drain is connected with the positive power supply HV, and the source is connected with the floating potential SW; the grid electrode of the low-side GaN tube M6 is connected with the output G2 of the tube core 2, the drain electrode is connected with the floating potential SW, and the source electrode is connected with the ground;
the first die is composed of a first power supply Vcc1, a first NMOS transistor M1, a second NMOS transistor M2, a first coupling capacitor C1 and a first high-K dielectric power device S1; the first power supply Vcc1 is connected to the drain of the first NMOS transistor M1; the grid electrode of the first NMOS tube M1 is connected with an external input control signal seven, and the source electrode of the first NMOS tube M2 is connected with the drain electrode of the second NMOS tube M to form an output end G1 of the first tube core; the grid electrode of the second NMOS tube M2 is connected with an external input control signal eight, and the source electrode is connected with the cathode of the first high-K dielectric power device S1 and the floating potential SW; one end of the first coupling capacitor C1 is connected with the output end G1 and the anode of the first high-K dielectric power device S1, and the other end is connected with the slave gate of the first high-K dielectric power device S1; the main grid of the first high-K dielectric power device S1 is connected with an external input control signal six, and the auxiliary grid is connected with an external input control signal five;
the second die is composed of a second power supply Vcc2, a third NMOS tube M3, a fourth NMOS tube M4, a second coupling capacitor C2 and a second high-K dielectric power device S2; the second power supply Vcc2 is connected to the drain of the third NMOS transistor M3; the grid electrode of the third NMOS tube M3 is connected with an external input control signal nine, and the source electrode of the third NMOS tube M3578 is connected with the drain electrode of the fourth NMOS tube M4 to form an output end G2 of the second tube core; the grid electrode of the fourth NMOS tube M4 is connected with an external input control signal ten, and the source electrode is connected with the cathode electrode of the second high-K dielectric power device S2, the source electrode of the low-side GaN tube M6 and the ground; one end of the second coupling capacitor C2 is connected with the output end G2 and the anode of the second high-K dielectric power device S2, and the other end is connected with the slave gate of the second high-K dielectric power device S2; the main gate of the second high-K dielectric power device S2 is connected to the external input control signal twelve, and the slave gate is connected to the external input control signal eleven.
The high-K dielectric power device is a power device developed on the basis of technology accumulation of the high-K device, and the device has three operation modes of standard LIGBT, enhanced gemini conduction and PMOS, and can be applied to different voltage levels by switching the three operation modes, and specifically, the content disclosed in patent No. zl201510998522.x can be referred to.
The GaN driver with the double protection functions provided by the invention has the characteristics that the first heavy voltage protection is provided on the basis of the negative voltage generated by the traditional capacitive coupling, the high-K dielectric power device is switched to the corresponding working mode according to different control signals, so that the GaN driver is suitable for driving of various voltage grades, the high-K dielectric power device is controlled to work in a strong pull-down capacity state through an externally input control signal, the grid voltage of a GaN power tube is lower than 0.7V, the second heavy protection is provided, and the GaN power tube is effectively prevented from being opened by mistake through the combined action of the capacitive coupling and the high-K dielectric power device. In the invention, one end of the coupling capacitor is connected with the slave grid of the high-K dielectric power device, the other end of the coupling capacitor is connected with the output end of the connecting tube core and the anode of the high-K dielectric power device, and after a voltage is applied to the coupling capacitor, one end of the coupling capacitor connected with the slave grid accumulates positive charges under the action of an electric field force, and the other end accumulates negative charges. That is, under the coupling action of the coupling capacitor, the negative charge accumulated by the coupling capacitor is substantially a positive voltage, unlike the negative voltage in the conventional sense, except that the voltage value is lower than the voltage value generated by the positive charge connected to the gate terminal. When the externally input high-level control signal four turns on the second NMOS transistor M2, the output terminal G1 is pulled down to ground. A transition stage exists in the whole negative pressure generation process, and the power consumption of the driver is effectively reduced. When large current disturbance occurs, the high-K power device is controlled to enter an enhanced double-electron conduction working mode, the high-K power device has strong current pull-down capability, the strong current pull-down capability of the high-K power device is utilized to timely release large current of an output end G1, the grid potential is clamped at 0.7V, and the GaN tube is prevented from being mistakenly opened.
Compared with the prior art, the invention has the following advantages:
1. the invention does not need external negative pressure or internal buck converter integration, on one hand, the problems of high power consumption and stability caused by switch interference caused by the traditional external negative pressure are avoided, and on the other hand, the structural complexity is reduced, the layout area is saved, and the cost is reduced.
2. The working mode of the high-K dielectric power device and the charging and discharging of the coupling capacitor are controlled through the control signal input from the outside, and the problem that negative voltage disappears due to the fact that capacitor charges are easily disturbed when negative voltage is generated by traditional capacitor coupling is solved.
Drawings
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a schematic structural view of example 1;
FIG. 3 is a timing chart of embodiment 1;
fig. 4 is a schematic structural diagram of embodiment 2:
FIG. 5 is a timing chart of embodiment 2.
Detailed Description
The GaN half-bridge driver with dual protection function according to the present invention will be described in detail with reference to the accompanying drawings and embodiments.
Example 1
FIG. 4 provides a first embodiment of the present invention, and as shown in FIG. 4, a GaN driver with dual protection function includes a first die and a load;
the first die comprises a first high-K dielectric power device S1, a power supply Vcc, a first coupling capacitor C1, a first NMOS transistor M1 and a second NMOS transistor M2. The first high-K dielectric power device S1 has a master gate 4, a slave gate 3, an anode 7 and a cathode 8; the main grid 4 of the high-K dielectric power device S1 is connected with a first external input control signal 5, the auxiliary grid 3 is connected with a second external input control signal 6, the anode 7 is connected with the source electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2, a first coupling capacitor C1 is connected between the auxiliary grid and the anode, and the cathode is grounded and the source electrode of the second NMOS tube M2; the grid electrode of the first NMOS tube M1 is connected with an external input control signal three 1, the drain electrode is connected with a power supply Vcc, and the source electrode is connected with the drain electrode of the second NMOS tube M2 to form an output end G1 of the first tube core; the gate of the second NMOS transistor M2 is connected to the external input control signal four 2, and the source is grounded.
The load is a GaN power tube M3, the grid electrode of the GaN power tube M3 is connected with the output end G1 of the first tube core, the drain electrode is connected with a positive power supply HV, and the source electrode is grounded.
As shown in fig. 5, at time t0-t1, setting the external input control signal three 1 to high level turns on the first NMOS transistor M1, and setting the external input control signal four 2 to low level turns off the second NMOS transistor M2; setting the external input control signal II 6 to be at a high level and setting the external input control signal I5 to be at a low level, so that the first high-K medium power device S1 is completely turned off; at this time, the first coupling capacitor C1 is connected to be positively charged from one end of the gate 3 and negatively charged from the other end, and the voltage at the point G1 is pulled up by the pull-up action of the first NMOS transistor M1, so that the GaN power transistor M3 is turned on.
When the GaN power tube M3 needs to be turned off at the time of t1, the external input signal three 1 is set to be low level to turn off the first NMOS tube M1, and the external input signal four 2 is set to be low level to turn off the second NMOS tube M2; at time t2, the external input signal one 5 provides a high level to the main gate 4, and the first high-K dielectric power device S1 operates in the typical two-sub conduction mode of the standard conventional LIGBT, while the external input signal four 2 provides a high level to turn on the second NMOS transistor M2, and the point G1 drops to the ground potential. At time t3, the external input signal four 2 is set to low level to turn off the second NMOS transistor, and the external input signal two 6 is set to low level, because the slave gate 3 of the first high-K dielectric power device S1 is at low level at this time, the negative voltage is realized on the right side of the first coupling capacitor C1, and the GaN power transistor M3 is completely turned off. Even if the circuit is disturbed to cause the potential of G1 to rise, because the high-K dielectric power device S1 works in a strong current pull-down capacity state at the moment, the current at the point G1 can be absorbed quickly, the potential at the point is lowered, and because the voltage difference of 0.7V exists between the anode 7 and the cathode 8 of the high-K dielectric power device S1 at the moment, the grid voltage of the GaN power tube M3 can be ensured not to exceed 0.7V under the worst condition, and double protection is provided for negative voltage.
Example 2
Fig. 2 provides a second embodiment of the present invention, and as shown in fig. 2, this embodiment provides a GaN driver with dual protection function, which includes: a first die, a second die, a high side GaN tube M5 and a low side GaN tube M6, a positive power supply HV. The high side GaN tube M5 has gate G1 connected to the output of die 1, M5 drain connected to the positive power supply HV, and M5 source connected to the floating potential SW. The low side GaN tube M6 has gate G2 connected to the die 2 output, M6 drain connected to the floating potential SW, and M6 source connected to ground.
The die 1 comprises: the high-K dielectric power device comprises a high-K dielectric power device S1, a first NMOS transistor M1, a second NMOS transistor M2, a first coupling capacitor C1, an external input control signal five 11, an external input control signal six 12, an external input control signal seven 7, an external input control signal eight 8 and a positive power supply Vcc 1. The grid of the first NMOS tube (M1) is connected with an external input control signal seven 7, the grid of the second NMOS tube M2 is connected with an external input control signal eight 8, the main grid 10 of the high-K dielectric power device S1 is connected with an external input control signal six 12, the auxiliary grid 9 is connected with an external input control signal five 11, the left side of the first coupling capacitor C1 is connected with an external input control signal five 11, and the right side of the first coupling capacitor C1 is connected with G1. The drain of the first NMOS transistor M1 is connected to a power supply Vcc1 and the source is connected to G1. The drain of the second NMOS transistor is connected to G1, and the source is connected to the floating potential SW.
The die 2 includes: the high-K dielectric power device S2, a third NMOS transistor M3, a fourth NMOS transistor M4, a second coupling capacitor C2, an external input control signal nine 15, an external input control signal ten 16, an external input control signal eleven 17, an external input control signal twelve 18 and a positive power supply Vcc 2. The gate of the third NMOS transistor M3 is connected to the ninth 15 external input control signal, the gate of the fourth NMOS transistor M4 is connected to the tenth 16 external input control signal, the slave gate 19 of the high-K dielectric power device S2 is connected to the eleventh 17 external input control signal, the master gate 20 is connected to the twelfth 18 external input control signal, the left side of the second coupling capacitor C2 is connected to the eleventh 17 external input control signal, and the right side is connected to the G2. The drain of the third NMOS transistor M3 is connected to a power supply Vcc2 and the source is connected to G2. The drain of the fourth NMOS transistor is connected to G2, and the source is connected to ground.
As shown in the standard operation timing diagram of fig. 3, when the high-side GaN transistor M5 needs to be turned off, at time t1, the first NMOS gate is pulled low, and M1 is turned off; then at time t2, the gate level of the second NMOS transistor inside die 1 is set to high level, M2 is turned on, and the external input control signal six 12 sets the master gate 10 of the high-K dielectric power device S1 to high level, while the external input control signal five 11 keeps the slave gate 9 at high level. At this time, the second NMOS transistor M2 pulls down G1 to the level of the floating potential SW point, and the gate-source voltage of the high-side GaN transistor M5 is zero, and will be in the off state.
In the dead time of the switch at t2 and t3, because the master gate 10 and the slave gate 9 of the high-K dielectric power device S1 are at high levels at the same time, the high-K dielectric power device S1 at this time will be in the standard LIGBT operating mode, and because the second NMOS transistor M2 pulls the voltage at point G1 to the floating potential SW voltage, the voltage between the anode 13 and the cathode 14 of the high-K dielectric power device S1 is lower than 0.7V, so that no current flows through the high-K dielectric power device S1, but because of the strong current pull-down capability of the LIGBT, if a large disturbance occurs at this time, the voltage at point G1 is rapidly increased, and the strong current pull-down capability of the high-K dielectric power device S1 will rapidly absorb the disturbance current, so as to ensure that the voltage at point G1 does not exceed 0.7V, and prevent the high-side GaN transistor M5 from being turned on by mistake. At this time, since the slave gate 9 of the high-K dielectric power device S1 is high and G1 is low, the first coupling capacitor C1 will be positively charged at the left plate and negatively charged at the right plate.
When the dead time from t2 to t3 ends, the low side GaN tube M6 needs to be opened. Before t3, high-K dielectric power device S2 was operated at high current pull-down capability with G2 at negative voltage. At time t3, the external input control signal eleven 17 asserts the high-K dielectric power device S2 high from the gate 19 and the external input control signal twelve 18 asserts the main gate 20 low to completely turn off the high-K dielectric power device S2. Since there is leakage in the second coupling capacitor C2 during the off time of the low side GaN tube M6, so that the voltage difference across C2 is reduced, when the high K dielectric power device S2 rises from the voltage on the gate 19 to a high level voltage, G2 will generate a positive voltage, thereby turning on the low side GaN tube M6. Since the voltage of the high-K dielectric power device S2 rising rapidly from the gate 19 is coupled to the point G2 through the second coupling capacitor C2, the delay is small, and the low-side GaN tube M6 turns on very rapidly. At the same time, the externally input control signal eight 8 goes low, turning off M2 in die 1. When the external input control signal five 11 turns the slave gate 9 of the high-K dielectric power device S1 from high to low, a voltage from left to right exists on the first coupling capacitor C1, and the right G1 of the first coupling capacitor C1 realizes a negative voltage, so that the high-side GaN tube M5 is completely turned off.
The device S2 has been turned off at time t3 due to the high-K dielectric. At time t4, the external input control signal nine 15 goes high, turning on the third NMOS transistor M3 without generating short-circuit current, and after M3 turns on, it will provide a stable active positive voltage for G2, thereby keeping the low-side GaN transistor M6 on. When the low-side GaN transistor M6 needs to be turned off and the high-side GaN transistor M5 needs to be turned on, at time t5, the external input control signal nine 15 first sets the gate of the third NMOS transistor in the die 2 to low level to turn off M3 and avoid short circuit. Then at time t6, the external input control signal twelve 18 sets the main gate 20 of the high-K dielectric power device S2 in the die 2 to high level, the external input control signal ten 16 sets the gate of the fourth NMOS transistor M4 to high level, and at the same time, M4 pulls the G2 point to ground level, similarly to the high-K dielectric power device S1 in the die 1 at time t2, at this time, the high-K dielectric power device S2 will enter the standard LIGBT operating mode, and may discharge the large current disturbance at the G2 point. While the slave gate 19 of the high-K dielectric power device S2 is high and the G2 is low, the second coupling capacitor C2 will charge positively on the left plate and negatively on the right plate. At time t7, the main gate 10 and the slave gate 9 of the high-K dielectric power device S1 are set to low level and high level, respectively, to completely turn off the novel high-K dielectric multifunctional device S1, and the high-side GaN tube M5 is quickly turned on through the capacitive coupling of the first coupling capacitor C1 by the rising voltage of the slave gate 9. At the same time, the external input control signal ten 16 goes low, turning off the fourth NMOS transistor M4 in the die 2. The external input control signal eleven 17 turns the slave gate 19 of the high-K dielectric power device S2 high. Since there is a left-to-right voltage on the second coupling capacitor C2, the G2 point will achieve a negative voltage when the slave gate 19 is at ground.
At time t8, the external input control signal 7 seven sets the gate of the first NMOS transistor in the die 1 to high, turns on the first NMOS transistor M1, keeps the voltage at the point G1 high, and keeps the high-side GaN transistor M5 turned on continuously, thereby implementing the high-side switching operation.
Therefore, the invention can realize negative pressure drive without integrating external negative pressure and an internal buck converter. Compared with the conventional method of driving the GaN power tube by generating negative voltage through capacitive coupling, the present embodiment provides a new concept. According to the embodiment, the GaN power tube is driven by controlling the high-K dielectric power device and the coupling capacitor to generate negative pressure, and the problem that capacitive charge existing in the traditional capacitive coupling negative pressure driving is easy to disturb to cause the negative pressure to disappear, or positive pressure of a GaN grid possibly occurs when disturbance in a circuit is too large, so that the GaN grid which should be closed is continuously conducted is solved. In this embodiment, the operating mode of the high-K dielectric power device is switched, and the coupling capacitor is controlled to generate a negative voltage, so that the high-K dielectric power device can fully absorb a peak current caused by large disturbance when being in a high-current pull-down capability state, and a GaN gate voltage is ensured not to exceed 0.7V in the worst case, thereby providing high-reliability dual protection for GaN.
Claims (4)
1. A GaN driver with double protection function comprises a first die and a load, one end of the load is connected with an output end G1 of the first die, and the other end of the load is grounded, and the GaN driver is characterized in that:
the first die comprises a first high-K dielectric power device S1, a first coupling capacitor C1, a first NMOS transistor M1, a power supply Vcc and a second NMOS transistor M2;
the first high-K dielectric power device S1 comprises a main grid, a secondary grid, an anode and a cathode, wherein the main grid is connected with a first control signal input from the outside, the secondary grid is connected with a second control signal input from the outside, the anode is connected with the source electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2, and the cathode is connected with the ground and the source electrode of the second NMOS tube M2;
one end of the first coupling capacitor C1 is connected with the slave gate of the first high-K dielectric power device S1, and the other end is connected with the source electrode of the first NMOS tube M1 and the drain electrode of the second NMOS tube M2;
the grid electrode of the first NMOS tube M1 is connected with a control signal III input from the outside, the drain electrode is connected with a power supply Vcc, and the source electrode is connected with the drain electrode of the second NMOS tube M2 to form an output end G1 of the first tube core;
the grid electrode of the second NMOS tube M2 is connected with a control signal IV input from the outside, and the source electrode is grounded;
the on/off of the first NMOS transistor M1 and the second NMOS transistor M2 is controlled by the high and low levels of the externally input control signal three and the control signal four; the working mode of the high-K dielectric power device S1 is controlled by the high and low levels of the control signal I and the control signal II which are input externally, so that the charging and discharging of the first coupling capacitor C1 are controlled, and negative voltage is generated stably.
2. The GaN driver with dual protection as claimed in claim 1, wherein: the process of stably generating negative pressure of the GaN driver with the double protection function comprises the following steps:
when the low level control signal three and the low level control signal four are input externally, the first NMOS transistor M1 and the second NMOS transistor M2 are turned off; when a high-level control signal II is input from the outside, a slave grid of the high-K dielectric power device S1 is set to be high level, when a main grid of the level control signal I input from the outside is set to be low level, the high-K dielectric power device S1 is in a turn-off mode, one end of a first coupling capacitor C1 connected with the slave grid is charged with positive charges, the other end of the first coupling capacitor C1 is charged with negative charges, when negative pressure needs to be generated, a high-level control signal IV is input from the outside to enable a second NMOS tube M2 to be turned on, namely G1 can be pulled down to be ground potential, and preparation is made for generating the negative pressure;
when the external input low level control signal four turns off the second NMOS transistor M2, the external input low level control signal two turns the slave gate input of the high-K dielectric power device from high level to low level, the external input high level control signal one turns the master gate input from low level to high level, the high-K dielectric power device S1 is turned on, and operates in a strong current pull-down capability state, and since one end of the first coupling capacitor C1, which is connected with the slave gate, is at ground level, the other end of the first coupling capacitor C1 generates a negative voltage.
3. A GaN driver with dual protection function as claimed in claim 1 or 2, wherein: the load is a GaN power tube M3, the gate of which is connected to the output end G1 of the first die, the drain of which is connected to the positive power supply HV, and the source of which is grounded.
4. A GaN driver with dual protection function, comprising a high-side GaN tube M5, a low-side GaN tube M6, a first die, and a second die, characterized in that:
the gate of the high-side GaN tube M5 is connected with the output G1 of the first tube core, the drain is connected with a positive power supply HV, and the source is connected with a floating potential SW; the grid electrode of the low-side GaN tube M6 is connected with the output G2 of the tube core 2, the drain electrode is connected with the floating potential SW, and the source electrode is connected with the ground;
the first die is composed of a first power supply Vcc1, a first NMOS tube M1, a second NMOS tube M2, a first coupling capacitor C1 and a first high-K medium power device S1; the first power supply Vcc1 is connected to the drain of the first NMOS transistor M1; the grid electrode of the first NMOS tube M1 is connected with an external input control signal seven, and the source electrode of the first NMOS tube M2 is connected with the drain electrode of the second NMOS tube M to form an output end G1 of the first tube core; the grid electrode of the second NMOS tube M2 is connected with an external input control signal eight, and the source electrode is connected with the cathode of the first high-K dielectric power device S1 and the floating potential SW; one end of the first coupling capacitor C1 is connected with the output end G1 and the anode of the first high-K dielectric power device S1, and the other end is connected with the slave gate of the first high-K dielectric power device S1; the main grid of the first high-K dielectric power device S1 is connected with an external input control signal six, and the auxiliary grid is connected with an external input control signal five;
the second die is composed of a second power supply Vcc2, a third NMOS transistor M3, a fourth NMOS transistor M4, a second coupling capacitor C2 and a second high-K dielectric power device S2; the second power supply Vcc2 is connected to the drain of the third NMOS transistor M3; the grid electrode of the third NMOS tube M3 is connected with an external input control signal nine, and the source electrode of the third NMOS tube M3578 is connected with the drain electrode of the fourth NMOS tube M4 to form an output end G2 of the second tube core; the grid electrode of the fourth NMOS tube M4 is connected with an external input control signal ten, and the source electrode is connected with the cathode electrode of the second high-K dielectric power device S2, the source electrode of the low-side GaN tube M6 and the ground; one end of the second coupling capacitor C2 is connected with the output end G2 and the anode of the second high-K dielectric power device S2, and the other end is connected with the slave gate of the second high-K dielectric power device S2; the main gate of the second high-K dielectric power device S2 is connected to the external input control signal twelve, and the slave gate is connected to the external input control signal eleven.
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