CN114497206A - Heterojunction bipolar transistor and manufacturing method thereof - Google Patents

Heterojunction bipolar transistor and manufacturing method thereof Download PDF

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Publication number
CN114497206A
CN114497206A CN202210160215.4A CN202210160215A CN114497206A CN 114497206 A CN114497206 A CN 114497206A CN 202210160215 A CN202210160215 A CN 202210160215A CN 114497206 A CN114497206 A CN 114497206A
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region
epitaxial layer
ion implantation
layer
collector
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段文婷
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66242—Heterojunction transistors [HBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
    • H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors

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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

The invention provides a heterojunction bipolar transistor, comprising: a substrate layer, a buried layer and a first epitaxial layer; in the first epitaxial layer, a collector region, shallow trench isolation and collector region extraction are arranged; a second epitaxial layer is arranged above the first epitaxial layer; an emitting region is arranged above the second epitaxial layer, internal side walls are arranged on the inner surface, the lower surface and two sides of the emitting region, and external side walls are arranged outside two sides of the emitting region; and a first ion implantation region and a second ion implantation region are arranged in the second epitaxial layer, and an impurity expansion region is arranged below the inner side wall. The invention also provides a manufacturing method of the heterojunction bipolar transistor, wherein an emitter region is formed after a second epitaxial layer is formed above the collector region, and an outer side wall is formed outside the emitter region; and sequentially carrying out first ion implantation and second ion implantation on the second epitaxial layer. Accordingly, the highest oscillation frequency of the heterojunction bipolar transistor device can be increased, and the device can be manufactured.

Description

Heterojunction bipolar transistor and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor devices, and more particularly to heterojunction bipolar transistors.
The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of a heterojunction bipolar transistor.
Background
A silicon germanium Heterojunction Bipolar Transistor (SiGe HBT), is a good choice for ultra high frequency devices. Firstly, the energy band difference of SiGe and Si (silicon) is utilized to improve the carrier injection efficiency of an emitting region and increase the current amplification factor of a device; secondly, the high doping of the SiGe outer base region is utilized to reduce the resistance of the base region and improve the characteristic frequency; in addition, the SiGe process is basically compatible with the silicon process, and thus the SiGe HBT has become one of the mainstream of the uhf device.
In the prior art, the technical problems to be solved are as follows: how to increase the highest oscillation frequency of the device.
Disclosure of Invention
The technical problems to be solved by the invention are as follows: how to increase the highest oscillation frequency of the device.
In order to solve the above technical problems, the present invention provides a heterojunction bipolar transistor, which aims to increase the highest oscillation frequency of the device.
In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a heterojunction bipolar transistor, which is intended to manufacture the heterojunction bipolar transistor.
In order to achieve the above object, the present invention provides a heterojunction bipolar transistor comprising:
a substrate layer, a buried layer and a first epitaxial layer;
in the first epitaxial layer, a collector region, shallow trench isolation and collector region extraction are arranged;
a second epitaxial layer is arranged above the first epitaxial layer;
an emitting region is arranged above the second epitaxial layer, internal side walls are arranged on the inner surface, the lower surface and two sides of the emitting region, and external side walls are arranged outside two sides of the emitting region;
and a first ion implantation region and a second ion implantation region are arranged in the second epitaxial layer, and an impurity expansion region is arranged below the inner side wall.
Preferably, the buried layer is positioned at the adjacent position of the upper surface of the substrate layer and the lower surface of the first epitaxial layer, is partially positioned in the substrate layer and is partially positioned in the first epitaxial layer;
the collector region and the range of the collector region led out of the collector region and aligned with the buried layer in the up-down direction are arranged between the upper surface of the buried layer and the upper surface of the first epitaxial layer in a penetrating mode;
the shallow trench isolation is arranged on the upper surface of the first epitaxial layer; the shallow trench isolation, the collector region, the shallow trench isolation, the collector region extraction and the shallow trench isolation are sequentially arranged in the left and right directions;
the second epitaxial layer is arranged above the collector region in a spanning mode and within the shallow trench isolation range on the two sides of the collector region, completely covers the collector region, and partially covers the shallow trench isolation on the two sides of the collector region;
the emission region is aligned with the collector region in the up-down direction, and the emission region is located in the coverage range of the collector region when viewed in projection.
Preferably, the emitter region is aligned in the upper-lower direction of the second epitaxial layer to form a base region, and the second epitaxial layer outside the base region and outside the emitter region and the external side wall alignment region is provided with an outer base region;
the first ion implantation area and the second ion implantation area are positioned in the outer base area.
Preferably, contact holes are respectively arranged above the leading-out position of the collector region, the emitting region and the outer base region, and metal is filled to connect the contact holes into a collector electrode, an emitting electrode and a base electrode.
Preferably, the substrate layer is a first electric type silicon substrate;
the buried layer is a second electric type ion implantation buried layer;
the first epitaxial layer is a second electric type silicon epitaxy;
the extraction of the collector region and the collector region is the second electric type ion implantation;
the second epitaxial layer is a first electric type germanium-silicon epitaxial layer;
the emitter region is polysilicon; the ion implantation in the emission region is of a second electric type;
the first ion implantation area, the second ion implantation area and the impurity extension area in the second epitaxial layer are of a first electric type.
In order to achieve the above object, the present invention also provides a method of manufacturing a heterojunction bipolar transistor,
forming a second epitaxial layer above the collector region and then forming an emitter region, wherein an outer side wall is formed outside the emitter region;
and sequentially carrying out first ion implantation and second ion implantation on the second epitaxial layer.
Preferably, the first ion implantation has a first energy and a first dose, and the second ion implantation has a second energy and a second dose;
an inner side wall is formed inside the emitting region and close to the second epitaxial layer;
the second epitaxial layer outside the coverage range of the emitter region and the outer side wall of the emitter region is provided with an outer base region;
compared with the first ion implantation and the second ion implantation, the first energy of the first ion implantation is larger, the first dose is smaller, and the first energy can drive the first ion to enter the deeper part of the outer base region to the second epitaxial layer without breaking down the second epitaxial layer;
the second energy of the second ion implantation is smaller, the second dosage is larger, and the second energy can drive the second ion distribution to be positioned above the first ion;
and impurities of the first ion implantation and the second ion implantation are expanded to be below the inner side wall.
Preferably, on the substrate layer of the first electric type, patterning an ion implantation region of the buried layer, forming a buried layer of the second electric type by ion implantation of the second electric type; regrowing a first epitaxial layer of a second electrical type;
opening a shallow trench isolation region by utilizing active region photoetching, depositing to form shallow trench isolation, and performing second electrical type ion implantation depth on a collector region and a collector region lead-out region to reach the upper surface of a second electrical type buried layer;
growing a second epitaxial layer, and patterning the second epitaxial layer to the collector region and the shallow trench isolation range on two sides of part of the collector region;
growing an inner side wall, depositing to form an emitting region, and then forming an outer side wall;
performing ion implantation of a second electric type on the emitter region;
the second epitaxial layer at the upper and lower aligned positions of the emitter region is a base region, and the second epitaxial layer outside the coverage range of the outer side walls of the emitter region and the emitter region is an outer base region;
carrying out first ion implantation of a first electric type on an epitaxial region of the second epitaxial layer so that the ions of the first electric type are implanted to the deep part of the second epitaxial layer and stop in the second epitaxial layer without breaking down the second epitaxial layer; performing second ion implantation of the first electric type above the first ion implantation; and impurities of the first ion implantation and the second ion implantation are expanded to the second epitaxial layer below the inner side wall.
Preferably, the substrate layer of the first electrical type is a silicon substrate; the first epitaxial layer is a silicon epitaxial layer;
the second epitaxial layer is a germanium-silicon epitaxial layer;
polysilicon is deposited in the emitter region.
Preferably, contact holes are etched at the leading-out positions of the outer base region, the emitter region and the collector region, metal electrodes are deposited, a base electrode, an emitter electrode and a collector electrode are formed, and the device is manufactured.
Compared with the prior art, the invention provides a heterojunction bipolar transistor, comprising: a substrate layer, a buried layer and a first epitaxial layer; in the first epitaxial layer, a collector region, shallow trench isolation and collector region extraction are arranged; a second epitaxial layer is arranged above the first epitaxial layer; an emitting region is arranged above the second epitaxial layer, internal side walls are arranged on the inner surface, the lower surface and two sides of the emitting region, and external side walls are arranged outside two sides of the emitting region; and a first ion implantation region and a second ion implantation region are arranged in the second epitaxial layer, and an impurity expansion region is arranged below the inner side wall. The invention also provides a manufacturing method of the heterojunction bipolar transistor, wherein an emitter region is formed after a second epitaxial layer is formed above the collector region, and an outer side wall is formed outside the emitter region; and sequentially carrying out first ion implantation and second ion implantation on the second epitaxial layer. Accordingly, the present invention can achieve the technical effect of increasing the highest oscillation frequency of the heterojunction bipolar transistor device.
Drawings
Fig. 1 shows a schematic structural diagram of an embodiment of a heterojunction bipolar transistor provided by the present invention.
Fig. 2 shows a schematic diagram comparing the longitudinal distribution of the first electric type impurity in the outer base region of the heterojunction bipolar transistor provided by the present invention with that of the heterojunction bipolar transistor in the prior art.
Fig. 3A to 3E show schematic diagrams of part of the stages of an embodiment of a method of manufacturing a heterojunction bipolar transistor according to the invention.
Description of reference numerals:
101 substrate layer
102 buried layer
103 first epitaxial layer
104 shallow trench isolation
105 collector region lead-out
106 collector region
107 second epitaxial layer
108 inner side wall
109 emission area
110 external side wall
111 base electrode
112 emitter
113 collector electrode
114 impurity extension region
115 first ion implantation
116 second ion implantation
117 base region
118 outer base region.
Detailed Description
The following describes in detail embodiments of the present invention with reference to the drawings.
Referring to fig. 1, the present invention provides a heterojunction bipolar transistor, comprising: substrate layer 101, buried layer 102, first epitaxial layer 103. In the first epitaxial layer 103, a collector region 106, a shallow trench isolation 104, and a collector region extraction 105 are provided. A second epitaxial layer 107 is provided over the first epitaxial layer 103. An emitting region 109 is arranged above the second epitaxial layer 107, inner side walls 108 are arranged on the inner surface, the lower surface and two sides of the emitting region 109, and outer side walls 110 are arranged outside two sides of the emitting region 109. In the second epitaxial layer 107, a first ion implantation 115 region and a second ion implantation 116 region are provided, and an impurity extension region 114 is provided below the inner sidewall 108.
The buried layer 102 is located at the border of the upper surface of the substrate layer 101 and the lower surface of the first epitaxial layer 103, partly in the substrate layer 101 and partly in the first epitaxial layer 103. Collector region 106 and collector region extraction 105 are disposed through the upper surface of buried layer 101 to the upper surface of first epitaxial layer 103 within a range aligned with buried layer 102 in the up-down direction. Shallow trench isolation 104 is provided at the upper surface of the first epitaxial layer 103; in the left-right direction, sequentially arranged are: shallow trench isolation 104, collector region 106, shallow trench isolation 104, collector region extraction 105 and shallow trench isolation 104. The second epitaxial layer 107 spans over the collector region 106 and the shallow trench isolation 104 on both sides of the collector region 106, and completely covers the collector region 106 and partially covers the shallow trench isolation 104 on both sides of the collector region. The emitter region 109 is arranged in the vertical direction in alignment with the collector region 106, and the emitter region 109 is located within the coverage of the collector region 106 when viewed in projection.
Aligned vertically in the second epitaxial layer 107 to the emitter region 109 is a base region 117. An extrinsic base region 118 is provided in the second epitaxial layer 107 outside the base region 117 and outside the emitter region 109 and outside the outer sidewall 110 alignment region. A first ion implantation 115 region and a second ion implantation 116 region are located in the extrinsic base region 118.
Contact holes are respectively arranged above the collector region leading-out 105, the emitter region 109 and the outer base region 118, and metal is filled to connect the contact holes into a collector electrode 113, an emitter electrode 112 and a base electrode 111.
The substrate layer 101 is a first electrical type silicon substrate (taking P type as the first electrical type as an example, the corresponding electrical type is marked in the following brackets; certainly, the electrical types can be exchanged without being limited thereto). The buried layer 102 is a second electric type ion implantation buried layer (N type). The first epitaxial layer is a second electrical type silicon Si epitaxial (N type). Collector region 106 and collector region extraction 105 are of a second electric type (N type) ion implantation. The second epitaxial layer 107 is a first electrical type SiGe epitaxy (P-type). The emitter region 109 is polysilicon and the ion implantation in the emitter region 109 is of the second electrical type (N-type). The first ion implantation 115 region, the second ion implantation 116 region, and the impurity extension region 114 in the second epitaxial layer 107 are of the first electrical type (P-type).
Referring to fig. 3A to 3E, a method for manufacturing a heterojunction bipolar transistor according to the present invention is shown.
Referring to fig. 3D, after forming the second epitaxial layer 107 over the collector region 106, an emitter region 109 is formed, and outside sidewalls 110 are formed outside the emitter region 109. The second epitaxial layer 107 is sequentially subjected to a first ion implantation 115 and a second ion implantation 116.
The first ion implant 115 has a first energy and a first dose and the second ion implant has a second energy and a second dose. Inside the emitter region 109, near the second epitaxial layer 107, inner sidewalls 110 are formed. The second epitaxial layer 107 outside the area covered by the emitter region 109 and the outer sidewall 110 of the emitter region 109 has an extrinsic base region 118. Compared with the second ion implantation 116, the first ion implantation 115 has a larger first energy and a smaller first dose, and the first energy can drive the first ion to enter the deeper part of the outer base region 118 to the second epitaxial layer 107, but does not break through the second epitaxial layer 107. The second ion implantation 116 has a smaller second energy and a larger second dose, and the second energy can drive the second ion distribution to be located above the first ion. The impurities of the first ion implantation 115 and the second ion implantation 116 extend to below the inner sidewall 110.
Referring to fig. 3A, on a substrate layer 101 of a first electrical type (taking a P type as the first electrical type as an example, and the subsequent brackets indicate corresponding electrical types; certainly, the electrical types are not limited thereto, and may be reversed), an ion implantation region of a buried layer is patterned, and a buried layer 102 of a second electrical type (N type) is formed by ion implantation of the second electrical type; a first epitaxial layer 103 of the second electrical type (N-type) is regrown.
Referring to fig. 3B, active area lithography is used to open the shallow trench isolation 104 region, and then the shallow trench isolation 104 is deposited, and ion implantation of the second electrical type (N type) is performed in the collector region 106 and the collector region extraction 105 region to a depth reaching the upper surface of the buried layer 102 of the second electrical type.
Referring to fig. 3C, a second epitaxial layer 107 is grown and the second epitaxial layer 107 is patterned into the collector region 105 and into the shallow trench isolation 104 on both sides of a portion of the collector region. In other words, second epitaxial layer 107 does not exceed shallow trench isolation 104 on both sides of collector region 105, but completely covers collector region 105. In particular, the portions of the two ends beyond the points 105 are symmetrically arranged.
Referring to fig. 3D, inner sidewalls 108 are grown, emitter regions 109 are deposited, and outer sidewalls 110 are formed. The spacers are not limited to silicon nitride, silicon oxide, etc.
Referring to fig. 3D, a second electrical type (N-type) ion implantation is performed on the emitter region 109.
Referring to fig. 3D, the second epitaxial layer 107 at the upper and lower alignment of the emitter region 109 is a base region 117, and the second epitaxial layer 107 outside the range covered by the emitter region 109 and the outer sidewall 110 of the emitter region is an outer base region 118. Performing a first ion implantation 115 of a first electrical type (P-type) on the epitaxial region 118 of the second epitaxial layer so that the ions of the first electrical type are implanted deep into the second epitaxial layer 107 and stop in the second epitaxial layer 107 without breaking down the second epitaxial layer 107; a second ion implantation 116 of the first electrical type (P-type) is performed above the first ion implantation 115. The impurities of the first ion implantation 115 and the second ion implantation 116 extend into the second epitaxial layer 107 under the inner sidewall 110.
Referring to fig. 3D, the substrate layer 101 of the first electrical type is a silicon substrate Si. The first epitaxial layer 103 is a silicon epitaxial layer Si. The second epitaxial layer 107 is a silicon germanium epitaxial layer SiGe. Polysilicon Poly is deposited in emitter region 109.
Referring to fig. 3E, contact holes are etched at the outer base region 118, the emitter region 109 and the collector region lead-out 105, metal electrodes are deposited to form a base 111, an emitter 112 and a collector 113, and the device is manufactured.
The above is a specific embodiment of the heterojunction bipolar transistor and the manufacturing method thereof provided by the present invention.
Referring to fig. 2, a vertical profile of the impurity of the first electrical type at the extrinsic base region 118 is shown. In order to improve the maximum oscillation frequency f of the SiGe HBTmaxThe extrinsic base region 118 is implanted using two implants, the upper one with a high dose and low energy (second ion implant 116) and the lower one with a low dose and high energy (first ion implant 115), but without penetrating the SiGe epitaxy (second epitaxial layer 107). Base resistance R due to dosage increaseBReducing (here, the resistance of the outer base region 118), and simultaneously implanting impurities into the outer base region 118 to extend into the SiGe epitaxy (the partial base region 117 of the second epitaxial layer 107) under the inner sidewall 108, further reducing the base resistance RBTwo injections make the collector junction (BC junction) more gradual, thus CBCAnd decreases. Maximum oscillation frequency fmaxIs calculated by the formula
Figure BDA0003514253390000071
Due to RBAnd CBCAre all reduced, and therefore the highest oscillation frequency fmaxAnd (4) increasing. Therefore, the invention can achieve the technical effect of increasing the highest oscillation frequency of the device. And the corresponding device provided by the invention can be manufactured by the method of the invention.
The above-mentioned embodiments and the accompanying drawings are only for illustrating the technical solutions and effects of the present invention, and are not to be construed as limiting the present invention. It is to be understood that those skilled in the art can modify and change the above-described embodiments without departing from the technical spirit and scope of the present invention as defined in the appended claims.

Claims (10)

1. A heterojunction bipolar transistor, comprising:
a substrate layer, a buried layer and a first epitaxial layer;
in the first epitaxial layer, a collector region, shallow trench isolation and collector region extraction are arranged;
a second epitaxial layer is arranged above the first epitaxial layer;
an emitting region is arranged above the second epitaxial layer, internal side walls are arranged on the inner surface, the lower surface and two sides of the emitting region, and external side walls are arranged outside two sides of the emitting region;
and a first ion implantation region and a second ion implantation region are arranged in the second epitaxial layer, and an impurity expansion region is arranged below the inner side wall.
2. The heterojunction bipolar transistor of claim 1,
the buried layer is positioned at the adjacent position of the upper surface of the substrate layer and the lower surface of the first epitaxial layer, is partially positioned in the substrate layer and is partially positioned in the first epitaxial layer;
the collector region and the range of the collector region led out of the collector region and aligned with the buried layer in the up-down direction are arranged between the upper surface of the buried layer and the upper surface of the first epitaxial layer in a penetrating mode;
the shallow trench isolation is arranged on the upper surface of the first epitaxial layer; the shallow trench isolation, the collector region, the shallow trench isolation, the collector region extraction and the shallow trench isolation are sequentially arranged in the left and right directions;
the second epitaxial layer is arranged above the collector region in a spanning mode and within the shallow trench isolation range on the two sides of the collector region, completely covers the collector region, and partially covers the shallow trench isolation on the two sides of the collector region;
the emission region is aligned with the collector region in the up-down direction, and the emission region is located in the coverage range of the collector region when viewed in projection.
3. A heterojunction bipolar transistor according to claim 2,
a base region is arranged at the position, aligned with the emitter region, of the second epitaxial layer in the up-down direction, and an outer base region is arranged in the second epitaxial layer outside the base region and outside the emitter region and the outer side wall alignment region;
the first ion implantation area and the second ion implantation area are positioned in the outer base area.
4. A heterojunction bipolar transistor as claimed in claim 3, wherein contact holes are respectively formed above the extraction portion of the collector region, the emitter region and the extrinsic base region, and metal is filled to connect the contact holes to form a collector, an emitter and a base.
5. The heterojunction bipolar transistor of claim 1,
the substrate layer is a first electric type silicon substrate;
the buried layer is a second electric type ion implantation buried layer;
the first epitaxial layer is a second electric type silicon epitaxy;
the extraction of the collector region and the collector region is the second electric type ion implantation;
the second epitaxial layer is a first electric type germanium-silicon epitaxial layer;
the emitter region is made of polysilicon; the ion implantation in the emission region is of a second electric type;
the first ion implantation area, the second ion implantation area and the impurity extension area in the second epitaxial layer are of a first electric type.
6. A method of manufacturing a heterojunction bipolar transistor,
forming a second epitaxial layer above the collector region and then forming an emitter region, wherein an outer side wall is formed outside the emitter region;
and sequentially carrying out first ion implantation and second ion implantation on the second epitaxial layer.
7. The method of manufacturing a heterojunction bipolar transistor according to claim 6,
the first ion implantation has a first energy and a first dosage, and the second ion implantation has a second energy and a second dosage;
an inner side wall is formed inside the emitting region and close to the second epitaxial layer;
the second epitaxial layer outside the coverage range of the emitter region and the outer side wall of the emitter region is provided with an outer base region;
compared with the first ion implantation and the second ion implantation, the first energy of the first ion implantation is larger, the first dose is smaller, and the first energy can drive the first ion to enter the deeper part of the outer base region to the second epitaxial layer without breaking down the second epitaxial layer;
the second energy of the second ion implantation is smaller, the second dosage is larger, and the second energy can drive the second ion distribution to be positioned above the first ion;
and impurities of the first ion implantation and the second ion implantation are expanded to be below the inner side wall.
8. The method of manufacturing a heterojunction bipolar transistor according to claim 6,
patterning an ion implantation area of the buried layer on the substrate layer of the first electric type, and forming a buried layer of a second electric type through ion implantation of the second electric type; regrowing a first epitaxial layer of a second electrical type;
opening a shallow trench isolation region by utilizing active region photoetching, depositing to form shallow trench isolation, and performing second electrical type ion implantation depth on a collector region and a collector region lead-out region to reach the upper surface of a second electrical type buried layer;
growing a second epitaxial layer, and patterning the second epitaxial layer to the collector region and the shallow trench isolation range on two sides of part of the collector region;
growing an inner side wall, depositing to form an emitting region, and then forming an outer side wall;
performing ion implantation of a second electric type on the emitter region;
the second epitaxial layer at the upper and lower aligned positions of the emitter region is a base region, and the second epitaxial layer outside the coverage range of the outer side walls of the emitter region and the emitter region is an outer base region;
carrying out first ion implantation of a first electric type on an epitaxial region of the second epitaxial layer so that the ions of the first electric type are implanted to the deep part of the second epitaxial layer and stop in the second epitaxial layer without breaking down the second epitaxial layer; performing second ion implantation of the first electric type above the first ion implantation; and impurities of the first ion implantation and the second ion implantation are expanded to the second epitaxial layer below the inner side wall.
9. The method of manufacturing a heterojunction bipolar transistor according to claim 8,
the first electric type substrate layer is a silicon substrate; the first epitaxial layer is a silicon epitaxial layer;
the second epitaxial layer is a germanium-silicon epitaxial layer;
polysilicon is deposited in the emitter region.
10. The method of claim 8, wherein contact holes are formed at the leading-out positions of the outer base region, the emitter region and the collector region, and metal electrodes are deposited to form a base electrode, an emitter electrode and a collector electrode, thereby completing the device fabrication.
CN202210160215.4A 2022-02-22 2022-02-22 Heterojunction bipolar transistor and manufacturing method thereof Pending CN114497206A (en)

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