CN114864681A - NLDMOS device, preparation method of NLDMOS device and chip - Google Patents

NLDMOS device, preparation method of NLDMOS device and chip Download PDF

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Publication number
CN114864681A
CN114864681A CN202210810576.9A CN202210810576A CN114864681A CN 114864681 A CN114864681 A CN 114864681A CN 202210810576 A CN202210810576 A CN 202210810576A CN 114864681 A CN114864681 A CN 114864681A
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region
field oxide
oxide layer
nldmos device
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吴波
赵东艳
王于波
陈燕宁
付振
刘芳
邓永锋
王凯
郁文
刘倩倩
余山
王帅鹏
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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Beijing Smartchip Microelectronics Technology Co Ltd
Beijing Core Kejian Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7823—Lateral DMOS transistors, i.e. LDMOS transistors with an edge termination structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to the technical field of semiconductors, and discloses an NLDMOS device, a preparation method of the NLDMOS device and a chip. The NLDMOS device comprises: a substrate; the P-type body region and the N-type drift region are arranged on the substrate; a field oxide layer with a specific opening arranged on the N-type drift region; and locate P type body district with grid on the field oxide, wherein, specific open-ended one side exceedes the outer edge of grid homonymy is located in specific opening the thickness of field oxide is at the predetermined range. The invention effectively solves the problem that the breakdown voltage and the on-resistance are contradictory, can improve the breakdown voltage of the NLDMOS device and reduce the on-resistance of the NLDMOS device.

Description

NLDMOS device, preparation method of NLDMOS device and chip
Technical Field
The invention relates to the technical field of semiconductors, in particular to an NLDMOS device, a preparation method of the NLDMOS device and a chip.
Background
LDMOS (Laterally Diffused Metal Oxide Semiconductor) has the characteristics of high voltage resistance, large current driving capability, low power consumption and the like, and is widely applied to power management circuits. In the BCD (Bipolar-CMOS-DMOS) process, LDMOS and CMOS (Complementary Metal Oxide Semiconductor) are integrated in the same chip and process flow, so that power consumption can be greatly reduced, system performance is improved, circuit packaging cost is saved, better reliability is achieved, and more selection space is provided for chip circuits of the process during design. Under the premise that the conditions of a channel region and a drift region of the LDMOS device are shared with the existing process conditions of the CMOS, the on resistance and the Breakdown Voltage (BV) of the LDMOS device have a contradiction relationship, and the LDMOS device often cannot meet the target of the LDMOS device, namely high withstand voltage and low on resistance, or the lowest on resistance is provided under a given working voltage.
Currently, the breakdown voltage is increased by increasing the length of the channel and drift region or decreasing the doping concentration of the drift region, but this increases the area and on-resistance of the LDMOS device. That is, the breakdown voltage and the on-resistance of the conventional LDMOS device are limited to each other, and only a balance point between the on-resistance and the breakdown voltage can be obtained.
Disclosure of Invention
The invention aims to provide an NLDMOS device, a preparation method of the NLDMOS device and a chip, which effectively solve the problem that breakdown voltage and on-resistance are mutually contradictory, can improve the breakdown voltage of the NLDMOS device and can reduce the on-resistance of the NLDMOS device.
In order to achieve the above object, a first aspect of the present invention provides an NLDMOS device, including: a substrate; the P-type body region and the N-type drift region are arranged on the substrate; a field oxide layer with a specific opening arranged on the N-type drift region; and locate P type body district with grid on the field oxide, wherein, specific open-ended one side exceedes the outer edge of grid homonymy is located in specific opening the thickness of field oxide is at the predetermined range.
Preferably, the thickness of the field oxide layer located in the specific opening is the same.
Preferably, a ratio of a lateral length of the specific opening to a lateral length of the field oxide layer is a preset ratio.
Preferably, the NLDMOS device further includes: and the first P-type buried layer is arranged on the N-type drift region, wherein the position of the first P-type buried layer corresponds to the position of the specific opening.
Preferably, the NLDMOS device further includes: and the second P-type buried layer is arranged on the substrate and is connected with the P-type body region and the N-type drift region.
Preferably, the NLDMOS device further includes: the first high-voltage N-type well region is arranged on the substrate, and the P-type body region and the N-type drift region are arranged on the first high-voltage N-type well region; or locate second high pressure N type well region, N type isolation layer and third high pressure N type well region on the substrate, wherein, second high pressure N type well region N type isolation layer with third high pressure N type well region forms and encloses P type somatic region with the isolation space in N type drift region.
Preferably, the NLDMOS device further includes: and the N-type heavily doped region is arranged on the N-type drift region, wherein one side of the field oxide layer is connected with the N-type heavily doped region.
Preferably, the substrate is a P-type substrate.
Through the technical scheme, the field oxide layer is creatively provided with the opening, one side of the opening extends beyond the outer edge of the corresponding side of the grid, and the thickness of the field oxide layer in the opening area is basically uniform, namely, the thickness distribution of the field oxide layer is optimized to improve the electric field modulation capability of the grid, so that the surface electric field of the grid covering area is reduced, and the purposes of simultaneously improving the breakdown voltage and reducing the on-resistance can be realized.
The second aspect of the present invention provides a method for manufacturing an NLDMOS device, where the method includes: forming a substrate; forming a P-type body region and an N-type drift region on the substrate; forming a field oxide layer with a specific opening on the N-type drift region; and P type body district with form the grid on the field oxide, wherein, specific open-ended one side exceedes the outer edge of grid homonymy is located in specific open-ended in the thickness of field oxide is at predetermineeing the within range.
Preferably, the preparation method further comprises: forming a first P-type buried layer on the N-type drift region through a specific mask, and accordingly, forming a field oxide layer having a specific opening on the N-type drift region includes: forming an initial field oxide layer on the N-type drift region; and forming the specific opening on the initial field oxide layer through the specific mask to obtain the field oxide layer with the specific opening, wherein the position of the first P-type buried layer corresponds to the position of the specific opening.
The third aspect of the invention provides a chip, which comprises the NLDMOS device.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a schematic structural diagram of an NLDMOS device according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing an NLDMOS device according to an embodiment of the present invention; and
fig. 3 to fig. 7 are schematic structural diagrams of an NLDMOS device according to an embodiment of the present invention in a manufacturing process.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a schematic structural diagram of an NLDMOS device according to an embodiment of the present invention. As shown in fig. 1, the NLDMOS device may include: a substrate 101; a P-type body region 106 and an N-type drift region 105 disposed on the substrate; a field oxide layer 108 having a specific opening and disposed on the N-type drift region 105; and a gate 111 disposed on the P-type body region 106 and the field oxide layer 108, wherein one side (e.g., right side) of the specific opening exceeds an outer edge of the gate 111 on the same side (e.g., right side), and a thickness of the field oxide layer in the specific opening (i.e., in the ABCD region) is within a predetermined range.
The field oxide layer 108 may be a LOCOS field oxide layer. The gate 111 (e.g., polysilicon gate) fills the opening of the field oxide (e.g., LOCOS field oxide) 108.
The substrate 101 may be a P-type substrate, or a P-type substrate and a P-type epitaxial layer.
The inventor has found that when the drain voltage of the LDMOS device is high, a peak of the electric field strength is located in a region corresponding to the outer edge of the gate 111 in the boundary region between the field oxide layer 108 and the N-type drift region 105 due to the outer edge (i.e., field plate terminal) of the gate 111. In this embodiment, the outer edge of the gate 111 is disposed in the opening region of the field oxide layer, and the thickness of the field oxide layer corresponding to the opening region is substantially uniform (i.e., the thickness of the field oxide layer in the region is within a predetermined range), so as to improve the electric field modulation capability of the gate, reduce the surface electric field of the gate coverage region, and further achieve the purpose of simultaneously improving the breakdown voltage and reducing the on-resistance.
In a preferred embodiment, the thickness of the field oxide layer located within the specific opening is the same. Therefore, the electric field modulation capability of the grid can be improved by further optimizing the thickness distribution of the field oxide layer, so that the surface electric field of the grid covering region is further reduced, and the purposes of improving the breakdown voltage and reducing the on-resistance can be realized.
The inventor obtains the following conclusion through theoretical research, simulation and experimental verification: the electric field modulation capability of the gate depends on the ratio of the width (i.e. lateral length, length of AB or CD) of the specific opening to the lateral length of the field oxide layer, so that the electric field modulation capability of the gate can be improved by setting the appropriate opening width. Therefore, in an embodiment, the ratio of the lateral length of the specific opening to the lateral length of the field oxide layer is a predetermined ratio, so that the electric field modulation capability of the gate can be more effectively improved. Wherein the preset ratio may be any one of [1/10,1/2 ]. Of course, the present invention is not limited to the ratios within the above ranges, and ratios within the ranges obtained by reasonable fine adjustment are also possible.
In an embodiment, the NLDMOS device may further include: a first P-type buried layer 103 disposed on the N-type drift region, wherein a position of the first P-type buried layer 103 corresponds to a position of the specific opening (i.e., ABCD area).
The inventor finds that the depletion of the drift region can be effectively increased by arranging the P-type buried layer in the drift region, and the surface electric field of the drift region is reduced, so that the breakdown voltage of the NLDMOS device can be improved, and the on-resistance of the NLDMOS device can be reduced. And if the position of the P-type buried layer is matched with the position of the opening of the field oxide layer, in the process of preparing the NLDMOS device, the opening of the field oxide layer and the P-type buried layer can be formed only through the same mask, so that the cost of the mask can be saved, and meanwhile, the surface electric field of a drift region can be further reduced through the P-type buried layer matched with the position of the opening of the field oxide layer, so that the breakdown voltage of the NLDMOS device can be improved, and the on-resistance of the NLDMOS device can be reduced.
In an embodiment, the NLDMOS device may further include: a second P-type buried layer 104 disposed on the substrate 101, wherein the second P-type buried layer 104 connects the P-type body region 106 and the N-type drift region 105. The second P-type buried layer 104 can increase the depletion of the drift region, reduce the surface electric field (form a RESURF structure), and finally improve the breakdown voltage of the device.
In an embodiment, the NLDMOS device may further include: a first high voltage N-well 102 disposed on the substrate 101, wherein the P-type body region 106 and the N-type drift region 105 are disposed on the first high voltage N-well 102.
That is, the P-type body region 106 and the N-type drift region 105 are disposed on the first hvnw 102, rather than directly on the substrate 101, and of course, other layers/regions (e.g., the second P-type buried layer 104) are correspondingly disposed on the first hvnw 102. Compared with the other embodiments (the P-type body region 106 and the N-type drift region 105 are directly disposed on the substrate), when the device is affected by external or parasitic inductance, the substrate generates a sufficiently large forward bias, and since the first high-voltage N-well region 102 in this embodiment isolates the P-type body region 106, the second P-type buried layer 104 and the substrate 101, injection of electrons from the drain into the substrate is suppressed, thereby suppressing latch-up (latch-up) and other reliability problems.
In an embodiment, the NLDMOS device may further include: and a second high voltage N-well (not shown), an N-isolation layer (not shown), and a third high voltage N-well (not shown) disposed on the substrate 101, wherein the second high voltage N-well, the N-isolation layer, and the third high voltage N-well form an isolation space surrounding the P-type body region 106 and the N-type drift region 105.
Compared to the previous embodiment (the first hvnw 102 isolates the P-type body region 106 from the N-type drift region 105), the higher doping concentration of the N-type isolation layer in this embodiment has better effect of suppressing latch-up, and at the same time, the reduced first hvnw 102 can effectively lower the on-resistance.
In an embodiment, the NLDMOS device may further include: an N-type heavily doped region (i.e., drain region) 118 disposed on the N-type drift region 105, wherein one side of the field oxide layer 108 is connected to the N-type heavily doped region (i.e., drain region) 118.
In an embodiment, the NLDMOS device may further include: a sidewall spacer 112 and a Self-Aligned silicide Block (SAB) 113 disposed on the field oxide layer 108; isolation regions 107 (e.g., shallow isolation trenches), as shown in fig. 1.
In an embodiment, the NLDMOS device may further include: a heavily N-doped region 109 (i.e., source region) and a heavily P-doped region 110 disposed over the P-type body region 106, as shown in fig. 1.
In summary, the present invention creatively provides an opening on the field oxide layer, wherein one side of the opening extends beyond the outer edge of the corresponding side of the gate, and the thickness of the field oxide layer in the opening region is substantially uniform, that is, the thickness distribution of the field oxide layer is optimized to improve the electric field modulation capability of the gate, thereby reducing the surface electric field of the gate coverage region, and further achieving the purpose of simultaneously improving the breakdown voltage and reducing the on-resistance.
Fig. 2 is a flowchart of a method for manufacturing an NLDMOS device according to an embodiment of the present invention. As shown in fig. 2, the preparation method may include: step S201, forming a substrate; step S202, forming a P-type body region and an N-type drift region on the substrate; step S203, forming a field oxide layer with a specific opening on the N-type drift region; and step S204, forming a grid on the P-type body region and the field oxide layer.
Wherein, one side of the specific opening exceeds the outer edge of the grid on the same side, and the thickness of the field oxide layer in the specific opening is within a preset range.
The substrate 101 may be a P-type substrate, or a P-type substrate and a P-type epitaxial layer.
The following describes the fabrication process of the NLDMOS device with reference to fig. 3 to 7.
As shown in FIG. 3, implanted phosphorus is formed on a P-type substrate 101 (e.g., P-type silicon substrate/silicon epitaxial layer) at an energy of 2000keV to 3500keV and a dose of 10 11 ～10 13 cm -2 (ii) a Then, HNW (High Voltage N Well) 102 is formed by High temperature annealing at 1000-1200 ℃ for 120-650 minutes.
An isolation region 107 (e.g., shallow trench isolation, STI) is formed for isolation by photolithography and etching, the etching depth of the trench is 3000-4000A, and the etching angle is 65-75 degrees.
As shown in fig. 4, silicon oxide and silicon nitride are deposited on the P-type silicon substrate as a hard mask, a field oxide region is defined in the first hvnw region 102 of the drift region by photolithography, local oxidation (LOCOS) growth is performed and a field oxide layer (e.g., LOCOS field oxide layer) 108 is formed. The thickness of the silicon oxide of the hard mask is 100-300A, the thickness of the silicon nitride is 150-800A, and the thickness of the LOCOS field oxide layer is 500-3500A. The silicon nitride and silicon oxide of the hard mask are then removed.
In one embodiment, the preparation method may further include: and forming a first P-type buried layer on the N-type drift region through a specific mask. Accordingly, the forming of the field oxide layer having a specific opening on the N-type drift region may include: forming an initial field oxide layer on the N-type drift region; and forming the specific opening on the initial field oxide layer through the specific mask to obtain the field oxide layer with the specific opening, wherein the position of the first P-type buried layer corresponds to the position of the specific opening.
As shown in fig. 5, a first P-type buried layer 103 is formed on the upper surface of the field oxide layer 108 by ion implantation under the field oxide layer 108 (inside the drift region) using a patterned photo-resist 115 as a mask, wherein boron is used as an impurity and the implantation dose is 5e11cm -2 ～5e12cm -2 The implantation energy is 20Kev to 500 Kev.
Thereafter, an opening is opened in the upper surface of the field oxide layer 108 by wet etching using a hydrofluoric acid (HF) containing solution using the patterned photoresist 115 as a mask. The wet etching is isotropic etching, and the bottom and the opening of the photoresist are etched.
As shown in fig. 6, the photoresist 115 is removed. The whole surface of the device is subjected to wet etching by a solution containing hydrofluoric acid (HF), the surface area at the edge of the opening is large, and therefore the etching rate at the edge is high. The edge of the opening can be made to be smooth by wet etching, and therefore the gate field plate cannot generate a tip effect on an electric field of the drift region. By controlling the etching amount of the two wet etches and the position of the photoresist 115, the following steps are carried out: the thickness of the opening vertically downwards to the lower surface of the field oxide layer is approximately equal or equal, the right end of the opening exceeds the outer edge of the right end of the grid electrode, and the width (namely the length in the transverse direction) of the opening accounts for the proportion of the transverse length of the field oxide layer to be a preset proportion. The smooth opening edge and the optimized thickness distribution of the field oxide layer improve the electric field modulation capability of the grid field plate on the transverse double-diffusion transistor.
As shown in FIG. 7, the drift region 105 is formed by implanting phosphorus into the first HVN region 102 with an energy of 200keV to 600keV and a dose of 10 keV 11 ～10 13 cm -2 (ii) a Boron is implanted into the first high voltage N well region 102 four times to form a P-type body region (i.e., channel region) 106 with an energy of 50keV to 700keV and a dose of 10 keV 12 ～10 14 cm -2 (ii) a The drift region is in contact with or at a distance from the channel region. Implanting boron into the first high voltage N well region 102 at the bottom of the drift region and the channel region to form a second P buried layer 104 with energy of 1000 keV-2000 keV and dosage of 10 keV 11 ～10 13 cm -2 (ii) a Then activating by high-temperature heat treatment at 950 ℃ for 15 seconds.
As shown in fig. 1, a gate oxide layer 117 is grown; after the growth of the gate oxide layer 117 is completed, depositing polysilicon; the gate 111 and the polysilicon field plate are defined by photolithography and etching. Implanting phosphorus and arsenic into the source region and the channel region to form an N-type lightly doped region 116 (which is self-aligned with the side of the polysilicon gate) with an energy of 40 keV-70 keV and a dose of 10 keV 13 ～10 14 cm -2 . Then, silicon dioxide and silicon nitride are deposited and etched to form a polysilicon gate 111 and a sidewall 112 of the polysilicon field plate.
Phosphorus or arsenic is implanted into the device region once or multiple times to form N-type heavily doped regions (N +, N Plus) 118, 109 of source and drain, the implantation energy is 5 keV-100 keV, and the dosage is 10 keV 13 ～10 15 cm -2 . Implanting boron once or repeatedly to form a P-type heavily doped region (P Plus) 110 with energy of 0 keV-50 keV and dosage of 10 keV 13 ～10 15 cm -2 . Silicon oxide was deposited as a Self-Aligned silicide Block (SAB) 112 and then activated by high temperature heat treatment at 1015 c for 10 seconds. The salicide block layer 112 is defined by photolithography, the salicide block layer is removed by dry etching and wet etching in the region outside the salicide block layer 112, and the exposed silicon region reacts with Co to form Co salicide (CoSalicide) 114. And (4) the finally formed NLDMOS device is in the shape.
In summary, the present invention creatively forms a field oxide layer with a specific opening on the N-type drift region, and forms a gate on the P-type body region and the field oxide layer, wherein one side of the specific opening extends beyond the outer edge of the corresponding side of the gate, and the thickness of the field oxide layer in the opening region is substantially uniform, that is, the thickness distribution of the field oxide layer is optimized to improve the electric field modulation capability of the gate, thereby reducing the surface electric field of the gate coverage region, and further achieving the purpose of simultaneously improving the breakdown voltage and reducing the on-resistance.
The third aspect of the present invention further provides a chip, which includes the NLDMOS device.
For details and advantages of the chip provided by the present invention, reference may be made to the above description for the NLDMOS device, and details are not repeated herein.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
In addition, any combination of various different implementation manners of the embodiments of the present invention is also possible, and the embodiments of the present invention should be considered as disclosed in the embodiments of the present invention as long as the combination does not depart from the spirit of the embodiments of the present invention.

Claims (11)

1. An NLDMOS device, comprising:
a substrate;
the P-type body region and the N-type drift region are arranged on the substrate;
a field oxide layer with a specific opening arranged on the N-type drift region; and
a gate electrode disposed on the P-type body region and the field oxide layer,
wherein, one side of the specific opening exceeds the outer edge of the grid electrode on the same side, and the thickness of the field oxide layer in the specific opening is within a preset range.
2. The NLDMOS device of claim 1, wherein the thickness of the field oxide layer in the specific opening is the same.
3. The NLDMOS device of claim 1, wherein a ratio of a lateral length of the specific opening to a lateral length of the field oxide layer is a predetermined ratio.
4. The NLDMOS device of claim 1, wherein the NLDMOS device further comprises:
and the first P-type buried layer is arranged on the N-type drift region, wherein the position of the first P-type buried layer corresponds to the position of the specific opening.
5. The NLDMOS device of claim 1, wherein the NLDMOS device further comprises:
and the second P-type buried layer is arranged on the substrate and is connected with the P-type body region and the N-type drift region.
6. The NLDMOS device of claim 1, wherein the NLDMOS device further comprises:
the first high-voltage N-type well region is arranged on the substrate, and the P-type body region and the N-type drift region are arranged on the first high-voltage N-type well region; or
Locate second high pressure N type well region, N type isolation layer and third high pressure N type well region on the substrate, wherein, second high pressure N type well region N type isolation layer with third high pressure N type well region forms and encloses P type somatic region with the isolation space in N type drift region.
7. The NLDMOS device of claim 1, wherein the NLDMOS device further comprises:
and the N-type heavily doped region is arranged on the N-type drift region, wherein one side of the field oxide layer is connected with the N-type heavily doped region.
8. The NLDMOS device of claim 1, wherein said substrate is a P-type substrate.
9. A preparation method of an NLDMOS device is characterized by comprising the following steps:
forming a substrate;
forming a P-type body region and an N-type drift region on the substrate;
forming a field oxide layer with a specific opening on the N-type drift region; and
forming a gate on the P-type body region and the field oxide layer,
wherein, one side of the specific opening exceeds the outer edge of the grid on the same side, and the thickness of the field oxide layer in the specific opening is within a preset range.
10. The method of manufacturing according to claim 9, further comprising: forming a first P-type buried layer on the N-type drift region through a specific mask,
correspondingly, the forming of the field oxide layer with a specific opening on the N-type drift region includes:
forming an initial field oxide layer on the N-type drift region; and
forming the specific opening on the initial field oxide layer through the specific mask to obtain the field oxide layer having the specific opening,
wherein a position of the first P-type buried layer corresponds to a position of the specific opening.
11. A chip comprising the NLDMOS device of any one of claims 1 to 8.
CN202210810576.9A 2022-07-11 2022-07-11 NLDMOS device, preparation method of NLDMOS device and chip Pending CN114864681A (en)

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291851B1 (en) * 1995-07-21 2001-09-18 Rohm Co., Ltd. Semiconductor device having oxide layers formed with different thicknesses
US20050073007A1 (en) * 2003-10-01 2005-04-07 Fu-Hsin Chen Ldmos device with isolation guard rings
US20130320445A1 (en) * 2012-06-04 2013-12-05 Ming-Tsung Lee High voltage metal-oxide-semiconductor transistor device
US20140070315A1 (en) * 2008-10-29 2014-03-13 Tower Semiconductor Ltd. Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure
CN107527857A (en) * 2016-06-22 2017-12-29 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method and electronic installation
CN108847423A (en) * 2018-05-30 2018-11-20 矽力杰半导体技术(杭州)有限公司 Semiconductor devices and its manufacturing method
CN109148304A (en) * 2018-09-04 2019-01-04 盛世瑶兰（深圳）科技有限公司 A kind of transistor and preparation method thereof
CN114050181A (en) * 2022-01-07 2022-02-15 北京芯可鉴科技有限公司 NLDMOS device, preparation method and chip
CN114695515A (en) * 2020-12-31 2022-07-01 半导体元件工业有限责任公司 Semiconductor device having transistor and method of forming semiconductor device having transistor

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6291851B1 (en) * 1995-07-21 2001-09-18 Rohm Co., Ltd. Semiconductor device having oxide layers formed with different thicknesses
US20050073007A1 (en) * 2003-10-01 2005-04-07 Fu-Hsin Chen Ldmos device with isolation guard rings
US20140070315A1 (en) * 2008-10-29 2014-03-13 Tower Semiconductor Ltd. Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure
US20130320445A1 (en) * 2012-06-04 2013-12-05 Ming-Tsung Lee High voltage metal-oxide-semiconductor transistor device
CN107527857A (en) * 2016-06-22 2017-12-29 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method and electronic installation
CN108847423A (en) * 2018-05-30 2018-11-20 矽力杰半导体技术(杭州)有限公司 Semiconductor devices and its manufacturing method
CN109148304A (en) * 2018-09-04 2019-01-04 盛世瑶兰（深圳）科技有限公司 A kind of transistor and preparation method thereof
CN114695515A (en) * 2020-12-31 2022-07-01 半导体元件工业有限责任公司 Semiconductor device having transistor and method of forming semiconductor device having transistor
CN114050181A (en) * 2022-01-07 2022-02-15 北京芯可鉴科技有限公司 NLDMOS device, preparation method and chip

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