CN114496907A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114496907A
CN114496907A CN202011263291.5A CN202011263291A CN114496907A CN 114496907 A CN114496907 A CN 114496907A CN 202011263291 A CN202011263291 A CN 202011263291A CN 114496907 A CN114496907 A CN 114496907A
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Prior art keywords
material layer
plug material
layer
opening
forming
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Chinese (zh)
Inventor
成国良
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202011263291.5A priority Critical patent/CN114496907A/en
Publication of CN114496907A publication Critical patent/CN114496907A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

A method of forming a semiconductor structure, comprising: forming a first plug material layer in the first opening and a second plug material layer in the second opening by adopting a first selective chemical vapor deposition process, wherein the top surface of the first plug material layer is higher than that of the second plug material layer; passivating the first plug material layer and the second plug material layer; after the passivation treatment, a second selective chemical vapor deposition process is adopted, a third plug material layer is formed on the surface of the first plug material layer in the first opening, the third plug material layer is filled in the first opening, a fourth plug material layer is formed on the surface of the second plug material layer in the second opening, the fourth plug material layer is filled in the second opening, and the rate of forming the third plug material layer is less than the rate of forming the fourth plug material layer. The method is beneficial to improving the performance of the formed semiconductor structure.

Description

Method for forming semiconductor structure
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.
Background
With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in the integrated circuit is continuously reduced, so that the operation speed of the whole integrated circuit can be effectively increased. As the size requirements of the components become smaller, the size of the conductive structures formed accordingly becomes smaller.
The forming method of the conductive structure comprises the following steps: providing a semiconductor substrate; forming a first dielectric layer on a semiconductor substrate, wherein the first dielectric layer is internally provided with a first opening; forming a first plug within the first opening; after the first plug is formed, forming a second dielectric layer on the surface of the first plug and the surface of the first dielectric layer; forming a second opening in the second dielectric layer; after forming the second opening, a second plug is formed within the second opening. The first and second plugs form a conductive structure. To reduce the resistance of conductive structures of increasingly smaller dimensions, materials of lower resistivity are used to form the conductive structures.
However, the performance of the semiconductor devices formed by the prior art needs to be improved.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to improve the performance of the formed semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a first conducting layer and a second conducting layer which are separated from each other; forming a first dielectric layer on the substrate, wherein the first dielectric layer is internally provided with a first opening and a second opening, the first opening exposes the first conductive layer, and the second opening exposes the second conductive layer; forming a first plug material layer in the first opening and a second plug material layer in the second opening by adopting a first selective chemical vapor deposition process, wherein the top surface of the first plug material layer is higher than that of the second plug material layer; passivating the first plug material layer and the second plug material layer; after the passivation treatment, a second selective chemical vapor deposition process is adopted, a third plug material layer is formed on the surface of the first plug material layer in the first opening, the third plug material layer is filled in the first opening, a fourth plug material layer is formed on the surface of the second plug material layer in the second opening, the fourth plug material layer is filled in the second opening, and the rate of forming the third plug material layer is less than the rate of forming the fourth plug material layer.
Optionally, the method further includes: after the first plug material layer and the second plug material layer are formed and before the passivation treatment, first ion implantation is carried out on the first dielectric layer exposed by the first opening and the second opening, so that the width of the first opening higher than the surface of the first plug material layer is reduced, and the width of the second opening higher than the second plug material layer is reduced.
Optionally, the passivation method includes: introducing passivation gas by adopting a remote plasma process; the parameters of the remote plasma process include: an included angle is formed between the incident direction of the passivation gas and the normal line of the surface of the substrate, and the included angle is larger than 0 degree.
Optionally, the passivation gas comprises: a nitrogen-containing gas comprising nitrogen, ammonia, nitric oxide, or nitrous oxide.
Optionally, the parameters of the first ion implantation process include: and implanting first ions, wherein the relative atomic mass of the first ions is larger than that of one element in the first dielectric layer, the implantation energy range is 1 kilo-electron volt to 100 kilo-electron volts, the dosage range is 1E10 atom per square centimeter to 1E100 atom per square centimeter, and the cycle number is 1 to 1000.
Optionally, the material of the first dielectric layer contains silicon element and oxygen element, and the relative atomic mass of the first ions is greater than the relative atomic mass of the silicon element.
Optionally, the first ions include: germanium ions or tin ions.
Optionally, the first plug material layer and the second plug material layer are made of the same material; the materials of the first and second plug material layers include: a metal comprising copper, tungsten, aluminum, titanium nitride, or tantalum.
Optionally, the parameters of the first selective chemical vapor deposition process include: the gas introduced comprises WF6And H2The WF6In the flow range of 0 ml/min to 1000 ml/min, said H2The flow rate of (a) is in the range of 0 ml/min to 10000 ml/min and the pressure is in the range of 0 torr to 100 torr.
Optionally, the method further includes: and after the passivation treatment and before the second selective chemical vapor deposition process, cleaning treatment is carried out.
Optionally, the method of cleaning treatment comprises: and introducing reducing gas to enable the reducing gas to react with impurities on the surfaces of the first plug material layer and the second plug material layer.
Optionally, the third plug material layer and the fourth plug material layer are made of the same material; the material of the third and fourth plug material layers comprises: a metal comprising copper, tungsten, aluminum, titanium nitride, or tantalum.
Optionally, the second selective chemical vapor deposition process parameters include: the gas introduced comprises WF6And H2The WF6In the flow range of 0 ml/min to 1000 ml/min, said H2The flow rate of (a) is in the range of 0 ml/min to 10000 ml/min and the pressure is in the range of 0 torr to 100 torr.
Optionally, the method further includes: forming an adhesion layer on the surfaces of the first dielectric layer, the third plug material layer and the fourth plug material layer; forming a fifth plug material layer on the surface of the adhesion layer; and flattening the fifth plug material layer, the adhesion layer, the third plug material layer and the fourth plug material layer until the fifth plug material layer, the adhesion layer, the third plug material layer and the fourth plug material layer are flush with or lower than the surface of the second plug material layer, forming a first plug in the first opening, and forming a second plug in the second opening.
Optionally, the method further includes: after the third plug material layer and the fourth plug material layer are formed and before the adhesion layer is formed, second ion implantation is carried out on the first dielectric layer, and gaps between the first plug material layer, the second plug material layer, the third plug material layer and the fourth plug material layer and the first dielectric layer are reduced.
Optionally, the process parameters of the second ion implantation include: and injecting second ions, wherein the relative atomic mass of the second ions is larger than that of one element in the first dielectric layer material, the injection energy is in a range of 1 kilo-electron volt to 100 kilo-electron volt, the dosage is in a range of 1E10 atom per square centimeter to 1E100 atom per square centimeter, and the cycle number is in a range of 1 to 1000.
Optionally, a material of the first dielectric layer includes silicon element and oxygen element, and a relative atomic mass of the second ions is greater than a relative atomic mass of the silicon element.
Optionally, the second ions include: germanium ions or tin ions.
Optionally, the substrate comprises: the first conducting layer and the second conducting layer are positioned in the second dielectric layer, and the first conducting layer and the second conducting layer are exposed out of the second dielectric layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the forming method of the semiconductor structure provided by the technical scheme of the invention, after the first plug material layer and the second plug material layer are formed, the first plug material layer and the second plug material layer are passivated, and the passivation treatment can reduce the rate of forming a film layer by adopting a second selective chemical vapor deposition process. Since the top surface of the first plug material layer within the first opening is higher than the top surface of the second plug material layer within the second opening, the passivation process causes a greater degree of passivation to the first plug material layer than to the second plug material layer, so that the rate of forming the third plug material layer is less than that of the fourth plug material layer, thereby reducing the need for the first selective chemical vapor deposition process, a difference in the rate of formation of the film layer within the first opening and the second opening such that the overall thickness of the first plug material layer and the third plug material layer formed within the first opening, close to the overall thickness of the second plug material layer and the fourth plug material layer formed in the second opening, therefore, the appearance uniformity of the film formed in the first opening and the film formed in the second opening is improved, and the performance of the formed semiconductor structure is improved.
Further, before the passivation treatment, the method further comprises: and performing first ion implantation on the first dielectric layer exposed by the first opening and the second opening, wherein the implanted first ions can replace atomic positions in crystal lattices of the material of the first dielectric layer, and the relative atomic mass of the first ions is greater than that of one element in the first dielectric layer, so that the film layer after the first ion implantation treatment is expanded, and the width of the first opening which is higher than the surface of the first plug material layer and the width of the second opening which is higher than the surface of the second plug material layer can be reduced. And the top surface of the first plug material layer is higher than the top surface of the second plug material layer, the height of the first opening exposed by the first plug material layer is smaller than the height of the second opening exposed by the second plug material layer, and the height of the first opening with reduced width is smaller than the height of the second opening with reduced width by the first ion implantation, so that the passivation effect of the passivation treatment on the first plug material layer and the second plug material layer is enhanced, the difference of the subsequent film forming rates in the first opening and the second opening is increased, the uniformity of the film forms in the first opening and the second opening is improved, and the performance of the formed semiconductor structure is improved.
Further, after forming the third plug material layer and the second plug layer, the method further includes: and carrying out second ion implantation on the first dielectric layer. The injected second ions can replace the atomic position in the crystal lattice of the first medium layer material, and the relative atomic mass of the second ions is larger than that of one element in the first medium layer, so that the film layer after the second ion injection treatment expands, gaps among the first plug material layer, the second plug material layer, the third plug material layer, the fourth plug material layer and the first medium layer can be reduced, the loss of a grinding solution adopted in a subsequent planarization process to the first conducting layer and the second conducting layer is reduced, and the performance of the formed semiconductor structure is improved.
Furthermore, through cleaning treatment, the introduced reducing gas reacts with impurities on the surfaces of the first plug material layer and the second plug material layer, so that surface impurities can be removed, the surface smoothness of the first plug material layer and the second plug material layer is improved, and the quality of a film layer formed by a second selective chemical vapor deposition process is improved.
Drawings
FIGS. 1-4 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 5 to 14 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
It should be noted that "surface" and "upper" in the present specification are used to describe a relative positional relationship in space, and are not limited to direct contact or not.
First, the reason for the poor performance of the conventional semiconductor structure will be described in detail with reference to the accompanying drawings, and fig. 1 to 4 are schematic structural diagrams of steps of a method for forming the conventional semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 has a first conductive layer 111 and a second conductive layer 112 separated from each other, the substrate 100 has a dielectric layer 120 thereon, the dielectric layer 120 has a first opening 121 and a second opening 122 therein, the first opening 121 exposes the first conductive layer 111, and the second opening 122 exposes the second conductive layer 112.
Referring to fig. 2, a first selective chemical vapor deposition process is performed to form a first plug material layer 131 in the first opening 121, form a second plug material layer 132 in the second opening 122, and fill the first opening 121 with the first plug material layer 131.
Referring to fig. 3, a second selective chemical vapor deposition process is employed to form a third plug material layer 141 on the surface of the first plug material layer 131, and a fourth plug material layer 142 on the surface of the second plug material layer 132, wherein the second opening 122 is filled with the fourth plug material layer 142.
Referring to fig. 4, an adhesion layer (not shown) is formed on the surface of the dielectric layer 120, the surface of the third plug material layer 141, and the surface of the fourth plug material layer 142; forming a fifth plug material layer (not shown in the figure) on the surface of the adhesion layer; and planarizing the third plug material layer 141, the fourth plug material layer 142, the adhesion layer, and the fifth plug material layer until the surface of the dielectric layer 120 is exposed.
In the method, the selective chemical vapor deposition process can grow layer by layer on the exposed surfaces of the first conductive layer 111 and the second conductive layer 112, and meanwhile, the selective chemical vapor deposition process cannot grow on the surface of the dielectric layer 120, so that the formed film layer has good quality and good density, holes are not easy to generate, and an adhesion layer does not need to be formed in advance, thereby being beneficial to reducing the contact resistance.
However, due to the different amounts of the byproducts remaining in the first opening 121 and the second opening 122, the uniformity of the rates of the first plug material layer 131 and the second plug material layer 132 formed by the selective chemical vapor deposition process is poor, so that while the first plug material layer 131 in the first opening 121 fills the first opening 121, the film layer in the second opening 122 does not fill the second opening 122, and the first plug material layer 131 with the faster growth rate is easily closed at the top of the second opening 122 in advance, which results in the generation of a void a in the second opening 122, and thus the contact resistance of the conductive structure in the second opening 122 is relatively large.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: and passivating the first plug material layer and the second plug material layer, wherein the passivating treatment can reduce the rate of forming a film layer by adopting a second selective chemical vapor deposition process, so that the overall thickness of the first plug material layer and the third plug material layer formed in the first opening is close to the overall thickness of the second plug material layer and the fourth plug material layer formed in the second opening, the uniformity of the shapes of the film layer formed in the first opening and the film layer formed in the second opening is improved, and the improvement of the performance of the formed semiconductor structure is facilitated.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 14 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 5, a substrate 200 is provided, in which the substrate 200 has a first conductive layer 211 and a second conductive layer 212 separated from each other.
In this embodiment, the substrate 200 includes: a substrate (not shown), and a second dielectric layer (not shown) on the surface of the substrate, wherein the first conductive layer 211 and the second conductive layer 212 are located in the second dielectric layer, and the second dielectric layer exposes the first conductive layer 211 and the second conductive layer 212.
The material of the first conductive layer 211 includes a metal including: copper, tungsten, aluminum, titanium nitride, or tantalum; the material of the second conductive layer 212 includes: a metal comprising copper, tungsten, aluminum, titanium nitride, or tantalum.
In this embodiment, the first conductive layer 211 and the second conductive layer 212 are made of the same material and are both cobalt.
The material of the substrate comprises: silicon, germanium, silicon on insulator or germanium on insulator. In this embodiment, the substrate is made of silicon.
The second dielectric layer is made of an insulating material and comprises: one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon nitride boride, silicon oxycarbonitride or silicon oxynitride. In this embodiment, the second dielectric layer is made of silicon oxide.
Referring to fig. 6, a first dielectric layer 220 is formed on the substrate 200, the first dielectric layer 220 has a first opening 221 and a second opening 222 therein, the first opening 221 exposes the first conductive layer 211, and the second opening 222 exposes the second conductive layer 212.
The first dielectric layer 220 is made of an insulating material, and includes: one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon nitride boride, silicon oxycarbonitride and silicon oxynitride. In this embodiment, the first dielectric layer 220 is made of silicon oxide.
It should be noted that, in this embodiment, the first opening 221 is further located in the first conductive layer 211, and a width of a portion, located in the first conductive layer 211, of the first opening 221 is greater than a width of a portion, located in the first dielectric layer 220, of the first opening 221, that is, the first opening 221 has a protruding portion, and the protruding portion can play a certain role in blocking a polishing solution used in a planarization process in a process of filling a material in the first opening 221 and performing the planarization process, so that etching damage of the polishing solution to the first conductive layer 211 at the bottom of the first opening 221 is reduced, and performance of a formed semiconductor structure is further improved.
Similarly, in this embodiment, the second opening 222 is further located in the second conductive layer 212, and a width of a part of the second opening 222 located in the second conductive layer 212 is greater than a width of a part of the second opening located in the first dielectric layer 220, and similarly, the second opening 222 has a protruding portion, and the protruding portion can play a certain role in blocking a polishing solution used in a planarization process in a process of filling a material in the subsequent second opening 222 and performing the planarization process, so that etching damage of the polishing solution to the second conductive layer 212 at the bottom of the second opening 222 is reduced, and further, the performance of the formed semiconductor structure is favorably improved.
Referring to fig. 7, a first selective chemical vapor deposition process is employed to form a first plug material layer 231 in the first opening 221 and a second plug material layer 232 in the second opening 222, wherein a top surface of the first plug material layer 221 is higher than a top surface of the second plug material layer 232.
The first plug material layer 231 provides material for forming a first plug in the first opening 221; the second plug material layer 232 provides material for a subsequent second plug formation within the second opening 222.
The first plug material layer 231 and the second plug material layer 232 are made of the same material; the materials of the first plug material layer 231 and the second plug material layer 232 include: a metal comprising copper, tungsten, aluminum, titanium nitride, or tantalum. In this embodiment, the first plug material layer 231 and the second plug material layer 232 are both made of tungsten.
The parameters of the first selective chemical vapor deposition process include: the gas introduced comprises WF6And H2The WF6In the flow range of 0 ml/min to 1000 ml/min, said H2The flow rate of (a) is in the range of 0 ml/min to 10000 ml/min and the pressure is in the range of 0 torr to 100 torr.
By adopting the first selective chemical vapor deposition process, the film layers for forming the first plug material layer 231 and the second plug material layer 232 have good quality and density, are not easy to generate holes, and do not need to form an adhesion layer, thereby being beneficial to reducing the contact resistance.
It should be noted that the first dielectric layer 220 includes a region to be implanted a, and the region to be implanted a is to be implanted with first ions by a subsequent first ion implantation process.
Referring to fig. 8, a first ion implantation is performed on the first dielectric layer 220 exposed by the first opening 221 and the second opening 222, so as to reduce the width of the first opening 221 above the surface of the first plug material layer 231 and reduce the width of the second opening 222 above the surface of the second plug material layer 232.
It should be noted that the first dielectric layer 220 includes a region to be implanted a, the first ion implantation makes the region to be implanted a form an implanted region B, and the width of the implanted region B is greater than the width of the region to be implanted a.
The width refers to a dimension in a direction perpendicular to a sidewall of the first opening 221 or the second opening 222.
The parameters of the first ion implantation process include: and implanting first ions, wherein the relative atomic mass of the first ions is larger than that of one element in the first dielectric layer, the implantation energy range is 1 kilo-electron volt to 100 kilo-electron volts, the dosage range is 1E10 atom per square centimeter to 1E100 atom per square centimeter, and the cycle number is 1 to 1000.
Because the implanted first ions can replace atomic positions in the crystal lattice of the material of the first dielectric layer 220, and the relative atomic mass of the first ions is greater than the relative atomic mass of one element in the first dielectric layer 220, the film layer after the first ion implantation treatment is expanded, that is, the size of the region a to be implanted of the first dielectric layer 220 is increased after the first ions are implanted, so that the width of the first opening 221 higher than the surface of the first plug material layer 231 and the width of the second opening 222 higher than the surface of the second plug material layer 232 can be reduced, that is, the width of the implantation region B is greater than the width of the region a to be implanted. Moreover, the top surface of the first plug material layer 231 is higher than the top surface of the second plug material layer 232, and then the height of the first opening 221 which is higher than the surface of the first plug material layer 231 is smaller than the height of the second opening 222 which is higher than the surface of the second plug material layer, and the first ion implantation makes the height of the width reduction of the first opening 221 smaller than the height of the width reduction of the second opening 222, so as to be beneficial to enhancing the passivation effect of the subsequent passivation treatment on the first plug material layer 231 and the second plug material layer 232, and increasing the difference of the film forming rates in the first opening 221 and the second opening 222, so as to be beneficial to improving the film forming uniformity in the first opening 221 and the film forming uniformity in the second opening 222, and to improving the performance of the formed semiconductor structure.
The dose range of the first ion implantation process is 1E10 atoms per square centimeter to 1E12 atoms per square centimeter, and the first ion implantation process has a higher dose range, which is beneficial to fully expanding the implantation region of the first dielectric layer 220, so that the degree of reduction of the first opening 221 exposed by the first plug material layer 231 is larger, and the degree of reduction of the second opening 222 exposed by the second plug material layer 232 is larger, thereby improving the uniformity of the film profile formed in the first opening 221 and the film profile formed in the second opening 222.
In this embodiment, the material of the first dielectric layer 220 includes silicon element and oxygen element, and the relative atomic mass of the first ions is greater than that of silicon element. The first ions are: germanium ions. In other embodiments, the first ion may also be a tin ion.
Referring to fig. 9, after the first ion implantation, a passivation process is performed on the first plug material layer 231 and the second plug material layer 232.
The passivation treatment method comprises the following steps: introducing passivation gas by adopting a remote plasma process; the parameters of the remote plasma process include: an included angle is formed between the incident direction of the passivation gas and the normal line of the surface of the substrate, and the included angle is larger than 0 degree.
The passivation gas includes: a nitrogen-containing gas comprising nitrogen, ammonia, nitric oxide, or nitrous oxide. In this embodiment, the passivation gas is nitrogen.
By performing passivation on the first plug material layer 231 and the second plug material layer 232, the passivation can reduce the rate of forming a film layer by a second selective chemical vapor deposition process. Since the top surface of the first plug material layer 231 located in the first opening 221 is higher than the top surface of the second plug material layer 232 located in the second opening 222, the passivation process passivates the first plug material layer 231 more than the second plug material layer 232, so that the rate of forming the third plug material layer is lower than that of the fourth plug material layer.
In other embodiments, the first ion implantation process may not be performed, and after the first plug material layer and the second plug material layer are formed, the first plug material layer and the second plug material layer may be passivated.
Referring to fig. 10, after the passivation process, a cleaning process is performed.
The method of cleaning treatment comprises: and introducing reducing gas to enable the reducing gas to react with impurities on the surfaces of the first plug material layer and the second plug material layer.
The reducing gas comprises hydrogen.
Through cleaning treatment, the introduced reducing gas reacts with impurities on the surfaces of the first plug material layer 231 and the second plug material layer 232, so that surface impurities can be removed, the surface smoothness of the first plug material layer 231 and the second plug material layer 232 is improved, and the quality of a film layer formed by a second selective chemical vapor deposition process is improved.
In other embodiments, the cleaning process may not be performed after the passivation process.
Referring to fig. 11, a second selective chemical vapor deposition process is employed to form a third plug material layer 241 on the surface of the first plug material layer 231 in the first opening 221, so that the third plug material layer 241 fills the first opening 221, form a fourth plug material layer 242 on the surface of the second plug material layer 232 in the second opening 222, and make the fourth plug material layer 242 fill the second opening 222, and the rate of forming the third plug material layer 241 is less than the rate of forming the fourth plug material layer 242.
The third plug material layer 241 provides material for the subsequent formation of a first plug in the first opening 221; the fourth plug material layer 242 provides material for a second plug to be subsequently formed within the second opening 222.
The second selective chemical vapor deposition process parameters include: the gas introduced comprises WF6And H2The WF6In the flow range of 0 ml/min to 1000 ml/min, said H2The flow rate of (a) is in the range of 0 ml/min to 10000 ml/min and the pressure is in the range of 0 torr to 100 torr.
The third plug material layer 241 and the fourth plug material layer 242 are made of the same material; the materials of the third and fourth plug material layers 241, 242 include: a metal comprising copper, tungsten, aluminum, titanium nitride, or tantalum. In this embodiment, the material of the third plug material layer 241 and the fourth plug material layer 242 is tungsten.
By adopting the first selective chemical vapor deposition process, the film layers for forming the first plug material layer 231 and the second plug material layer 232 have good quality and density, are not easy to generate holes, and do not need to form an adhesion layer, thereby being beneficial to reducing the contact resistance. Because the passivation process can reduce the rate of forming the film layer by the selective chemical vapor deposition process, and the degree of the passivation effect on the first plug material layer 231 is greater than the degree of the passivation effect on the second plug material layer 232, so that the rate of forming the third plug material layer 241 by the second selective chemical vapor deposition process is less than the rate of forming the fourth plug material layer 242, thereby reducing the difference of the film layer rates formed in the first opening 221 and the second opening 222 by the first selective chemical vapor deposition process, so that the overall thickness of the first plug material layer 231 and the third plug material layer 241 formed in the first opening 221 is close to the overall thickness of the second plug material layer 232 and the fourth plug material layer 242 formed in the second opening 222, thereby improving the film layer formed in the first opening 221 and the film layer formed in the second opening 222 in the uniformity of the film layer, the method is favorable for improving the performance of the formed semiconductor structure.
Referring to fig. 12, after forming the third plug material layer 241 and the fourth plug material layer 242, a second ion implantation is performed on the first dielectric layer 220 to reduce gaps between the first plug material layer 231, the second plug material layer 232, the third plug material layer 241, and the fourth plug material layer 242 and the first dielectric layer 220.
The process parameters of the second ion implantation comprise: and injecting second ions, wherein the relative atomic mass of the second ions is larger than that of one element in the first dielectric layer material, the injection energy is in a range of 1 kilo-electron volt to 100 kilo-electron volt, the dosage is in a range of 1E10 atom per square centimeter to 1E100 atom per square centimeter, and the cycle number is in a range of 1 to 1000.
Because the injected second ions can replace the atomic position in the crystal lattice of the material of the first dielectric layer 220, and the relative atomic mass of the second ions is greater than the relative atomic mass of one element in the first dielectric layer 220, the film layer after the second ion injection treatment expands, so that gaps among the first plug material layer 231, the second plug material layer 232, the third plug material layer 241, the fourth plug material layer 242 and the first dielectric layer 220 can be reduced, the loss of a grinding solution adopted in a subsequent planarization process to the first conductive layer 211 and the second conductive layer 212 is favorably reduced, and the performance of the formed semiconductor structure is improved.
By adopting the second ion implantation with the higher implantation energy range, the region of the implanted first dielectric layer 220 can be deep enough, so that the gap between the film layer in the first opening 221 and the first dielectric layer 220 in the whole depth can be reduced, and the gap between the film layer in the second opening 222 and the first dielectric layer 220 in the whole depth can be reduced, thereby ensuring that the loss of the grinding solution adopted in the subsequent planarization process to the first conductive layer 211 and the second conductive layer 212 is effectively reduced, and further improving the performance of the formed semiconductor structure.
In this embodiment, the material of the first dielectric layer 220 includes silicon element and oxygen element, and the relative atomic mass of the second ions is greater than the relative atomic mass of silicon element. The second ions are germanium ions.
In other embodiments, the second ion may also be a tin ion.
In other embodiments, the second ion implantation may not be performed.
Referring to fig. 13, after the second ion implantation, an adhesion layer 251 is formed on the surfaces of the first dielectric layer 220, the third plug material layer 241 and the fourth plug material layer 242; and forming a fifth plug material layer 252 on the surface of the adhesion layer 251.
The adhesion layer 251 is used for better forming the adhesion layer 251 on the surface of the first dielectric layer 220, and the subsequent fifth plug material layer 252 is better adhered to the adhesion layer 251, so that the fifth plug material layer 252 can be better formed on the first dielectric layer 220.
The material of the adhesion layer 251 includes: titanium nitride or tantalum nitride.
By forming the fifth plug material layer 252, the overall surface of the fifth plug material layer 252 is relatively flat, which is beneficial to performing a subsequent planarization process.
The material of the fifth plug material layer 252 includes: a metal comprising copper, tungsten, aluminum, titanium nitride, or tantalum. In this embodiment, the material of the fifth plug material layer 252 is tungsten.
Referring to fig. 14, the fifth plug material layer 252, the adhesion layer 251, the third plug material layer 241 and the fourth plug material layer 242 are planarized until they are flush with or lower than the surface of the second plug material layer 232, so as to form a first plug 261 in the first opening 221 and a second plug 262 in the second opening 222.
In the present embodiment, the planarization process is performed until the surface of the second plug material layer 232 (shown in fig. 7) is flush.
The planarization process includes: and (5) carrying out a chemical mechanical polishing process.
The chemical mechanical polishing process adopts polishing solution.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (19)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a first conducting layer and a second conducting layer which are separated from each other;
forming a first dielectric layer on the substrate, wherein the first dielectric layer is internally provided with a first opening and a second opening, the first opening exposes the first conductive layer, and the second opening exposes the second conductive layer;
forming a first plug material layer in the first opening and a second plug material layer in the second opening by adopting a first selective chemical vapor deposition process, wherein the top surface of the first plug material layer is higher than that of the second plug material layer;
passivating the first plug material layer and the second plug material layer;
after the passivation treatment, a second selective chemical vapor deposition process is adopted, a third plug material layer is formed on the surface of the first plug material layer in the first opening, the third plug material layer is filled in the first opening, a fourth plug material layer is formed on the surface of the second plug material layer in the second opening, the fourth plug material layer is filled in the second opening, and the rate of forming the third plug material layer is less than the rate of forming the fourth plug material layer.
2. The method of forming a semiconductor structure of claim 1, further comprising: after the first plug material layer and the second plug material layer are formed and before the passivation treatment, first ion implantation is carried out on the first dielectric layer exposed by the first opening and the second opening, so that the width of the first opening higher than the surface of the first plug material layer is reduced, and the width of the second opening higher than the second plug material layer is reduced.
3. The method of forming a semiconductor structure of claim 1, wherein the method of passivating comprises: introducing passivation gas by adopting a remote plasma process; the parameters of the remote plasma process include: an included angle is formed between the incident direction of the passivation gas and the normal line of the surface of the substrate, and the included angle is larger than 0 degree.
4. The method of forming a semiconductor structure of claim 3, wherein the passivating gas comprises: a nitrogen-containing gas comprising nitrogen, ammonia, nitric oxide, or nitrous oxide.
5. The method of forming a semiconductor structure of claim 2, wherein the parameters of the first ion implantation process comprise: and implanting first ions, wherein the relative atomic mass of the first ions is larger than that of one element in the first dielectric layer, the implantation energy range is 1 kilo-electron volt to 100 kilo-electron volts, the dosage range is 1E10 atom per square centimeter to 1E100 atom per square centimeter, and the cycle number is 1 to 1000.
6. The method of claim 5, wherein the material of the first dielectric layer comprises elemental silicon and elemental oxygen, and wherein the relative atomic mass of the first ions is greater than the relative atomic mass of elemental silicon.
7. The method of forming a semiconductor structure of claim 6, wherein the first ions comprise: germanium ions or tin ions.
8. The method of forming a semiconductor structure of claim 1, wherein said first plug material layer and said second plug material layer are the same material; the materials of the first and second plug material layers include: a metal comprising copper, tungsten, aluminum, titanium nitride, or tantalum.
9. The method of claim 1, wherein the parameters of the first selective chemical vapor deposition process comprise: the gas introduced comprises WF6And H2The WF6In the flow range of 0 ml/min to 1000 ml/min, said H2The flow rate of (a) is in the range of 0 ml/min to 10000 ml/min and the pressure is in the range of 0 torr to 100 torr.
10. The method of forming a semiconductor structure of claim 1, further comprising: and after the passivation treatment and before the second selective chemical vapor deposition process, cleaning treatment is carried out.
11. The method of forming a semiconductor structure of claim 10, wherein the cleaning process comprises: and introducing reducing gas to enable the reducing gas to react with impurities on the surfaces of the first plug material layer and the second plug material layer.
12. The method of forming a semiconductor structure of claim 1, wherein the third plug material layer and the fourth plug material layer are the same material; the material of the third and fourth plug material layers comprises: a metal comprising copper, tungsten, aluminum, titanium nitride, or tantalum.
13. The method of forming a semiconductor structure of claim 1, wherein the second selective chemical vapor deposition process parameters comprise: the gas introduced comprises WF6And H2The WF6In the flow range of 0 ml/min to 1000 ml/min, said H2The flow rate of (a) is in the range of 0 ml/min to 10000 ml/min and the pressure is in the range of 0 torr to 100 torr.
14. The method of forming a semiconductor structure of claim 1, further comprising: forming an adhesion layer on the surfaces of the first dielectric layer, the third plug material layer and the fourth plug material layer; forming a fifth plug material layer on the surface of the adhesion layer; and flattening the fifth plug material layer, the adhesion layer, the third plug material layer and the fourth plug material layer until the fifth plug material layer, the adhesion layer, the third plug material layer and the fourth plug material layer are flush with or lower than the surface of the second plug material layer, forming a first plug in the first opening, and forming a second plug in the second opening.
15. The method of forming a semiconductor structure of claim 14, further comprising: after the third plug material layer and the fourth plug material layer are formed and before the adhesion layer is formed, second ion implantation is carried out on the first dielectric layer, and gaps between the first plug material layer, the second plug material layer, the third plug material layer and the fourth plug material layer and the first dielectric layer are reduced.
16. The method of forming a semiconductor structure of claim 15, wherein the process parameters of the second ion implantation comprise: and injecting second ions, wherein the relative atomic mass of the second ions is larger than that of one element in the first dielectric layer material, the injection energy is in a range of 1 kilo-electron volt to 100 kilo-electron volt, the dosage is in a range of 1E10 atom per square centimeter to 1E100 atom per square centimeter, and the cycle number is in a range of 1 to 1000.
17. The method of claim 16, wherein the material of the first dielectric layer comprises elemental silicon and elemental oxygen, and wherein the relative atomic mass of the second ions is greater than the relative atomic mass of elemental silicon.
18. The method of forming a semiconductor structure of claim 17, wherein the second ions comprise: germanium ions or tin ions.
19. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: the first conducting layer and the second conducting layer are positioned in the second dielectric layer, and the first conducting layer and the second conducting layer are exposed out of the second dielectric layer.
CN202011263291.5A 2020-11-12 2020-11-12 Method for forming semiconductor structure Pending CN114496907A (en)

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