CN114496735A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN114496735A
CN114496735A CN202011153840.3A CN202011153840A CN114496735A CN 114496735 A CN114496735 A CN 114496735A CN 202011153840 A CN202011153840 A CN 202011153840A CN 114496735 A CN114496735 A CN 114496735A
Authority
CN
China
Prior art keywords
layer
mask
side wall
sidewall
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011153840.3A
Other languages
Chinese (zh)
Inventor
赵海
盛伟
张婷
赵君红
张彬
张继伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN202011153840.3A priority Critical patent/CN114496735A/en
Publication of CN114496735A publication Critical patent/CN114496735A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate comprising an adjacent device area and a pseudo-pattern area, wherein a device mask side wall is arranged on the substrate in the device area, and a pseudo-mask side wall is arranged on the substrate in the pseudo-pattern area; forming a filling layer on the substrate to cover the device mask side wall and the pseudo mask side wall; etching the filling layer and the pseudo mask side wall with partial height in the pseudo pattern area to form a residual pseudo mask side wall, wherein the residual pseudo mask side wall and the filling layer enclose a groove; forming a side wall protection layer on the side wall of the groove; etching to remove the residual pseudo mask side wall; removing the side wall protection layer; removing the filling layer; and etching the substrate by taking the device mask side wall as a mask. According to the invention, the pseudo mask side wall is removed by two etching steps, and the second etching step is carried out after the side wall protective layer is formed, so that the probability of the false etching of the device mask side wall is reduced under the protection action of the side wall protective layer, and the device mask side wall has lower line width roughness, thereby improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
Semiconductor technology continues to step toward smaller process nodes driven by moore's law. With the continuous progress of semiconductor technology, the functions of devices are becoming more powerful, but the difficulty of semiconductor manufacturing is increasing. The photolithography (photolithography) technology is the most critical production technology in the semiconductor manufacturing process, and with the continuous decrease of the semiconductor process nodes, the existing light source photolithography technology cannot meet the requirements of the semiconductor manufacturing.
When moore's law continues to be extended forward and the step is not reversible, self-aligned double patterning (SADP) method becomes a patterning method favored in recent years, which can increase the density of patterns formed on a substrate and further reduce the pitch (pitch) between two adjacent patterns, thereby making the photolithography process overcome the limit of the photolithography resolution.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising an adjacent device area and a pseudo-pattern area, wherein a device mask side wall is formed on the substrate of the device area, and a pseudo-mask side wall is formed on the substrate of the pseudo-pattern area; forming a filling layer on the substrate, wherein the filling layer covers the device mask side wall and the pseudo mask side wall; etching the filling layer and the pseudo mask side wall with partial height in the pseudo pattern area to form a residual pseudo mask side wall, wherein the residual pseudo mask side wall and the filling layer enclose a groove; forming a side wall protection layer on the side wall of the groove; after the side wall protective layer is formed, etching to remove the residual pseudo mask side wall; removing the side wall protection layer; removing the filling layer after removing the side wall protection layer; and after removing the filling layer, etching the substrate by taking the device mask side wall as a mask.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate including a device region and a dummy pattern region adjacent to each other; the device mask side wall is positioned on the substrate of the device area and used as a mask for etching the substrate; the residual pseudo mask side wall to be etched and removed is positioned on the substrate of the pseudo pattern area, and the top of the residual pseudo mask side wall is lower than that of the device mask side wall; the filling layer is positioned on the substrate, covers the device mask side wall and exposes the top of the residual pseudo mask side wall, and the filling layer and the residual pseudo mask side wall enclose a groove; and the side wall protection layer is positioned on the side wall of the groove.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the forming method provided by the embodiment of the invention, firstly, a filling layer and a pseudo mask side wall with partial height are etched in a pseudo pattern area to form a residual pseudo mask side wall, the residual pseudo mask side wall and the filling layer enclose a groove, then, a side wall protective layer is formed on the side wall of the groove, and after the side wall protective layer is formed, the residual pseudo mask side wall is removed by etching; compared with the scheme of etching and removing the pseudo mask side wall in the same etching step, the embodiment of the invention can remove the pseudo mask side wall by etching twice, and carries out a second etching step after forming the side wall protective layer, under the protection action of the side wall protective layer, the transverse etching of the etching process on the side wall of the groove can be reduced in the process of etching and removing the residual pseudo mask side wall, so that the probability of mistaken etching of the device mask side wall adjacent to the pseudo mask side wall is reduced, the device mask side wall is correspondingly enabled to have lower Line Width Roughness (LWR), the line width uniformity of the device mask side wall is improved, and the substrate is etched by taking the device mask side wall as the mask subsequently, so that the pattern transmission precision is improved, and the improvement of the line width uniformity of a target pattern formed after etching the substrate is correspondingly facilitated, The line width roughness of the target pattern is reduced, and the performance of the semiconductor structure is improved.
In the alternative scheme, after the residual pseudo mask side wall is removed by etching, a sacrificial layer is formed on the substrate exposed by the filling layer before the side wall protection layer is removed, the sacrificial layer exposes the side wall protection layer, the sacrificial layer can play a role in protecting the substrate in the process of removing the side wall protection layer, the loss probability of the substrate in the process of removing the side wall protection layer is reduced, and correspondingly, after the substrate is etched by taking the device mask side wall as a mask, the line width uniformity of the formed target pattern can be improved, the line width roughness of the target pattern is reduced, and the pitch walking (namely parity effect) problem of the target pattern is improved.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 4 to fig. 13 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The performance of semiconductor structures currently needs to be improved. The reason why the performance of a semiconductor structure needs to be improved is analyzed in combination with a method for forming the semiconductor structure.
Fig. 1 to fig. 3 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate (not labeled) is provided, and includes an adjacent device region i and a dummy pattern region ii, and mask sidewalls 50 are formed on the substrate, where the mask sidewalls 50 located in the device region i are used as device mask sidewalls 52, and the mask sidewalls 50 located in the dummy pattern region ii are used as dummy mask sidewalls 51.
As an example, the mask sidewall spacers 50 are formed by a self-aligned double patterning (SADP) process.
In this embodiment, the base includes an initial substrate 10, a buffer layer 20 on the initial substrate 10, and a hard mask material layer 30 on the buffer layer 20. An etching stop layer 40 is further formed on the substrate, and the device mask side wall 52 and the pseudo mask side wall 51 are located on the etching stop layer 40.
Referring to fig. 1 and fig. 2, a cutting process is performed to remove the dummy mask sidewall 51 in a portion of the dummy pattern region ii.
Specifically, the step of the cutting process includes: forming a filling layer 60 on the substrate, wherein the filling layer 60 covers the device mask side wall 52 and the pseudo mask side wall 51; forming a shielding layer 61 on the filling layer 60, wherein an opening 62 is formed in the shielding layer 61, and the opening 62 exposes part of the filling layer 60 in the dummy pattern region ii; with the shielding layer 61 as a mask, etching the filling layer 60 and the pseudo mask sidewall 51 along the opening 62; the barrier layer 61 and the filling layer 60 are removed.
Referring to fig. 3, the cutting process is repeated one or more times to remove the dummy mask sidewall 51 in the remaining dummy pattern region ii.
The subsequent steps further comprise: etching the etching stop layer 40 and the hard mask material layer 30 by taking the device mask side wall 52 as a mask, and patterning the hard mask material layer 30 into a hard mask layer; and etching the buffer layer 20 and the initial substrate 10 by taking the hard mask layer as a mask, and patterning the initial substrate 10 into a substrate and a fin part protruding out of the substrate.
As the feature size of the integrated circuit is continuously reduced, the interval (space) between adjacent mask side walls 50 is continuously reduced, so that in the process of etching the filling layer 60 and the pseudo mask side walls 51 along the openings 62, the time required for etching the pseudo mask side walls 51 is long, and the process for removing the pseudo mask side walls 51 is prone to mis-etching the device mask side walls 52 adjacent to the pseudo mask side walls 51, thereby easily causing the line width roughness of the device mask side walls 52 to increase, the line width uniformity of the device mask side walls 52 to decrease, and particularly when overlay shift (overlay shift) exists in the process of forming the openings 62, the probability of the above problems is higher. Therefore, when the pattern of the device mask sidewall 52 is subsequently transferred to the substrate, accuracy of pattern transfer is easily reduced, for example, the line width accuracy of the fin portion is low, and the line width roughness of the fin portion is high, so that performance of the semiconductor structure is reduced.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising an adjacent device area and a pseudo-pattern area, wherein a device mask side wall is formed on the substrate of the device area, and a pseudo-mask side wall is formed on the substrate of the pseudo-pattern area; forming a filling layer on the substrate, wherein the filling layer covers the device mask side wall and the pseudo mask side wall; etching the filling layer and the pseudo mask side wall with partial height in the pseudo pattern area to form a residual pseudo mask side wall, wherein the residual pseudo mask side wall and the filling layer enclose a groove; forming a side wall protection layer on the side wall of the groove; after the side wall protective layer is formed, etching to remove the residual pseudo mask side wall; removing the side wall protection layer; removing the filling layer after removing the side wall protection layer; and after removing the filling layer, etching the substrate by taking the device mask side wall as a mask.
According to the embodiment of the invention, the pseudo mask side wall is etched and removed through two etching steps, and the second etching step is carried out after the side wall protective layer is formed, so that the lateral etching of the side wall of the groove by an etching process can be reduced in the process of etching and removing the residual pseudo mask side wall under the protection action of the side wall protective layer, thereby reducing the probability of the false etching of the device mask side wall adjacent to the pseudo mask side wall, correspondingly enabling the device mask side wall to have lower line width roughness, and improving the line width uniformity of the device mask side wall.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 4 to 13 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 4, a substrate (not labeled) is provided, and includes a device region i and a dummy pattern region ii that are adjacent to each other, a device mask sidewall 220 is formed on the substrate of the device region i, and a dummy mask sidewall 210 is formed on the substrate of the dummy pattern region ii.
And the substrate is used for forming a target pattern after a subsequent patterning process. In this embodiment, the base includes an initial substrate 100 and a hard mask material layer 120 located on the initial substrate 100, where the initial substrate 100 is used to form a fin portion, that is, the target pattern is a fin portion.
In other embodiments, the base may also include a substrate and a gate material layer on the substrate, where the gate material layer is used to form a gate structure, that is, the target pattern is a gate structure.
In this embodiment, the material of the initial substrate 100 is silicon. In other embodiments, the material of the initial substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the initial substrate may also be other types of bases such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In subsequent processes, a pattern is first defined in the hard mask material layer 120 to form a patterned hard mask layer, and the hard mask layer is used as a mask for etching the initial substrate 100. By transferring the pattern into the hard mask material layer 120 first, and then into the initial substrate 100, it is beneficial to improve the accuracy of the pattern transfer. And in the subsequent planarization process for forming the isolation layer, the top surface of the hard mask layer is used for defining the stop position of the planarization process.
The hard mask material layer 120 is made of a nitrogen-containing material, so that the hardness and the compactness of the hard mask material layer 120 are high. In this embodiment, the material of the hard mask material layer 120 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. These materials have a high degree of compactness and hardness, and the etching selectivity of the material of the initial substrate 100 to the above-mentioned materials is high during the subsequent etching of the initial substrate 100. As an example, the material of the hard mask material layer 120 is silicon nitride.
It is noted that the base further includes a buffer layer 110 between the initial substrate 100 and the hard mask material layer 120. The buffer layer 110 has good adhesion to the hard mask material layer 120, and the buffer layer 110 has good adhesion to the initial substrate 100. Furthermore, the buffer layer 110 is used to provide a stress buffering effect when the hard mask material layer 120 is formed, thereby improving the problem of dislocation generated when the hard mask material layer 120 is formed. In this embodiment, the buffer layer 110 is made of silicon oxide.
The device mask sidewall spacers 220 are used as a mask for subsequent substrate etching. The material of the device mask sidewall spacers 220 may include one or more of silicon oxide, silicon nitride, silicon, titanium oxide, titanium nitride, and tungsten carbide. In this embodiment, the material of the device mask sidewall spacer 220 is silicon nitride.
The pseudo mask sidewall 210 is located on the substrate of the pseudo pattern region ii, the pseudo mask sidewall 210 and the device mask sidewall 220 form a mask sidewall 200 (as shown in fig. 4), and the pattern density of the mask sidewall 200 is improved by forming the pseudo mask sidewall 210, so that in the process of forming the device mask sidewall 220 and the pseudo mask sidewall 210, the etching load effect caused by the pattern density is improved, and further, the line width uniformity of the device mask sidewall 220 is improved. The pseudo mask sidewall 210 and the device mask sidewall 220 are formed in the same step, and therefore, the materials of the pseudo mask sidewall 210 and the device mask sidewall 220 are the same.
In this embodiment, the pseudo mask sidewall 210 and the device mask sidewall 220 are formed by a self-aligned multi-patterning process to increase the density of the target patterns formed on the substrate and further reduce the pitch (pitch) between adjacent target patterns, so that the limit of the photolithography resolution is overcome by the photolithography process. For example, the self-aligned multi-patterning process may be a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.
Specifically, taking the SADP process as an example, the step of forming the device mask sidewall spacers 220 and the dummy mask sidewall spacers 210 includes: forming a core layer (not shown) on a substrate; forming a mask side wall 200 on the side wall of the core layer, wherein the mask side wall 200 located in the device region I is used as a device mask side wall 220, and the mask side wall 200 located in the pseudo-pattern region II is used as a pseudo-mask side wall 210; and removing the core layer. In other embodiments, the material layers corresponding to the pseudo mask sidewall and the device mask sidewall may also be etched directly by using photolithography and etching processes, so as to form the pseudo mask sidewall and the device mask sidewall, respectively. For example, the dummy mask sidewall and the device mask sidewall may be formed using a LELE (photo-etching-photo-etching) process.
It should be further noted that, before forming the device mask sidewall spacers 220 and the dummy mask sidewall spacers 210, the forming method further includes: an etch stop layer 130 is formed on the substrate. Specifically, the etch stop layer 130 is formed on the hard mask material layer 120.
The process for forming the device mask sidewall 220 and the pseudo mask sidewall 210 includes an etching process, and in the etching process, the etching stop layer 130 can define an etching stop position in the etching process, so as to reduce the probability of etching damage to the hard mask material layer 120, thereby reducing the probability of the problem of inconsistent height of the top surface of the hard mask material layer 120, and accordingly, being beneficial to improving the precision of subsequent pattern transfer.
The material of etch stop layer 130 includes one or more of silicon nitride, titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. In this embodiment, the material of the etch stop layer 130 is silicon oxide.
Referring to fig. 5, a filling layer 300 is formed on the substrate (not labeled), and the filling layer 300 covers the device mask sidewall 220 and the dummy mask sidewall 210.
The filling layer 300 is used for protecting the device mask sidewall 220 in the subsequent process of etching the pseudo mask sidewall 210. Moreover, the filling layer 300 is also used to provide a flat surface for the subsequent formation of the shielding layer.
The filling property of the material selected for the filling layer 300 is good, the material is easy to fill in the space between the adjacent mask side walls, the flatness of the filling layer 300 is high, and the filling layer 300 is also easy to etch, so that the process difficulty of etching the filling layer 300 and the process difficulty of subsequently removing the filling layer 300 are reduced. In addition, the material of the filling layer 300 and the material of the device mask sidewall 220 have a high etching selectivity, that is, the probability of damage to the device mask sidewall 220 is low during the etching of the filling layer 300. The material of the filling layer 300 and the material of the etching stop layer 130 also have a high etching selectivity ratio, so that the probability of damage to the etching stop layer 130 is reduced in the process of etching the filling layer 300 or removing the filling layer 300.
Therefore, the material of the filling layer 300 is an organic material. Specifically, the material of the filling layer 300 includes a Spin On Carbon (SOC) material, a bottom anti-reflective coating (BARC) material, a dielectric anti-reflective coating (DARC) material, a deep ultraviolet light absorbing oxide (DUO) material, or an Advanced Patterning Film (APF) material.
In this embodiment, the material of the filling layer 300 is an advanced patterning film material. The subsequent process further comprises: and in the pseudo-pattern region II, etching the filling layer 300 and the pseudo-mask side wall 210 with partial height to form a residual pseudo-mask side wall, wherein the residual pseudo-mask side wall and the filling layer 300 enclose a groove. Because the advanced pattern film material has excellent physical properties, after the groove is formed, the side wall of the groove has lower Line Edge Roughness (LER), the appearance quality of the side wall of the groove is correspondingly improved, and the improvement of the line width uniformity (CDU) of the groove is facilitated.
In this embodiment, the forming method further includes: a shielding layer 310 is formed on the filling layer 300, and an opening 320 is formed in the shielding layer 310 to expose the filling layer 300 in the dummy pattern region ii.
When the filling layer 300 and the pseudo mask sidewall 210 with a partial height are subsequently etched, the blocking layer 310 is used as an etching mask, and the opening 320 defines a region to be etched.
In the present embodiment, the opening 320 is formed in the blocking layer 310 using a LELE (photo-etching-photo-etching) process, thereby enabling a photolithography process to overcome the limit of a photolithography resolution. The LELE process follows the process sequence of photo-etch-photo-etch, whose main principle is: first, a first part of pattern is formed on the first layer of photoresist through exposure and development, then the first part of pattern is transferred into the lower shielding layer 310 through etching, then the second layer of photoresist is spin-coated and a second part of pattern is formed through exposure and development, and finally the second part of pattern is transferred into the lower shielding layer 310 through etching.
In this embodiment, the width of the opening 320 is greater than the width of the pseudo mask sidewall 210 along a direction parallel to the substrate surface and perpendicular to the sidewall of the pseudo mask sidewall 210, so as to increase a process window for forming the opening 320, and easily make the opening 320 located above the pseudo mask sidewall 210.
The difference between the widths of the opening 320 and the dummy mask sidewall 210 is not too small or too large. If the width difference between the opening 320 and the dummy mask sidewall 210 is too small, the problem of offset of the relative position between the opening 320 and the dummy mask sidewall 210 is likely to occur, for example, the problem of serious overlay shift (overlay shift) occurs in the process of forming the opening 320; if the width difference between the opening 320 and the pseudo mask sidewall 210 is too large, the device mask sidewall 220 is also easily exposed after the filling layer 300 is etched when the filling layer 300 and the pseudo mask sidewall 210 with a partial height are subsequently etched along the opening 320, so that the device mask sidewall 220 is erroneously etched. Therefore, in this embodiment, the difference between the widths of the opening 320 and the dummy mask sidewall 210 is 3 nm to 4 nm.
The material of the blocking layer 310 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the shielding layer 310 is silicon oxide. The etch selectivity between silicon nitride and silicon oxide is relatively high. Furthermore, the silicon oxide material is easily removed.
Referring to fig. 6, in the dummy pattern region ii, the filling layer 300 and the dummy mask sidewall 210 with a partial height are etched to form a remaining dummy mask sidewall 230, and the remaining dummy mask sidewall 230 and the filling layer 300 enclose a trench 330.
The trench 330 is used to provide a spatial location for the subsequent formation of a sidewall protection layer.
Subsequently, after forming a sidewall protection layer on the sidewall of the trench 330, the remaining dummy mask sidewall 230 is removed by etching, that is, in this embodiment, the dummy mask sidewall 210 is removed by two etching steps, and after forming the sidewall protection layer, a second etching step is performed, under the protection of the side wall protection layer, in the process of removing the residual pseudo mask side wall 230 by etching, the lateral etching of the etching process to the side wall of the trench 330 can be reduced, thereby reducing the probability of the device mask sidewall 220 adjacent to the pseudo mask sidewall 210 being erroneously etched, correspondingly enabling the device mask sidewall 220 to have a lower line width roughness, improving the line width uniformity of the device mask sidewall 220, since the substrate is subsequently etched by taking the device mask side wall 220 as a mask, the precision of pattern transfer is improved, and the performance of the semiconductor structure is further improved.
In this embodiment, the filling layer 300 and the pseudo mask sidewall 210 with a partial height are etched by using an anisotropic etching process. The longitudinal etching rate of the anisotropic etching process is greater than the lateral etching rate thereof, so that the sidewall morphology quality of the trench 330 is improved, the lateral etching amount is reduced, and the possibility of exposing the device mask sidewall 220 is correspondingly reduced.
It should be noted that, in the step of etching the pseudo mask sidewall 210 with a partial height, the ratio of the longitudinal etching amount of the pseudo mask sidewall 210 to the height of the pseudo mask sidewall 210 is not too small or too large. If the ratio is too small, that is, the height of the remaining pseudo mask sidewall 230 is still large, the time required for subsequently etching the remaining pseudo mask sidewall 230 is long, and during the process of etching the remaining pseudo mask sidewall 230, not only the longitudinal etching is performed, but also a certain amount of lateral etching is generated, so that the probability that the device mask sidewall 220 is erroneously etched is still high; if the ratio is too small, that is, the longitudinal etching amount of the dummy mask sidewall 210 is large in the process of forming the trench 330, and in the process of etching the dummy mask sidewall 210, not only the longitudinal etching is performed, but also a certain lateral etching amount is generated, which also increases the probability that the device mask sidewall 220 is erroneously etched. Therefore, in the present embodiment, in the step of etching the pseudo mask sidewall 210 with a partial height, the longitudinal etching amount of the pseudo mask sidewall 210 is 1/3 to 1/2 of the height of the pseudo mask sidewall 210. The longitudinal direction is a direction perpendicular to the substrate surface, and the transverse direction is a direction parallel to the substrate surface and perpendicular to the sidewalls of the dummy mask sidewall 210.
In this embodiment, in the step of etching the filling layer 300 and the partial height of the pseudo mask sidewall 210, the blocking layer 310 is used as a mask to etch along the opening 320.
It should be noted that, compared with the scheme of repeatedly performing multiple etching processes, where each etching process is used to etch part of the pseudo mask sidewall in the pseudo pattern region, in this embodiment, the filling layer 300 and part of the high pseudo mask sidewall 210 are etched in one etching process, so that the etching uniformity is improved.
It should be further noted that, after the trench 330 is formed, the shielding layer 310 is retained, so that in a subsequent process, the shielding layer 310 protects the top of the filling layer 300, thereby reducing the probability of damaging the top of the filling layer 300, and further reducing the probability of exposing the device mask sidewall 220.
Referring to fig. 7 and 8 in combination, a sidewall protection layer 350 is formed on the sidewalls of the trench 330 (as shown in fig. 8).
In the subsequent process of removing the remaining pseudo mask sidewall 230 by etching, the sidewall protection layer 350 is used for protecting the sidewall of the trench 330, and can reduce the lateral etching of the sidewall of the trench 330 by the process of etching the remaining pseudo mask sidewall 230, thereby reducing the probability that the device mask sidewall 220 adjacent to the remaining pseudo mask sidewall 230 is erroneously etched, correspondingly enabling the device mask sidewall 220 to have lower line width roughness, and improving the line width uniformity of the device mask sidewall 220.
When the remaining pseudo mask sidewall spacers 230 are subsequently etched, the remaining pseudo mask sidewall spacers 230 and the sidewall protection layer 350 have a higher etching selectivity, so that the sidewall protection layer 350 can protect the sidewalls of the trench 330. Specifically, the etching selectivity between the remaining dummy mask sidewall spacers 230 and the sidewall protection layer 350 is greater than 5: 1.
Accordingly, the material of the sidewall protection layer 350 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the sidewall protection layer 350 is silicon oxide. The remaining pseudo mask sidewall 230 is made of silicon nitride, the etching selectivity between silicon nitride and silicon oxide is high, and the silicon oxide material is easily removed.
In addition, in this embodiment, the materials of the sidewall protection layer 350 and the shielding layer 310 are the same, so that the sidewall protection layer 350 and the shielding layer 310 can be removed in the same step.
Note that the thickness of the sidewall protection layer 350 should not be too small, and should not be too large. If the thickness of the sidewall protection layer 350 is too small, in the subsequent etching process for removing the remaining pseudo mask sidewall 230, the protection capability of the sidewall protection layer 350 on the sidewall of the trench 330 is low, and the probability that the device mask sidewall 220 adjacent to the pseudo mask sidewall 210 is erroneously etched is correspondingly high; if the thickness of the sidewall protection layer 350 is too large, the sidewall protection layer 350 may easily block the remaining pseudo mask sidewall 230, thereby affecting the subsequent etching of the remaining pseudo mask sidewall 230. For this reason, in this embodiment, the thickness of the sidewall protection layer 350 is
Figure BDA0002742064550000101
To
Figure BDA0002742064550000102
For example, the sidewall protection layer 350 has a thickness of
Figure BDA0002742064550000103
Or
Figure BDA0002742064550000104
In this embodiment, the step of forming the sidewall protection layer 350 on the sidewall of the trench 330 includes: as shown in fig. 7, a sidewall protection material layer 340 is formed conformally covering the bottom and sidewalls of the trench 330 and the top of the fill layer 300; as shown in fig. 8, the sidewall protection material layer 340 at the bottom of the trench 330 and at the top of the filling layer 300 is removed, and the remaining sidewall protection material layer 340 at the sidewall of the trench 330 is remained as a sidewall protection layer 350. Specifically, the sidewall protection material layer 340 covers the top of the shielding layer 310.
In this embodiment, the sidewall protection material Layer 340 is formed by an Atomic Layer Deposition (ALD) process. The sidewall protection material layer 340 formed by the atomic layer deposition process has good thickness uniformity, and the sidewall protection material layer 340 has good step coverage capability. In other embodiments, a high aspect ratio (high aspect ratio) chemical vapor deposition process may be further used to form the sidewall protection material layer, so that the sidewall protection material layer also has a better step coverage capability.
In this embodiment, the sidewall protection material layer 340 is etched longitudinally along a direction perpendicular to the substrate surface by a maskless anisotropic etching process to form the sidewall protection layer 350. By adopting a maskless etching process, the limitation of the photolithography process on the thickness of the sidewall protection material layer 340 is reduced, so that the thickness of the sidewall protection material layer 340 can be made smaller. Furthermore, the anisotropic etching process has a longitudinal etching rate greater than a lateral etching rate thereof, so that the sidewall protection material layer 340 on the sidewall of the trench 330 is maintained while the sidewall protection material layer 340 on the top of the barrier layer 310 and the bottom of the trench 330 is removed.
The shielding layer 310 is formed on the top of the filling layer 300, so that the shielding layer 310 protects the top of the filling layer 300 during the etching of the sidewall protection material layer 340, thereby reducing the probability of exposing the device mask sidewall 220.
Referring to fig. 9, after the sidewall protection layer 350 is formed, the remaining dummy mask sidewalls 230 are etched away (as shown in fig. 8).
By removing the remaining pseudo mask sidewall spacers 230, the pattern of the remaining pseudo mask sidewall spacers 230 is prevented from being transferred into the substrate. The sidewall protection layer 350 is formed on the sidewall of the trench 330, so that during the process of removing the remaining pseudo mask sidewall 230 by etching, the lateral etching of the sidewall of the trench 330 by the etching process is reduced, and further, the probability that the device mask sidewall 220 adjacent to the pseudo mask sidewall 210 is erroneously etched is reduced.
It should be noted that, under the influence of the etching process, the sidewall of the trench 330 has a certain inclination, and after the remaining pseudo mask sidewall 230 is removed by etching, an included angle between the sidewall of the filling layer 300 exposed by the sidewall protection layer 350 and the substrate surface is also generally an obtuse angle, that is, in a direction from the top of the filling layer 300 to the bottom thereof, a lateral distance between the sidewall of the filling layer 300 exposed by the sidewall protection layer 350 and the device mask sidewall 220 is gradually increased, so that even if the sidewall protection layer 350 only covers the sidewall of the trench 330, the probability that the device mask sidewall 220 is erroneously etched is low in the process of removing the remaining pseudo mask sidewall 230 by etching.
In this embodiment, the remaining pseudo mask sidewall 230 is removed by etching using an anisotropic etching process, so as to reduce the amount of lateral etching, thereby reducing the probability that the device mask sidewall 220 is erroneously etched.
It should be noted that, in the process of etching the remaining pseudo mask sidewall spacers 230, the filling layer 300 at the bottom of the trench 330 is also etched.
Referring collectively to fig. 10 and 11, the sidewall protection layer 350 is removed (as shown in fig. 10).
The sidewall protection layer 350 is removed in preparation for subsequent removal of the fill layer 300.
As an example, the sidewall protection layer 350 is etched away using a wet etching process. The wet etching process has isotropic etching characteristics, which is beneficial to removing the sidewall protection layer 350 cleanly.
It should be noted that the shielding layer 310 (as shown in fig. 10) is formed on the top of the filling layer 300, and therefore, after the etching is performed to remove the remaining dummy mask sidewall spacers 230 (as shown in fig. 8) and before the removing of the filling layer 300, the forming method further includes: the blocking layer 310 is removed.
Specifically, the material of the shielding layer 310 and the sidewall protection layer 350 is the same, and thus, the shielding layer 310 and the sidewall protection layer 350 are removed in the same step, thereby simplifying the process steps.
As shown in fig. 10, in this embodiment, after removing the remaining pseudo mask sidewall spacers 230 by etching and before removing the sidewall protection layer 350, the forming method further includes: a sacrificial layer 360 is formed on the substrate exposed by the filling layer 300, and the sacrificial layer 360 exposes the sidewall protection layer 350.
The sacrificial layer 360 is used for removing the process of the side wall protection layer 350, protecting the substrate, and reducing the probability that the substrate is lost in the process of removing the side wall protection layer 350, and correspondingly, after the substrate is etched by taking the device mask side wall 220 as a mask, the line width uniformity of the formed target pattern can be improved, the line width roughness of the target pattern is reduced, and the pitch walking (namely, parity effect) problem of the target pattern is improved.
The sacrificial layer 360 is made of an organic material, so that the process difficulty of forming the sacrificial layer 360 and the process difficulty of subsequently removing the sacrificial layer 360 are reduced. Also, an organic material is easily filled into a space under the trench 330. Specifically, the material of the sacrificial layer 360 includes a spin-on carbon layer material, a bottom anti-reflective coating material, a dielectric anti-reflective coating material, a deep ultraviolet light absorbing oxide layer material, or an advanced patterning film material.
In this embodiment, the sacrificial layer 360 and the filling layer 300 are made of different materials. The sacrificial layer 360 exposes the sidewall protection layer 350, and therefore, a process for forming the sacrificial layer 360 generally includes a step of back etching, and by making the materials of the sacrificial layer 360 and the filling layer 300 different, damage to the filling layer 300 is reduced in the process of back etching, so that the probability that the device mask sidewall 220 is exposed or is etched by mistake is reduced.
In this embodiment, the sacrificial layer 360 is a carbon-coated material. The carbon-coated material is formed by a spin coating process, and thus, it is easy to fill the material of the sacrificial layer 360 in the space under the trench 330.
Specifically, the step of forming the sacrificial layer 360 includes: forming a sacrificial material layer covering the filling layer 300 and the substrate; and etching back the sacrificial material layer to expose the remaining sacrificial material layer out of the sidewall protection layer 350, wherein the remaining sacrificial material layer 360 serves as a sacrificial layer.
In this embodiment, the sacrificial material layer is etched back by using an anisotropic etching process.
It should be noted that the thickness of the sacrificial layer 360 is not too small, and is not too large. If the thickness of the sacrificial layer 360 is too small, the sacrificial layer 360 has a poor protective effect on the substrate, and the substrate has a relatively high probability of being damaged in the process of removing the sidewall protection layer 350; if the thickness of the sacrificial layer 360 is too large, it is easily contacted with the sidewall protection layer 350, thereby affecting the subsequent removal effect of the sidewall protection layer 350. For this purpose, in this embodiment, the thickness of the sacrificial layer 360 is
Figure BDA0002742064550000131
To
Figure BDA0002742064550000132
For example, the sacrificial layer 360 has a thickness of
Figure BDA0002742064550000133
Or
Figure BDA0002742064550000134
Referring to fig. 12, after removing the sidewall protection layer 350 (shown in fig. 10), the filling layer 300 (shown in fig. 11) is removed.
By removing the filling layer 300, preparation is made for subsequently etching the substrate by using the device mask sidewall spacers 220 as masks.
As an example, the material of the filling layer 300 is an advanced patterning film material, and therefore, the filling layer 300 is removed by an ashing process.
In this embodiment, after removing the sidewall protection layer 350, the forming method further includes: the sacrificial layer 360 is removed (as shown in fig. 11) in preparation for subsequent etching of the substrate.
As an example, the material of the sacrificial layer 360 is a carbon-coated layer material, and therefore, the sacrificial layer 360 is removed by an ashing process.
In this embodiment, the material of the filling layer 300 and the sacrificial layer 360 is organic material, so that the filling layer 300 and the sacrificial layer 360 are removed in the same ashing step, thereby simplifying the process steps.
Referring to fig. 13, after removing the filling layer 300 (shown in fig. 11) and the sacrificial layer 360 (shown in fig. 11), the substrate is etched by using the device mask sidewall spacers 220 as a mask.
The pattern of the device mask sidewall spacer 220 is transferred into the substrate, thereby forming a target pattern. The device mask side wall 220 has low line width roughness, and the line width uniformity of the device mask side wall 220 is high, so that the precision of pattern transfer is improved, the line width uniformity of a formed target pattern is correspondingly improved, the line width roughness of the target pattern is reduced, the pitch walking (namely parity effect) problem of the target pattern is improved, and the performance of a semiconductor structure is further improved.
Specifically, the step of etching the substrate with the device mask sidewall spacers 220 as the mask includes: the hard mask material layer 120 is etched using the device mask sidewall spacers 220 as a mask (as shown in fig. 12), forming a hard mask layer 125. The hard mask layer 125 is used as a mask for subsequent etching of the initial substrate 100 (shown in fig. 12).
Correspondingly, the forming method further comprises the following steps: and etching the initial substrate 100 by using the hard mask layer 125 as a mask to form a substrate 400 and a fin 410 protruding from the substrate 400. That is, the target pattern is the fin 410.
In this embodiment, the etching stop layer 130 is formed on the hard mask material layer 120, and the buffer layer 110 is formed between the hard mask material layer 120 and the initial substrate 100, so that the etching stop layer 130 is etched before the etching of the hard mask material layer 120, and the buffer layer 110 is etched before the etching of the initial substrate 100.
In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is adopted to sequentially etch the etch stop layer 130, the hard mask material layer 120, the buffer layer 110, and the initial substrate 100. The dry etching process has anisotropic etching characteristics, which is beneficial to improving the appearance quality and the dimensional accuracy of the fin portion 410, and in the process of the dry etching process, the stop layer 130, the hard mask material layer 120, the buffer layer 110 and the initial substrate 100 can be etched in the same etching equipment in sequence by adjusting etching gas and etching parameters, so that the process is simple and a machine table does not need to be converted.
In this embodiment, the initial substrate 100 is an integral structure, so that the initial substrate 100 with a certain thickness is etched, the remaining initial substrate 100 is used as the substrate 400, the protrusion on the substrate 400 is used as the fin 410, the fin 410 and the substrate 400 are integral structures, and the fin 410 and the substrate 400 are made of the same material.
It should be noted that the height of the dummy mask sidewall 210 is usually greater than the thickness of the hard mask material layer 120, so that the dummy mask sidewall 210 is easily removed by two etching steps, and the process has high feasibility of implementation.
In other embodiments, according to actual conditions, the patterns of the device mask sidewall and the dummy mask sidewall may also be transferred to the hard mask material layer, after the first hard mask layer corresponding to the device mask sidewall and the second hard mask layer corresponding to the dummy mask sidewall are formed, the second hard mask layer is removed through two etching steps, and a step of forming a sidewall protection layer is provided between the two etching steps.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. With continued reference to fig. 8, a schematic structural diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate (not labeled) comprising a device area I and a dummy pattern area II which are adjacent to each other; the device mask side wall 220 is positioned on the substrate 100 of the device region I, and the device mask side wall 220 is used as a mask for etching the substrate; the remaining pseudo mask side walls 230 to be removed by etching are located on the substrate of the pseudo pattern region II, and the tops of the remaining pseudo mask side walls 230 are lower than the tops of the device mask side walls 220; a filling layer 300 located on the substrate, wherein the filling layer covers the device mask sidewall 220 and exposes the top of the remaining pseudo mask sidewall 230, and a trench 330 is defined by the filling layer 300 and the remaining pseudo mask sidewall 230; and a sidewall protection layer 350 on sidewalls of the trench 330.
In the forming process of the semiconductor structure, in the process of forming the device mask sidewall 220, a pseudo mask sidewall is formed on the substrate of the pseudo pattern region ii, and the remaining pseudo mask sidewall 230 is formed by etching the pseudo mask sidewall with a partial thickness. And subsequently, the remaining pseudo mask sidewall 230 is etched and removed, wherein under the protection effect of the sidewall protection layer 350, in the process of removing the remaining pseudo mask sidewall 230 by etching, the lateral etching of the sidewall of the trench 330 by an etching process can be reduced, so that the probability that the device mask sidewall 220 adjacent to the pseudo pattern region ii is erroneously etched is reduced, the device mask sidewall 220 correspondingly has lower line width roughness, and the line width uniformity of the device mask sidewall 220 is improved.
And the substrate is used for forming a target pattern after a patterning process. In this embodiment, the base includes an initial substrate 100 and a hard mask material layer 120 located on the initial substrate 100, where the initial substrate 100 is used to form a fin portion, that is, the target pattern is a fin portion. In other embodiments, the base may also include a substrate and a gate material layer on the substrate, where the gate material layer is used to form a gate structure, that is, the target pattern is a gate structure.
In this embodiment, the material of the initial substrate 100 is silicon. In other embodiments, the material of the initial substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the initial substrate may also be other types of bases such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In subsequent processes, a pattern is first defined in the hard mask material layer 120 to form a patterned hard mask layer, so that the hard mask layer serves as a mask for etching the initial substrate 100. The hard mask material layer 120 is made of a nitrogen-containing material, so that the hardness and the compactness of the hard mask material layer 120 are high. In this embodiment, the material of the hard mask material layer 120 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. These materials have a high degree of compactness and hardness, and the etching selectivity of the material of the initial substrate 100 to the above-mentioned materials is high during the subsequent etching of the initial substrate 100. As an example, the material of the hard mask material layer 120 is silicon nitride.
It is noted that the base further includes a buffer layer 110 between the initial substrate 100 and the hard mask material layer 120. The buffer layer 110 has good adhesion to the hard mask material layer 120, and the buffer layer 110 has good adhesion to the initial substrate 100. Furthermore, the buffer layer 110 is used to provide a stress buffering effect when the hard mask material layer 120 is formed, thereby improving the problem of dislocation generated when the hard mask material layer 120 is formed. In this embodiment, the buffer layer 110 is made of silicon oxide.
The device mask sidewall spacers 220 are used as a mask for subsequent substrate etching. The material of the device mask sidewall spacers 220 may include one or more of silicon oxide, silicon nitride, silicon, titanium oxide, titanium nitride, and tungsten carbide. In this embodiment, the material of the device mask sidewall spacer 220 is silicon nitride.
The remaining pseudo mask sidewall 230 is located on the substrate of the pseudo pattern region ii, the remaining pseudo mask sidewall 230 is formed by etching a part of the pseudo mask sidewall, and the pseudo mask sidewall and the device mask sidewall 220 are formed in the same step, so that the remaining pseudo mask sidewall 230 and the device mask sidewall 220 are made of the same material.
The ratio of the height difference between the device mask sidewall 220 and the remaining dummy mask sidewall 230 to the height of the device mask sidewall 220 is not too small or too large. If the ratio is too small, that is, the height of the remaining pseudo mask sidewall 230 is large, the time required for subsequently etching the remaining pseudo mask sidewall 230 is long, and during the process of etching the remaining pseudo mask sidewall 230, not only the longitudinal etching is performed, but also a certain amount of lateral etching is generated, so that the probability that the device mask sidewall 220 is erroneously etched is still high; if the ratio is too small, that is, the longitudinal etching amount of the pseudo mask sidewall is large in the process of etching the pseudo mask sidewall to form the remaining pseudo mask sidewall 230, and in the process of etching the pseudo mask sidewall, not only the longitudinal etching is performed, but also a certain transverse etching amount is generated, which also increases the probability that the device mask sidewall 220 is erroneously etched. Therefore, in this embodiment, the height difference between the device mask sidewall 220 and the remaining dummy mask sidewall 230 accounts for 1/3-1/2 of the height of the device mask sidewall 220. The longitudinal direction is a direction perpendicular to the substrate surface, and the transverse direction is a direction parallel to the substrate surface and perpendicular to the sidewall of the device mask sidewall 220.
The filling layer 300 is used for protecting the device mask sidewall spacers 220 and the substrate during the process of forming the trench 330 and the process of subsequently etching the remaining pseudo mask sidewall spacers 230. The material of the filling layer 300 is an organic material. Specifically, the material of the filling layer 300 includes a spin-on carbon layer material, a bottom anti-reflective coating material, a dielectric anti-reflective coating material, a deep ultraviolet light absorbing oxide layer material, or an advanced patterning film material.
In this embodiment, the material of the filling layer 300 is an advanced patterning film material. The advanced patterning film material has excellent physical properties, so that the sidewall of the trench 330 has low line edge roughness, the morphology quality of the sidewall of the trench 330 is correspondingly improved, and the line width uniformity of the trench 330 is favorably improved.
In this embodiment, the semiconductor structure further includes: and a shielding layer 310 located on the filling layer 300, wherein an opening 320 is formed in the shielding layer 310, the bottom of the opening 320 is communicated with the top of the trench 330, and the shielding layer 310 is used as a mask for forming the trench 330.
In this embodiment, the width of the opening 320 is greater than the width of the remaining pseudo mask sidewall 230 along the direction parallel to the substrate surface and perpendicular to the sidewall of the remaining pseudo mask sidewall 230, so as to increase the process window for forming the opening 320, and easily make the opening 320 located above the remaining pseudo mask sidewall 230. The difference between the width of the opening 320 and the width of the remaining sidewall 230 of the pseudo mask is not too small or too large. If the width difference is too small, the problem that the relative positions of the opening 320 and the pseudo mask side wall are offset easily occurs in the process of etching the pseudo mask side wall to form the remaining pseudo mask side wall 230, so that the morphology and the size accuracy of the remaining pseudo mask side wall 230 are affected; if the width difference is too large, the device mask sidewall spacers 220 are easily exposed in the process of forming the trench 330, so that the device mask sidewall spacers 220 are erroneously etched. Therefore, in the present embodiment, the difference between the width of the opening 320 and the width of the remaining dummy mask sidewall 230 is 3 nm to 4 nm.
The material of the blocking layer 310 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the shielding layer 310 is silicon oxide. The etch selectivity between silicon nitride and silicon oxide is relatively high. Furthermore, the silicon oxide material is easily removed.
In the subsequent process of removing the remaining pseudo mask sidewall 230 by etching, the sidewall protection layer 350 is used for protecting the sidewall of the trench 330, and can reduce the lateral etching of the sidewall of the trench 330 by the process of etching the remaining pseudo mask sidewall 230, thereby reducing the probability that the device mask sidewall 220 adjacent to the remaining pseudo mask sidewall 230 is erroneously etched, correspondingly enabling the device mask sidewall 220 to have lower line width roughness, and improving the line width uniformity of the device mask sidewall 220.
Therefore, when the remaining pseudo mask sidewall spacers 230 are subsequently etched, the remaining pseudo mask sidewall spacers 230 and the sidewall protection layer 350 have a higher etching selectivity, so that the sidewall protection layer 350 can protect the sidewalls of the trench 330. Specifically, the etching selectivity between the remaining dummy mask sidewall spacers 230 and the sidewall protection layer 350 is greater than 5: 1. The material of the sidewall protection layer 350 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the sidewall protection layer 350 is silicon oxide. The remaining pseudo mask sidewall 230 is made of silicon nitride, the etching selectivity between silicon nitride and silicon oxide is high, and the silicon oxide material is easily removed.
In addition, in this embodiment, the materials of the sidewall protection layer 350 and the shielding layer 310 are the same, so that the sidewall protection layer 350 and the shielding layer 310 can be removed in the same step.
In this embodiment, the sidewall protection layer 350 is also located on the sidewall of the opening 320. Therefore, in the process of forming the sidewall protection layer 350, the shielding layer 310 protects the top of the filling layer 300, so as to reduce the probability of damaging the top of the filling layer 300, and further reduce the probability of exposing the device mask sidewall 220.
Note that the thickness of the sidewall protection layer 350 should not be too small, and should not be too large. If the thickness of the sidewall protection layer 350 is too small, in the process of removing the remaining pseudo mask sidewall 230 by subsequent etching, the protection capability of the sidewall protection layer 350 on the sidewall of the trench 330 is low, and the probability that the device mask sidewall 220 is erroneously etched is correspondingly high; if the thickness of the sidewall protection layer 350 is too large, the sidewall protection layer 350 may be removedThe remaining pseudo mask sidewall 230 is easily blocked, thereby affecting the subsequent etching of the remaining pseudo mask sidewall 230. For this reason, in this embodiment, the thickness of the sidewall protection layer 350 is
Figure BDA0002742064550000181
To
Figure BDA0002742064550000182
For example, the sidewall protection layer 350 has a thickness of
Figure BDA0002742064550000183
Or
Figure BDA0002742064550000184
It should be further noted that the semiconductor structure further includes: and an etch stop layer 130 between the remaining dummy mask sidewalls 230 and the substrate, between the device mask sidewalls 220 and the substrate, and between the fill layer 300 and the substrate. The process for forming the device mask sidewall 220 and the pseudo mask sidewall includes an etching process, and in the etching process, the etching stop layer 130 can define an etching stop position in the etching process so as to prevent etching damage to the hard mask material layer 120, thereby reducing the probability of the problem of inconsistent height of the top surface of the hard mask material layer 120, and accordingly facilitating improvement of the precision of subsequent pattern transfer.
The material of etch stop layer 130 includes one or more of silicon nitride, titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. In this embodiment, the material of the etch stop layer 130 is silicon oxide.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising an adjacent device area and a pseudo-pattern area, wherein a device mask side wall is formed on the substrate of the device area, and a pseudo-mask side wall is formed on the substrate of the pseudo-pattern area;
forming a filling layer on the substrate, wherein the filling layer covers the device mask side wall and the pseudo mask side wall;
etching the filling layer and the pseudo mask side wall with partial height in the pseudo pattern area to form a residual pseudo mask side wall, wherein the residual pseudo mask side wall and the filling layer enclose a groove;
forming a side wall protection layer on the side wall of the groove;
after the side wall protective layer is formed, etching to remove the residual pseudo mask side wall;
removing the side wall protection layer;
removing the filling layer after removing the side wall protection layer;
and after removing the filling layer, etching the substrate by taking the device mask side wall as a mask.
2. The method of forming a semiconductor structure of claim 1, wherein forming a sidewall protection layer on sidewalls of the trench comprises: forming a layer of sidewall protection material conformally covering the bottom and sidewalls of the trench and the top of the fill layer;
and removing the side wall protection material layer at the bottom of the groove and at the top of the filling layer, and reserving the residual side wall protection material layer at the side wall of the groove as a side wall protection layer.
3. The method of claim 2, wherein the layer of protective material is formed using an atomic layer deposition process or a high aspect ratio chemical vapor deposition process.
4. The method for forming a semiconductor structure according to claim 1, wherein after removing the remaining dummy mask sidewall spacers by etching and before removing the sidewall protection layer, the method further comprises: forming a sacrificial layer on the substrate exposed by the filling layer, wherein the side wall protection layer is exposed by the sacrificial layer;
after removing the side wall protection layer, before etching the substrate by using the device mask side wall as a mask, the forming method further comprises: and removing the sacrificial layer.
5. The method of forming a semiconductor structure of claim 4, wherein the step of forming the sacrificial layer comprises: forming a sacrificial material layer covering the filling layer and the substrate;
and etching back the sacrificial material layer to expose the residual sacrificial material layer out of the side wall protection layer, wherein the residual sacrificial material layer is used as a sacrificial layer.
6. The method of claim 1, wherein the base comprises an initial substrate and a hard mask material layer on the initial substrate, the initial substrate is used for forming a fin;
the step of etching the substrate by taking the device mask side wall as a mask comprises the following steps: etching the hard mask material layer by taking the device mask side wall as a mask to form a hard mask layer;
the forming method further includes: and etching the initial substrate by taking the hard mask layer as a mask to form a substrate and a fin part protruding out of the substrate.
7. The method of forming a semiconductor structure of claim 1, wherein the step of forming the device mask sidewall spacers and the dummy mask sidewall spacers comprises: forming a core layer on the substrate;
forming a mask side wall on the side wall of the core layer, wherein the mask side wall positioned in the device region is used as a device mask side wall, and the mask side wall positioned in the pseudo-pattern region is used as a pseudo-mask side wall;
and removing the core layer.
8. The method for forming a semiconductor structure according to claim 1, wherein before etching the fill layer and the partial height of the dummy mask sidewall spacers, the method further comprises: forming a shielding layer on the filling layer, wherein an opening of the filling layer exposing the dummy pattern area is formed in the shielding layer;
in the step of etching the filling layer and the pseudo mask side wall with partial height, the shielding layer is used as a mask to etch along the opening;
after the residual pseudo mask side wall is removed by etching and before the filling layer is removed, the forming method further comprises the following steps: and removing the shielding layer.
9. The method for forming a semiconductor structure according to claim 8, wherein the shielding layer and the sidewall protection layer are made of the same material;
and in the same step, removing the shielding layer and the side wall protection layer.
10. The method of forming a semiconductor structure of claim 4, wherein the sacrificial layer has a thickness of
Figure FDA0002742064540000031
To
Figure FDA0002742064540000032
11. The method of claim 4, wherein the sacrificial layer comprises a spin-on carbon layer material, a bottom anti-reflective coating material, a dielectric anti-reflective coating material, a deep ultraviolet light absorbing oxide layer material, or an advanced patterning film material.
12. The method for forming a semiconductor structure according to claim 1, wherein an anisotropic etching process is used to etch the filling layer and the pseudo mask sidewall with a partial height;
and etching to remove the residual pseudo mask side wall by adopting an anisotropic etching process.
13. A semiconductor structure, comprising:
a substrate including a device region and a dummy pattern region adjacent to each other;
the device mask side wall is positioned on the substrate of the device area and used as a mask for etching the substrate;
the residual pseudo mask side wall to be etched and removed is positioned on the substrate of the pseudo pattern area, and the top of the residual pseudo mask side wall is lower than that of the device mask side wall;
the filling layer is positioned on the substrate, covers the device mask side wall and exposes the top of the residual pseudo mask side wall, and the filling layer and the residual pseudo mask side wall enclose a groove;
and the side wall protection layer is positioned on the side wall of the groove.
14. The semiconductor structure of claim 13, wherein the semiconductor structure further comprises: the shielding layer is positioned on the filling layer, an opening is formed in the shielding layer, the bottom of the opening is communicated with the top of the groove, and the shielding layer is used as a mask for forming the groove;
the sidewall protection layer is also located on a sidewall of the opening.
15. The semiconductor structure of claim 14, wherein a width of the opening is greater than a width of the remaining dummy mask sidewall in a direction parallel to the substrate surface and perpendicular to the sidewalls of the remaining dummy mask sidewall, and a difference between the widths of the opening and the remaining dummy mask sidewall is between 3 nm and 4 nm.
16. The semiconductor structure of claim 13, wherein the sidewall protection layer has a thickness of
Figure FDA0002742064540000041
To
Figure FDA0002742064540000042
17. The semiconductor structure of claim 13, wherein a difference in height between the device mask sidewall and the remaining dummy mask sidewall is between 1/3 and 1/2 of a height of the device mask sidewall.
18. The semiconductor structure of claim 13, wherein the material of the fill layer comprises a spin-on carbon layer material, a bottom anti-reflective coating material, a dielectric anti-reflective coating material, a deep ultraviolet light absorbing oxide layer material, or an advanced patterning film material.
19. The semiconductor structure of claim 13, wherein a material of the sidewall protection layer comprises one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
20. The semiconductor structure of claim 13, wherein the base comprises an initial substrate and a layer of hard mask material on the initial substrate.
CN202011153840.3A 2020-10-26 2020-10-26 Semiconductor structure and forming method thereof Pending CN114496735A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011153840.3A CN114496735A (en) 2020-10-26 2020-10-26 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011153840.3A CN114496735A (en) 2020-10-26 2020-10-26 Semiconductor structure and forming method thereof

Publications (1)

Publication Number Publication Date
CN114496735A true CN114496735A (en) 2022-05-13

Family

ID=81470650

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011153840.3A Pending CN114496735A (en) 2020-10-26 2020-10-26 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN114496735A (en)

Similar Documents

Publication Publication Date Title
CN110739210B (en) Semiconductor structure and forming method thereof
CN112309838B (en) Semiconductor structure and forming method thereof
CN111640656B (en) Semiconductor device and method of forming the same
CN109559978B (en) Semiconductor structure and forming method thereof
US20200411366A1 (en) Semiconductor structure and method for the forming same
TW202218161A (en) Semiconductor structure and forming method therefor
CN110690117B (en) Semiconductor structure and forming method thereof
US11769672B2 (en) Semiconductor structure and forming method thereof
CN114334619A (en) Method for forming semiconductor structure
CN111668093B (en) Semiconductor device and method of forming the same
CN111640659B (en) Semiconductor device and method of forming the same
US8765608B2 (en) Methods for forming trenches
CN114496735A (en) Semiconductor structure and forming method thereof
CN112908836B (en) Semiconductor structure and forming method thereof
US11557480B2 (en) Semiconductor structure and fabrication method thereof
CN112018034B (en) Semiconductor structure and forming method thereof
US11309184B2 (en) Semiconductor structure and formation method thereof
CN113327843B (en) Method for forming semiconductor structure
CN111640667B (en) Semiconductor device and method of forming the same
CN111640666B (en) Semiconductor device and method of forming the same
CN111986989B (en) Semiconductor structure and forming method thereof
CN113972170A (en) Method for forming semiconductor structure
CN111952154A (en) Patterning method and semiconductor device formed by same
CN112017948A (en) Semiconductor structure and forming method thereof
CN112053947A (en) Patterning method and semiconductor device formed by same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination