CN114496013B - Memory computing device and memory computing method for spin random access memory and electronic equipment - Google Patents
Memory computing device and memory computing method for spin random access memory and electronic equipment Download PDFInfo
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Abstract
The invention relates to a spin random access memory in-memory computing device, a memory computing method and an electronic device. A spin random access memory in-memory computing device comprising: an array of a plurality of in-memory computing cells including magnetic tunnel junctions, a first word line disposed row by row, and a first bit line, a second bit line, and a third bit line disposed column by column, the in-memory computing cells being connected between the first word line and the first bit line, the third bit line being connected to a gate of a switching transistor between the in-memory computing cells and the first bit line, the second bit line being electrically isolated from the in-memory computing cells. The array of in-memory computing units stores a transpose of the input matrix whose element values correspond to the continuously adjustable conductance values of the magnetic tunnel junctions, the first word lines applying voltage values corresponding to the element values of the input column vectors to each row of in-memory computing units, respectively, the first bit lines outputting current values corresponding to the element values of the output column vectors.
Description
Technical Field
The present invention relates generally to the field of in-memory computing, and more particularly, to a spin random access memory in-memory computing device based on a thermal excitation effect, a method of in-memory computing using the spin random access memory in-memory computing device based on a thermal excitation effect, and an electronic apparatus including the spin random access memory in-memory computing device.
Background
In a conventional von neumann architecture, the memory and the computing unit are two separate components from each other. When the computer executes the calculation operation, the data needs to be taken out from the memory, transmitted to the calculation unit for calculation, and then the calculation result is returned to the memory. All the functions of the computer are realized by such a reciprocating data handling process, the memory access and the calculation of data are high in total energy consumption.
The in-memory computing (Computing In Memory, CIM) is a newly proposed computing mode, which combines a computing component with a memory, integrates storage and computation, breaks through the von Neumann architecture of the traditional computer, and can greatly reduce the computational power and the power consumption limitation caused by data migration. The most central problems of in-memory computing mainly include computing accuracy, computing scale (i.e., the degree of integration of the computing array), computing speed, power consumption, and the like. One important application scenario for in-memory computing is matrix operations in artificial intelligence. The core of large-scale computation such as neural network training is to solve the Matrix-vector multiplication (Matrix-vector multiplication, MVM), i.e., ax=b problem, where A, b is a Matrix and x is a vector. The conductance of the current Resistive Random Access Memory (RRAM) and phase change memory (PCRAM) has obvious problems of fluctuation, noise and drift, and the calculation accuracy in the memory based on the devices is limited. Binary Magnetic Random Access Memory (MRAM) based on electron spin tunneling has better fluctuation characteristics, but multi-value storage is not realized at present, and is not suitable for matrix vector multiplication operation.
Therefore, there is still a need to explore new devices and architectures to meet the requirements of in-memory computing for precision, integration, speed, and power consumption.
Disclosure of Invention
The present invention has been made in view of the above problems.
One aspect of the present invention provides a spin random access memory in-memory computing device comprising: an array of a plurality of in-memory computational cells, each in-memory computational cell comprising a magnetic tunnel junction based on a thermal excitation effect; a first word line provided for each row of the memory cells; and a first bit line, a second bit line, and a third bit line provided for each column of in-memory computing units, each in-memory computing unit being connected between a corresponding first word line and first bit line, the third bit line being connected to a gate of a switching transistor provided between the in-memory computing unit and the first bit line, the second bit line being electrically isolated from the in-memory computing unit. The first word line and the second bit line are configured to receive a write current to generate a write field that continuously adjusts a magnetization direction of a free magnetic layer of the magnetic tunnel junction relative to a magnetization direction of a reference magnetic layer between a parallel direction and an anti-parallel direction such that a conductance value of the magnetic tunnel junction is continuously adjustable within a corresponding range. The array of in-memory computing units is configured to store a transpose of the input matrix, wherein the transposed element values of the input matrix correspond to continuously adjustable conductance values of the magnetic tunnel junctions, respectively. The first word line is further configured to apply voltage values corresponding to element values of the input column vector to respective in-row-memory computing units storing a transpose of the memory matrix, respectively. The first bit lines are configured to output current values corresponding to element values of output column vectors, and the current value output by each first bit line is a current sum obtained by converging output currents of the computing units in each memory in the corresponding column on the first bit lines.
In some embodiments, the magnetic tunnel junction includes a first electrode, a first antiferromagnetic layer, a reference magnetic layer, an insulating barrier layer, a free magnetic layer, a second antiferromagnetic layer, and a second electrode formed in that order, the second antiferromagnetic layer having a blocking temperature that is lower than the blocking temperature of the first antiferromagnetic layer.
In some embodiments, when writing a transpose of an input matrix in an array of in-memory computing cells, a third bit line corresponding to the in-memory computing cell to be written is configured to turn on a switching transistor, a first word line and a second bit line corresponding to the in-memory computing cell to be written receive current to generate a write magnetic field, the first word line and the first bit line corresponding to the in-memory computing cell to be written apply a heating current flowing through a magnetic tunnel junction to heat the magnetic tunnel junction such that the write magnetic field orients a magnetization direction of a free magnetic layer of the magnetic tunnel junction in a same direction as the write magnetic field, such that a continuously adjustable conductance value of the magnetic tunnel junction is adjusted to a conductance value corresponding to an element value of the transpose of the input matrix.
In some embodiments, when writing of the conductance value is completed, the first word line and the second bit line are configured to stop applying the write magnetic field after stopping applying the heating current.
In some embodiments, the heating current heats the magnetic tunnel junction to a temperature that is above a blocking temperature of the second antiferromagnetic layer and below a blocking temperature of the first antiferromagnetic layer.
In some embodiments, the free magnetic layer and the reference magnetic layer have in-plane magnetization directions, and at least the free magnetic layer has in-plane isotropy.
Another aspect of the present invention provides a method of in-memory computation using a spin random access memory in-memory computing device including an array of a plurality of in-memory computing cells, a first word line provided for each row of in-memory computing cells, and first, second, and third bit lines provided for each column of in-memory computing cells, each in-memory computing cell including a magnetic tunnel junction based on a thermal excitation effect and being connected between the corresponding first word line and first bit line, the third bit line being connected to a gate of a switching transistor provided between the in-memory computing cell and the first bit line, the second bit line being electrically isolated from the in-memory computing cell, the method comprising: applying write currents on the first word line and the second bit line to generate write magnetic fields that continuously adjust the magnetization direction of the free magnetic layer in the magnetic tunnel junction of the in-memory computing unit relative to the magnetization direction of the reference magnetic layer between a parallel direction and an anti-parallel direction, such that the conductance value of each magnetic tunnel junction is continuously adjustable within a corresponding range, controlling the magnitude and direction of the write currents applied on the first word line and the second bit line to write the conductance value corresponding to the transposed element value of the input matrix into the corresponding magnetic tunnel junction; applying voltage values corresponding to element values of input column vectors to respective row memory computation units storing transposes of input matrices through first word lines; and outputting current values corresponding to the element values of the output column vectors through the first bit lines, wherein the current value output by each first bit line is a current sum obtained by converging the output current of the computing unit in each memory in the corresponding column on the first bit line.
In some embodiments, the magnetic tunnel junction includes a first electrode, a first antiferromagnetic layer, a reference magnetic layer, an insulating barrier layer, a free magnetic layer, a second antiferromagnetic layer, and a second electrode formed in that order, the second antiferromagnetic layer having a blocking temperature that is lower than the blocking temperature of the first antiferromagnetic layer.
In some embodiments, when writing the transpose of matrix a in the array of in-memory computing cells, a third bit line corresponding to the in-memory computing cell to be written is configured to turn on the switching transistor, the first word line and the second bit line corresponding to the in-memory computing cell to be written receive a write current to generate a write magnetic field, the first word line and the first bit line corresponding to the in-memory computing cell to be written apply a heating current through the magnetic tunnel junction to heat the magnetic tunnel junction such that the write magnetic field orients a magnetization direction of a free magnetic layer of the magnetic tunnel junction in a same direction as the write magnetic field, whereby a continuously adjustable conductance value of the magnetic tunnel junction is adjusted to a conductance value corresponding to an element value of a device inputting the matrix.
In some embodiments, when the writing of the conductance value is completed, the application of the write magnetic field is stopped after the heating current is stopped.
In some embodiments, the heating current heats the magnetic tunnel junction to a temperature that is above a blocking temperature of the second antiferromagnetic layer and below a blocking temperature of the first antiferromagnetic layer.
In some embodiments, the free magnetic layer and the reference magnetic layer have in-plane magnetization directions, and at least the free magnetic layer has in-plane isotropy.
Another aspect of the present invention provides an electronic device comprising the above spin-random access memory in-memory computing apparatus.
The invention adopts the following technical scheme and has the following beneficial effects:
(1) The invention overcomes the problem of the volatility of the Static Random Access Memory (SRAM) and the Dynamic Random Access Memory (DRAM) by utilizing the nonvolatile characteristic of the Magnetic Random Access Memory (MRAM), and combines with the in-memory calculation, so that the in-memory calculation has the advantage of still being capable of maintaining data after power failure.
(2) The invention overcomes the defects of low integration level and low read-write speed of the Flash memory (Flash) by utilizing the characteristics of high integration level and high read-write speed of the Magnetic Random Access Memory (MRAM), and is hopeful to realize high integration level and large-scale high-speed in-memory calculation by combining with in-memory calculation.
(3) The Magnetic Random Access Memory (MRAM) based on the spin electron tunneling mechanism solves the problem of poor precision caused by RRAM and PCRAM conductivity fluctuation by utilizing the good conductivity fluctuation characteristic of the magnetic random access memory, and can realize accurate numerical value storage and reading operation, thereby improving the accuracy of memory operation.
(4) The invention uses the spin magnetic random access memory technology of thermal excitation, uses current to assist in heating, and under the effect of exchange bias, the magnetization of the free layer is turned over and stabilized in the same direction as the external magnetic field. The technology can continuously regulate and control the conductance of the magnetic tunnel junction by regulating the magnetic moment included angle, so that multi-value storage can be realized, and the technology can be applied to analog memory calculation.
(5) The invention combines the technology of the thermally excited spin magnetic random access memory with the in-memory calculation, designs the in-memory calculation circuit of the thermally excited spin magnetic random access memory, fills the blank of the in-memory calculation of the analog MRAM, solves the problems of complex heating circuit and the like, and realizes the high-precision, large-scale and high-speed MVM analog in-memory calculation.
The above and other features and advantages of the present invention will become more apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram showing the principle of in-memory computation.
FIG. 2 is a circuit schematic diagram illustrating a thermally activated spin-magnetic random access memory in-memory computing device according to one embodiment of the invention.
Fig. 3 is a schematic diagram illustrating a configuration of a single in-memory computing unit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram showing the direction of a resultant magnetic field generated using word lines and bit lines according to an embodiment of the present invention.
Fig. 5 is a schematic diagram showing magnetization directions of a free magnetic layer and a fixed magnetic layer of a calculation unit in a spin-magnetic random access memory according to an embodiment of the present invention.
Fig. 6 is a timing diagram illustrating the application of write current and heating current during a write operation according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
FIG. 1 shows a schematic diagram of an in-memory computing principle that is equally applicable to a thermally activated spin-magnetic random access memory in-memory computing device according to embodiments of the invention described below. As shown in fig. 1, the in-memory computing device includes an array of m rows and n columns of in-memory computing units 11, m and n being integers greater than 1. Each in-memory computing unit 11 is a multi-value storage unit, and for example, a desired value can be written/stored by adjusting its conductance. In the m×n array of the in-memory computing unit 11, a transpose a T of a matrix a may be stored, where the matrix a is a matrix of n rows and m columns, and thus the transpose a T of the matrix a is a matrix of m rows and n columns, as shown in equations (1) and (2), respectively, below. It should be appreciated that although an mxn array of in-memory computing units 11 is described herein, it may be formed as a larger array, such as a 2 mxn array, so that other operations, such as operations involving negative values, etc., may be conveniently performed.
The row decoder 12 may apply m voltages v 0 to v m-1 to the m-row in-memory computing units 11 through word lines WL 0 to WL m-1, respectively. Each in-memory computing unit 11 generates a current I when a voltage v is applied, the magnitude of the current I being equal to the product i=vg of the voltage v and the conductance G of the in-memory computing unit 11. With the bit lines BL 0 to BL n-1, the output circuit 13 can read the sum of the output currents I 0 to I n-1 of the calculation units 11 in each column, thereby completing the matrix vector operation represented by the following equation (3), in which the vectors x and b are represented by the equation (4) and the equation (5), respectively. The method can be used for solving extensive algebraic problems such as linear equation sets, matrix eigenvectors and the like, and time-consuming and energy-consuming iterative operations are not needed.
Ax＝b (3)
It will be appreciated that in the process of actually performing Matrix Vector Multiplication (MVM) computation, there is a certain gap between the value ranges of the elements in the known n×m matrix a and m×1 column vector x as inputs and m×1 column vector b as outputs and the value ranges of the conductance values of the in-memory computing units, the voltage values applied thereto and the current values output thereto, so that in the computation, the values of the matrix a and the column vector x are normalized to adapt to the conductance ranges and the input voltage ranges of the device circuits. Similarly, after the output column vector b is obtained, the element values thereof are subjected to corresponding inverse processing to recover the obtained output result values. These normalization and inverse processes are well known in the art of in-memory computing and therefore will not be described in detail herein. For convenience and brevity, the respective element values in the matrix a and column vectors x, b are directly expressed in the present application by the conductance values, the voltage values, and the current values as in the above equations 1, 4, and 5.
FIG. 2 is a circuit schematic diagram illustrating a thermally activated spin-magnetic random access memory in-memory computing device according to one embodiment of the invention. As shown in fig. 2, the in-memory computing device includes an array of in-memory computing units 11, here shown as an m×n array for descriptive convenience, so that the location of each in-memory computing unit 11 in the array can be used as its address. The in-memory computing units 11 of each row are provided with first word lines WL extending in the row direction, the number of the first word lines WL being equal to the number m of rows of the array; the in-memory computing units 11 are provided with first, second, and third bit lines BL, BLB, and BLG extending in the column direction, the number of which is equal to the column number n of the array.
The input circuit 10 may receive input signals, which may include address data of the in-memory computing unit 11 and data for writing, reading, in-memory computing operations, etc. to the in-memory computing unit 11, and the input circuit 10 may include normalization circuits, which may normalize the a matrix and the x vector to accommodate the conductance range and the input voltage range of the device circuit. In some embodiments, the input circuit 10 may include a digital-to-analog converter (DAC) for converting a received digital input signal into an analog signal that may be used for various operations on the in-memory computing unit 11. The input circuit 10 may normalize the a matrix and x vector to accommodate the conductance range and input voltage range of the device circuit. The input circuit 10 may supply input data to the row decoder 12 and the column decoder 14, and the row decoder 12 and the column decoder 14 perform various operations on the array of in-memory computing units 11 through the first word line WL, the third bit line BLG, the first bit line BL, and the second bit line BLB, which will be described in further detail below.
The output circuit 13 may receive the output of the in-memory computing unit 11 through the first bit lines BL 0 to BL n-1. As described in detail below, the output received by the output circuit 13 may be data stored in the in-memory computing unit 11 or may be computation result data obtained after in-memory computation in the in-memory computing unit 11. The output circuit 13 may include an analog-to-digital converter (ADC) to convert the read analog signal into a digital signal; and a conversion circuit converting the output signal into a vector b.
Fig. 3 shows a schematic diagram of the structure of a single in-memory computing unit 11 according to an embodiment of the present invention. It will be appreciated that each in-memory computing unit 11 in the array shown in fig. 2 may have the structure shown in fig. 3. Referring to fig. 3, the in-memory computing unit 11 may include a Magnetic Tunnel Junction (MTJ) 2 having, in order, an electrode 26, an antiferromagnetic layer 25, a reference magnetic layer 24, a nonmagnetic insulating barrier layer 23, a free magnetic layer 22, an antiferromagnetic layer 21, and an electrode 20. Although FIG. 3 shows the free magnetic layer 22 above the reference magnetic layer 24, the magnetic tunnel junction 2 may also be formed in the reverse order.
Electrodes 20 and 26 may be formed of non-magnetically conductive materials, examples of which include, but are not limited to, non-magnetically conductive metals such as Au, ag, cu, nd, ti, al, ru, rh, mo, zr, hf, V, cr, nb, W, ta, pt and alloys thereof.
The free magnetic layer 22 and the reference magnetic layer 24 may be formed of ferromagnetic conductive materials, examples of which include, but are not limited to Fe, co, ni, gd and alloys thereof, or alloys thereof with one or more of the non-magnetic metallic materials Ti, V, zn, cu, ag, au, nb, ta, cr, mo, W, re, ru, os, rh, ir, pt, hf, cd, zr, sc, etc.
The insulating barrier layer 23 may be formed of a non-magnetic insulating material, examples of which include, but are not limited to, one or more of MgO、Al2O3、 Al2MgO4、ZnO、ZnMgO2、TiO2、HfO2、TaO2、Cd2O3、ZrO2、Ga2O3、Sc2O3、 V2O5、Fe2O3、Co2O3、NiO、CuO.
Antiferromagnetic layers 21 and 25 may be formed of antiferromagnetically conductive materials, examples of which include, but are not limited to IrMn, ptMn, osMn, rhMn, feMn, crPtMn, ruMn, niMn, ptPdMn and the like. It should be noted that by selecting appropriate materials for antiferromagnetic layers 21 and 25, the blocking temperature T B1 of antiferromagnetic layer 21 is made lower than the blocking temperature T B2 of antiferromagnetic layer 25. For example, antiferromagnetic layer 25 may be formed of CrPtMn, ptMn, niMn, ptPdMn or other antiferromagnetic material having a higher blocking temperature, while antiferromagnetic layer 21 may be formed of other antiferromagnetic material having a lower blocking temperature.
In the magnetic tunnel junction 2, the free magnetic layer 22 and the reference magnetic layer 24 may have in-plane magnetizations. The magnetization direction of the reference magnetic layer 24 is fixed by the antiferromagnetic layer 25 and does not change during device operation. As described in detail below, the magnetization direction of the free magnetic layer 22 may be changed during a write operation such that the magnetization direction of the free magnetic layer 22 and the magnetization direction of the reference magnetic layer 24 form an angle θ, and the resistance value of the magnetic tunnel junction 2 is proportional to the cosine of the angle θ. By writing different angles θ, multi-value writing, i.e., writing of one of a plurality of resistance/conductance values, can be achieved in the magnetic tunnel junction 2. The magnetic tunnel junction 2 may be, for example, circular such that at least the free magnetic layer 22 has in-plane isotropy, enabling different angle values θ to be written conveniently.
One end of the magnetic tunnel junction 2, e.g., electrode 20, may be connected to the first word line WL, the other end, e.g., electrode 26, may be connected to the first bit line BL through the switching transistor 3, and the control gate of the switching transistor 3 may be connected to the third bit line BLG. The second bit line BLB may be located below the magnetic tunnel junction 2 and electrically isolated from the magnetic tunnel junction 2, which may also be located elsewhere, e.g. above the magnetic tunnel junction 2 and the first word line WL.
A current I WL in the positive and negative extending directions may be applied in the first word line WL, and a heating current I Heat flowing through the in-memory computing unit 11 may also be applied. By selecting the first word line WL and the third bit line BLG, a heating current may be selectively applied to one memory cell 11 in the array to heat it without heating the other memory cells 11, thereby writing operations to a single memory cell 11, as described in detail below. The third bit line BLG may be applied with a voltage V BLG to control on and off of the switching transistor 3, so that a current flowing through the in-memory computing unit 11 may be controlled. Currents I BL and I BLB in the positive and negative extension directions may be applied to the first bit line BL and the second bit line BLB, respectively, although only current out of the page is shown in fig. 3.
Fig. 4 is a schematic diagram showing the directions of the resultant magnetic fields generated using the first word line WL and the second bit line BLB according to an embodiment of the present invention. Four example cases are shown in fig. 4. In the first case, applying a current I WL to the first word line WL, generating a horizontal right oersted magnetic field H WL; a current I BLB is applied to the second bit line BLB, producing a vertically downward oersted magnetic field H BLB. The resultant magnetic field of magnetic fields H WL and H BLB is H total, which is directed in the lower right direction. In the second case, changing the direction of the current I WL applied to the first word line WL, generating the oersted magnetic field H WL horizontally to the left; The direction of the current I BLB applied to the second bit line BLB is unchanged, so that the direction of the oersted magnetic field H BLB generated by the current is unchanged and still vertically downward. At this time, the direction of the combined magnetic field H total of the magnetic fields H WL and H BLB becomes directed in the lower left direction. in the third and fourth cases, a current may not be applied to the second bit line BLB, and thus it does not generate an oersted magnetic field. At this time, the resultant magnetic field H total is equal to the oersted magnetic field H WL generated by the first word line WL, which may be horizontal right (third case) or horizontal left (fourth case) depending on the direction of the current I WL applied to the first word line WL. It will be appreciated that by controlling the magnitude and direction of the current I WL applied to the first word line WL and the current I BLB applied to the second bit line BLB, the resultant magnetic field H total can be made to be in any direction 360 degrees in-plane.
Fig. 5 shows a schematic diagram of the magnetization direction M 22 of the free magnetic layer 22 and the magnetization direction M 24 of the reference magnetic layer 24 after the magnetic moment of the free magnetic layer 22 is oriented using the resultant magnetic field H total generated in fig. 4. as shown in fig. 5, assuming that the magnetization direction M 24 of the reference magnetic layer 24 is horizontal to the right, in the first case, the magnetization direction M 22 of the free magnetic layer 22 and the magnetization direction M 24 of the reference magnetic layer 24 form an included angle of about 45 degrees, It is assumed that it corresponds to the resistance value R 1. In the second case, the magnetization direction M 22 of the free magnetic layer 22 and the magnetization direction M 24 of the reference magnetic layer 24 form an angle of about 135 degrees, which is assumed to correspond to the resistance value R 2. In the third case, the magnetization direction M 22 of the free magnetic layer 22 and the magnetization direction M 24 of the reference magnetic layer 24 form an angle of about 0 degrees, that is, are parallel, assuming that they correspond to the resistance value R 3. In the fourth case, the magnetization direction M 22 of the free magnetic layer 22 and the magnetization direction M 24 of the reference magnetic layer 24 form an angle of about 180 degrees, which is assumed to correspond to the resistance value R 4. Since the resistance value of the magnetic tunnel junction 2 is proportional to the cosine of the angle θ between the magnetization directions of the free magnetic layer 22 and the reference magnetic layer 24 as described above, it can be determined that R 4>R2>R1>R3.
It should be understood that the orientation angles of the magnetization directions of the free magnetic layer 22 shown in FIG. 5 above are examples and not limiting. By controlling the direction of the write magnetic field, i.e. the resultant magnetic field H total, as shown in fig. 4, the magnetization direction of the free magnetic layer 22 can be made continuously adjustable between a parallel direction and an antiparallel direction with respect to the magnetization direction of the reference magnetic layer 24, so that the resistance value of the magnetic tunnel junction 2 is continuously adjustable between a maximum resistance value corresponding to the antiparallel configuration and a minimum resistance value corresponding to the parallel configuration, that is, the conductance value of the magnetic tunnel junction 2 is continuously adjustable within a corresponding range. In the prior art, only the maximum or minimum resistance value is written in each magnetic tunnel junction, so that the writing of single bit 0 or 1 is realized; in the embodiment of the present invention, since the conductance of the magnetic tunnel junction 2 is continuously adjustable within a range, the continuously adjustable conductance of the magnetic tunnel junction can be adjusted to the conductance corresponding to the element value of the matrix a, so that the in-memory calculation operation can be conveniently performed, as described in detail below.
Various operations of a thermally activated spin magnetic random access memory in-memory computing device according to embodiments of the present invention are described below. Describing the write operation first, the present invention enables individual writing to each in-memory computing unit 11. Fig. 6 shows a timing diagram of the application of write currents I WL and I BLB and heating current I heat during a write operation. Referring to fig. 2,3 and 6, in writing to a certain in-memory computing unit 11, a first write current I WL may be applied to a first word line WL to generate a first write magnetic field H WL, and a second write current I BLB may be applied to a second bit line BLB to generate a second write magnetic field H BLB, The in-memory computing unit 11 to be written is located at the crossing position of the first word line WL and the second bit line BLB, so that the resultant magnetic field H total acting on the in-memory computing unit 11 to be written is generated for changing the magnetization direction of the free magnetic layer 22 thereof as shown in fig. 4, and desired data is written. At the same time, the corresponding first word line WL and first bit line BL (or the corresponding first word line WL and third bit line BLG) are selected to apply the heating current I Heat flowing through the in-memory computing unit 11, and at this time, the voltage V BLG is applied to the corresponding third bit line BLG to turn on the switching transistor 3, thereby heating the in-memory computing unit 11 at a temperature greater than the blocking temperature (blocking temperature) T B1 of the antiferromagnetic layer 21, But below the blocking temperature T B2 of the antiferromagnetic layer 25 so that the antiferromagnetic layer 25 can still fix the magnetization direction of the reference magnetic layer 24 so that it is not affected by the external magnetic field H total; Whereas the antiferromagnetic layer 21 changes from antiferromagnetic to superparamagnetic properties at a heating temperature higher than the blocking temperature, the pinning effect to the magnetization direction of the free magnetic layer 22 is lost, and since the free magnetic layer 22 has in-plane homogeneity, the magnetization direction of the free magnetic layer 22 can be easily oriented by the external magnetic field H total into the direction in which the external magnetic field H total is located. It should be noted that, in the write operation, although the magnetic fields generated by the first word line WL and the second bit line BLB have some influence on the other in-memory computing units 11 in the corresponding rows and columns, since the heating current is applied only to the in-memory computing units 11 to be written, even if the heat is diffused to some extent, the adjacent in-memory computing units 11 are not heated to the blocking temperature T B1 of the antiferromagnetic layer 21 or more, so the magnetic fields generated by the first word line WL and the second bit line BLB do not have any substantial influence on the data stored in the other in-memory computing units 11.
As shown in fig. 6, the start times of applying the write currents I WL and I BLB may be before or substantially simultaneously with the application of the heating current I Heat, or after the application of the heating current I Heat, as long as the magnetic field H total can be generated during heating to perform writing. After the magnetization direction of the free magnetic layer 22 is oriented in the direction of H total, when the write operation is ended, it is preferable to stop the application of the heating current I Heat first, at which time the antiferromagnetic layer 21 is gradually cooled below the blocking temperature T B1 in the external magnetic field H total, equivalent to performing a thermal annealing treatment in the magnetic field to the antiferromagnetic layer 21, so that the antiferromagnetic layer 21 having recovered the antiferromagnetic property pins the magnetization direction of the free magnetic layer 22 in the direction of the external magnetic field H total, an accurate write operation is realized, and then the application of the write currents I WL and I BLB is stopped. It will be appreciated that the present invention is able to not affect the magnetization direction of the reference magnetic layer 24 during writing by making the blocking temperature of the antiferromagnetic layer 25 higher than that of the antiferromagnetic layer 21; by providing the antiferromagnetic layer 21 for the free magnetic layer 22, the magnetization of the free magnetic layer 22 can be stably pinned in the writing direction, realizing accurate multi-value writing; in addition, by selecting the corresponding first word line and first bit line to apply the heating current flowing through the single in-memory computing unit 11, it is possible to avoid the influence of the magnetic field generated by the first word line and second bit line on the in-memory computing unit 11 in the same row and column during writing, and to realize individual writing to the target in-memory computing unit 11.
The reading operation is described below. When reading, for the memory computing unit 11 to be read, the voltage V BLG on the corresponding third bit line BLG is controlled to turn on the switching transistor 3, and for the third bit lines BLG of other columns, the switching transistor 3 is turned off. The read voltage of the in-memory computing unit 11 is applied on the first word line WL and the first bit line BL corresponding to the in-memory computing unit 11 to be read, which generates a read current flowing through the magnetic tunnel junction 2, the magnitude of which is correlated with the resistance state of the magnetic tunnel junction 2 (i.e., the magnetization direction angle θ between the free magnetic layer 22 and the reference magnetic layer 24), so that the value stored in the magnetic tunnel junction 2 can be read. The output circuit 13 may receive a read signal from the first bit line BL corresponding to the in-memory computing unit 11 to be read.
The in-memory computing operation is described below, which is similar to a read operation performed on the entire array of all in-memory computing units 11 or on at least one sub-array of in-memory computing units 11 at the same time. For convenience of description, the in-memory calculation of the entire array is described herein as an example, but the principle thereof may also be applied to the in-memory calculation of one of the sub-arrays. In the in-memory computing operation, a voltage V BLG is applied to the third bit line BLG of each column, so that the switching transistor 3 is turned on. Voltages V 0 to V m-1 corresponding to input data are applied to the first word line WL of each row, and for each in-memory computing unit 11 in each row, the generated output current is equal to the product of the voltage it receives and its conductance. The currents output by the respective in-memory computing units 11 in each column are converged and superimposed on the first bit line BL of the column after flowing through the switching transistor 3, and then supplied to the output circuit 13, as shown in the schematic diagram of fig. 1. Thus, the in-memory computing operation is completed.
Another aspect of the invention also provides an electronic device comprising the in-memory computing apparatus described above, which may be, for example, a hardware accelerator for neural network operations. In the hardware accelerator, the in-memory computing device may be configured to perform matrix operations of the neural network. For example, for the convolutional neural network, the weight value of the convolutional kernel may be written into the array of the in-memory computing unit 11, the characteristic data is supplied as input voltages V 0 to V m-1 to the array of the in-memory computing unit 11 through the first word line WL, and the output currents I 0 to I n-1 as the matrix operation result are received on the first bit line BL, thereby completing the matrix operation. This greatly simplifies the structure of hardware devices for performing neural network operations, and increases the operation speed, and is particularly suitable for large-scale neural network models requiring large-scale operations.
Throughout the specification and claims, unless the context clearly requires otherwise, the words "comprise", "comprising", and the like, should be construed in an inclusive sense as opposed to an exclusive or exhaustive sense, that is to say, in a sense of "including but not limited to". Also, the words "herein," "above," "below," and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. The words in the above description using the singular or plural number may also include the plural or singular number, respectively, where the context allows. With respect to the phrase "or" when referring to a list of two or more items, the phrase encompasses all of the following interpretations of the phrase: any item in the list, all items in the list, and any combination of items in the list.
The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, although processes or blocks are presented in a given order, alternative embodiments may perform processes with the steps in a different order or employ systems with the blocks in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. In addition, although processes or blocks are sometimes shown as being performed serially, alternatively, these processes or blocks may be performed in parallel, or may be performed at different times.
The teachings of the present invention provided herein may be applied to other systems, not necessarily the systems described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments.
While some embodiments of the present application have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the application. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms. In addition, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the scope of the application.
Claims (13)
1. A spin random access memory in-memory computing device, comprising:
an array of a plurality of in-memory computational cells, each in-memory computational cell comprising a magnetic tunnel junction based on a thermal excitation effect;
A first word line provided for each row of the memory cells; and
A first bit line, a second bit line, and a third bit line provided for each column of in-memory computing units, each in-memory computing unit being connected between a corresponding first word line and first bit line, the third bit line being connected to a gate of a switching transistor provided between the in-memory computing unit and the first bit line, the second bit line being electrically isolated from the in-memory computing unit,
Wherein the first word line and the second bit line are configured to receive a write current to generate a write field that continuously adjusts a magnetization direction of a free magnetic layer of the magnetic tunnel junction relative to a magnetization direction of a reference magnetic layer between a parallel direction and an anti-parallel direction, such that a conductance value of the magnetic tunnel junction is continuously adjustable within a corresponding range,
The array of in-memory computing units is configured to store a transpose of the input matrix, wherein the transpose of the input matrix has element values corresponding to continuously adjustable conductance values of the magnetic tunnel junctions,
The first word line is also configured to apply voltage values corresponding to the element values of the input column vector to the row memory computation units storing the transpose of the memory matrix, respectively, and
The first bit lines are configured to output current values corresponding to element values of output column vectors, and the current value output by each first bit line is a current sum obtained by converging output currents of the computing units in each memory in the corresponding column on the first bit lines.
2. The spin-random access memory in-memory computing device of claim 1, wherein the magnetic tunnel junction comprises a first electrode, a first antiferromagnetic layer, a reference magnetic layer, an insulating barrier layer, a free magnetic layer, a second antiferromagnetic layer, and a second electrode formed in sequence, the second antiferromagnetic layer having a blocking temperature lower than a blocking temperature of the first antiferromagnetic layer.
3. The spin random access memory in-memory computing device of claim 2, wherein when writing the transpose of the input matrix in the array of in-memory computing cells, the third bit line corresponding to the in-memory computing cell to be written is configured to turn on the switching transistor, the first word line and the second bit line corresponding to the in-memory computing cell to be written receive current to generate a write magnetic field, the first word line and the first bit line corresponding to the in-memory computing cell to be written apply a heating current flowing through the magnetic tunnel junction to heat the magnetic tunnel junction such that the write magnetic field orients the magnetization direction of the free magnetic layer of the magnetic tunnel junction in the same direction as the write magnetic field, whereby the continuously adjustable conductance value of the magnetic tunnel junction is adjusted to a conductance value corresponding to the element value of the transpose of the input matrix.
4. The in-memory computing device of claim 3, wherein, when writing of the conductance value is completed, the first word line and the second bit line are configured to stop applying the write magnetic field after stopping applying the heating current.
5. The spin-random access memory in-memory computing device of claim 3, wherein the heating current heats the magnetic tunnel junction to a temperature that is above a blocking temperature of the second antiferromagnetic layer and below a blocking temperature of the first antiferromagnetic layer.
6. The spin-random access memory in-memory computing device of claim 2, wherein the free magnetic layer and the reference magnetic layer have in-plane magnetization directions, and at least the free magnetic layer has in-plane isotropy.
7. A method of in-memory computation using a spin random access memory in-memory computing device comprising an array of a plurality of in-memory computing cells, a first word line provided for each row of in-memory computing cells, and first, second, and third bit lines provided for each column of in-memory computing cells, each in-memory computing cell comprising a magnetic tunnel junction based on thermal excitation effects and being connected between a corresponding first word line and first bit line, the third bit line being connected to a gate of a switching transistor provided between the in-memory computing cell and the first bit line, the second bit line being electrically isolated from the in-memory computing cell, the method comprising:
Applying write currents on the first word line and the second bit line to generate write magnetic fields that continuously adjust the magnetization direction of the free magnetic layer in the magnetic tunnel junction of the in-memory computing unit relative to the magnetization direction of the reference magnetic layer between a parallel direction and an anti-parallel direction, such that the conductance value of each magnetic tunnel junction is continuously adjustable within a corresponding range, controlling the magnitude and direction of the write currents applied on the first word line and the second bit line to write the conductance value corresponding to the transposed element value of the input matrix into the corresponding magnetic tunnel junction;
applying voltage values corresponding to element values of input column vectors to respective row memory computation units storing transposes of input matrices through first word lines; and
And outputting current values corresponding to the element values of the output column vectors through the first bit lines, wherein the current value output by each first bit line is a current sum obtained by converging the output current of the computing unit in each memory in the corresponding column on the first bit line.
8. The method of claim 7, wherein the magnetic tunnel junction comprises a first electrode, a first antiferromagnetic layer, a reference magnetic layer, an insulating barrier layer, a free magnetic layer, a second antiferromagnetic layer, and a second electrode formed in that order, the second antiferromagnetic layer having a blocking temperature that is lower than a blocking temperature of the first antiferromagnetic layer.
9. The method of claim 8, wherein when writing the transpose of matrix a in the array of memory computing cells, a third bit line corresponding to the memory computing cell to be written is configured to turn on a switching transistor, a first word line and a second bit line corresponding to the memory computing cell to be written receive a write current to generate a write magnetic field, the first word line and the first bit line corresponding to the memory computing cell to be written apply a heating current flowing through a magnetic tunnel junction to heat the magnetic tunnel junction such that the write magnetic field orients a magnetization direction of a free magnetic layer of the magnetic tunnel junction in a same direction as the write magnetic field, whereby a continuously adjustable conductance value of the magnetic tunnel junction is adjusted to a conductance value corresponding to an element value of a device inputting the matrix.
10. The method of claim 9, wherein the application of the write magnetic field is stopped after the heating current is stopped when the writing of the conductance value is completed.
11. The method of claim 9, wherein the heating current heats the magnetic tunnel junction to a temperature that is above a blocking temperature of the second antiferromagnetic layer and below a blocking temperature of the first antiferromagnetic layer.
12. The method of claim 8, wherein the free magnetic layer and the reference magnetic layer have in-plane magnetization directions, and at least the free magnetic layer has in-plane isotropy.
13. An electronic device comprising the in-memory computing apparatus of any one of claims 1-6.
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