CN114490467B - Message processing DMA system and method of multi-core network processor - Google Patents
Message processing DMA system and method of multi-core network processor Download PDFInfo
- Publication number
- CN114490467B CN114490467B CN202210091507.7A CN202210091507A CN114490467B CN 114490467 B CN114490467 B CN 114490467B CN 202210091507 A CN202210091507 A CN 202210091507A CN 114490467 B CN114490467 B CN 114490467B
- Authority
- CN
- China
- Prior art keywords
- message
- data
- dma controller
- ddr
- dma
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000007726 management method Methods 0.000 claims description 10
- 238000013500 data storage Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000004458 analytical method Methods 0.000 claims description 3
- 238000003780 insertion Methods 0.000 claims description 3
- 230000037431 insertion Effects 0.000 claims description 3
- 238000003672 processing method Methods 0.000 claims description 3
- 238000004891 communication Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 208000000649 small cell carcinoma Diseases 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
Abstract
The invention provides a message processing DMA system and method of a multi-core network processor, belonging to the technical field of network communication. The method comprises the steps that a message is sent to a hardware forwarding module through an Ethernet interface module, the hardware forwarding module analyzes the message, a user-defined mode can be supported to carry out shunting, meanwhile, a processor core ID for processing the message is generated, after a processor core corresponding to a CPU processor system receives a request, the received message is stored into a DDR3/4 memory through a DMA mode, signal processing is carried out after the whole message is received, a new data message is generated after processing is completed, and the new data message is sent to the hardware forwarding module and the Ethernet interface module through the DMA mode and is sent out. After the DMA controller sends to the hardware forwarding module, the feedback message informs the CPU processor system, and then the CPU processor system releases the DDR space. The method can realize quick data exchange and high-efficiency data access.
Description
Technical Field
The invention relates to the technical field of network communication, in particular to a message processing DMA system and method for multi-core network processing, which can realize the off-chip efficient storage and data reading of messages of a multi-core network processor chip.
Background
The multi-core network processor chip is a network processor based on a general processor core architecture, is widely applied to a plurality of network communication devices including a carrier Ethernet switch/router, an optical transmission platform, a data center and a broadband infrastructure, can be also applied to devices such as a baseband processing unit (BBU) and a small cell (Smallcell) of a 5G core network, and is a key element of a new generation network communication system. The multi-core network processor combines the high-speed processing capability of hardware and the programmability of software, and can meet the requirements of users on various aspects such as bandwidth, delay and the like.
The "a network processor instruction storage device and the instruction storage method of the device (CN2012102337710. X)" of the emerging communication introduce methods such as instruction storage of a network processor based on a micro-engine structure, and the "controller (CN 201210484096.4) applied to DDR3 memory in the network processor" of the Chinese electric department 32 introduces an optimization method of the DDR3 controller in the multi-core network processor, but does not bypass the general multi-core CPU for Ethernet messages, and how to efficiently exchange the Ethernet messages into the DDR3 is studied.
Disclosure of Invention
The invention aims to provide a message processing DMA system and a message processing DMA method for a multi-core network processor, which can realize the off-chip efficient storage and data reading of a message of a multi-core network processor chip.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a message processing DMA system of a multi-core network processor comprises an Ethernet interface module, a hardware forwarding module, a DMA controller, a CPU processor system and a DDR3/4 memory;
the Ethernet interface module is used for receiving the Ethernet message and sending the Ethernet message to the hardware forwarding module; and the message is received from the hardware forwarding module and sent out;
the hardware forwarding module is used for analyzing the Ethernet message and sending the analyzed message to the DMA controller; the message is received from the DMA controller for analysis and then is sent to the Ethernet interface module;
the DMA controller is used for generating a processor core ID for processing the message, sending a DMA request to the CPU processor system, receiving the DDR address sent by the CPU processor system and the length information for determining the transmission data block, and writing the corresponding data message into the DDR3/4 memory; the system is also used for receiving the data message sent by the CPU processor system, assembling the data message into a message format, sending the message format to the hardware forwarding module, and sending a DMA feedback completion mark to the CPU processor system;
the CPU processor system comprises a plurality of processor cores, wherein one processor core is used for distributing a DDR space in the DDR3/4 memory as a management idle pointer and adopting a linked list for management; the other processor cores are used for responding to the DMA request in a polling mode, after the DMA request sent to the corresponding processor core is polled, the corresponding processor core reads the DDR space to obtain an idle pointer, and sends down the DDR address and the length information for determining the data block to be transmitted to the DMA controller through the annular bus;
the DDR3/4 memory is used for storing data messages in a set format.
Further, the data storage format of the DDR3/4 memory is { next ptr, eop, pkt_len, pkt_data }, next ptr represents a next pointer, eop represents a message terminator, pkt_len represents a message length, and pkt_data represents message data.
A message processing method of a multi-core network processor comprises the following steps:
(1) The process of the DMA controller moving the data block to the memory is as follows:
(1a) After the multi-core network processor chip is electrified, one processor core of the CPU processor system allocates a DDR space as a management idle pointer and adopts a linked list for management;
(1b) The Ethernet interface module receives the message and sends the message to the hardware forwarding module, the hardware forwarding module analyzes the message and then sends the message to the DMA controller, and the DMA controller generates a processor core ID for processing the message and sends a DMA request to the CPU processor system;
(1c) The processor core of the CPU processor system responds to the DMA request in a polling mode, after the DMA request sent to the corresponding processor core is polled, the corresponding processor core reads the DDR space to acquire an idle pointer, and issues a DDR address to the DMA controller and decides to transmit the length information of the data block;
(1d) After receiving the related information of the DDR address, the DMA controller stores corresponding data in a DDR space in a linked list mode, and executes the burst length of one operation, wherein the burst length is configured according to the requirement;
(1e) The DMA controller sends operation ending information to a processor core corresponding to the CPU processor system;
(2) The process of sending out the data block from the memory by the DMA controller is as follows:
(2a) After the CPU processor system data processing is completed, a new data message is generated and stored in the DDR space, the data message and the corresponding address information are read from the DDR space and sent to the DMA controller;
(2b) After receiving the data message sent by the CPU processor system, the DMA controller assembles a message format and sends the message format through the hardware forwarding module, after the sending is completed, a completion mark is fed back to the CPU processor system, and the CPU processor system obtains mark information in a polling mode.
Further, the data storage format of the DDR space is { next ptr, eop, pkt_len, pkt_data }, next ptr represents the next pointer, eop represents the end-of-packet symbol, pkt_len represents the packet length, and pkt_data represents the packet data.
Further, in the step (1 c), when the processor core issues the DDR address to the DMA controller, the data length is determined, if the data length is smaller than the set value, the DDR address is directly issued to the DMA controller and the length information of the data block is determined to be transferred, and if the data length is greater than the set value, a one-hop idle pointer is applied to the DDR space, and the next-hop idle pointer is issued to the DMA controller by operating the register.
Further, the data messages in the DDR space are stored in a linked list form by taking 2KB/4KB as a unit, and each 2KB/4KB data message needs to have a next ptr and eop, and the next ptr and eop are stored in the starting position of the 2KB/4KB data message; the DMA controller performs byte insertion processing on the data message when storing the corresponding data in the DDR space in the form of a linked list, and the specific processing process is as follows: inserting the data message into a 32-bit space at intervals of 2KB/4KB, wherein 27 bits are next ptr,1bit is eop, and 4 bits are free space; where next ptr represents the next pointer and eop represents the end of message symbol.
Compared with the prior art, the invention has the following advantages:
(1) The invention supports configurable message storage granularity, either 2KB or 4 KB;
(2) The invention supports the CPU to apply DDR message storage space pointer to the DMA controller;
(3) The pointer DDR memory space size and the message DDR memory space size can be configured.
Drawings
FIG. 1 is a schematic diagram of the overall structure of a system according to an embodiment of the present invention;
FIG. 2 is a bit width insertion block diagram of an embodiment of the present invention;
Detailed Description
The invention is described in further detail below with reference to the drawings and examples.
Referring to fig. 1, a packet processing DMA system of a multi-core network processor includes an ethernet interface module, a hardware forwarding module, a DMA controller, a CPU processor system, and a DDR3/4 memory;
the Ethernet interface module is used for receiving the Ethernet message and sending the Ethernet message to the hardware forwarding module; and the message is received from the hardware forwarding module and sent out;
the hardware forwarding module is used for analyzing the Ethernet message and sending the analyzed message to the DMA controller; the message is received from the DMA controller for analysis and then is sent to the Ethernet interface module;
the DMA controller is used for generating a processor core ID for processing the message, sending a DMA request to the CPU processor system, receiving the DDR address sent by the CPU processor system and the length information for determining the transmission data block, and writing the corresponding data message into the DDR3/4 memory; the system is also used for receiving the data message sent by the CPU processor system, assembling the data message into a message format, sending the message format to the hardware forwarding module, and sending a DMA feedback completion mark to the CPU processor system;
the CPU processor system comprises a plurality of processor cores (16A 53 cores are arranged in the embodiment), wherein the processor Core A53Core 0 cores are used for distributing a DDR space in the DDR3/4 memory as a management idle pointer and adopting a linked list for management; the other processor cores are used for responding to the DMA request in a polling mode, after the DMA request sent to the corresponding processor core is polled, the corresponding processor core reads the DDR space to obtain an idle pointer, and sends down the DDR address and the length information for determining the data block to be transmitted to the DMA controller through the annular bus;
the DDR3/4 memory is used for storing data messages in a set format. The data storage format of the DDR3/4 memory is { next ptr, eop, pkt_len, pkt_data }, next ptr represents a next pointer, eop represents a message terminator, pkt_len represents a message length, and pkt_data represents message data.
A message processing method of a multi-core network processor comprises the following steps:
(1) The process of the DMA controller moving the data block to the memory is as follows:
(1a) After the multi-Core network processor chip is electrified, a DDR space is distributed by a processor Core A53Core 0 of the CPU processor system as a management idle pointer, and the management is carried out by adopting a linked list;
(1b) The Ethernet interface module receives the message and sends the message to the hardware forwarding module, the hardware forwarding module analyzes the message and then sends the message to the DMA controller, and the DMA controller generates a processor core ID for processing the message and sends a DMA request to the CPU processor system;
(1c) The processor core of the CPU processor system responds to the DMA request in a polling mode, after the DMA request sent to the corresponding processor core is polled, the corresponding processor core reads the DDR space to acquire an idle pointer, and sends down the DDR address to the DMA controller and decides to transmit the length information of the data block through the annular bus; when the processor core issues the DDR address to the DMA controller, judging the data length, if the data length is smaller than a set value, directly issuing the DDR address to the DMA controller and determining the length information of a data block to be transmitted, if the data length is larger than the set value, applying a one-jump idle pointer to the DDR space, and issuing a next-jump idle pointer to the DMA controller in a mode of operating a register;
(1d) After receiving the related information of the DDR address, the DMA controller stores corresponding data into the DDR space in a linked list mode through an annular bus, executes the burst length of one operation, and the burst length can be configured;
referring to FIG. 2, the DMA controller is required to insert bytes into the off-chip stored message, and since the messages are stored in the DDR in linked list form in units of 2KB/4KB, there is a need for a next ptr and eop for each 2KB/4KB message. Next ptr and eop are stored at the beginning of the 2KB/4KB message data. It is necessary to insert 32 bits (27 bits are required for next ptr,1bit is required for loop, and 4 bits of free space) space reservation for an input message at intervals of 2KB/4KB to insert next ptr and eop. And (3) judging the position inserted into the 32-bit space by counting, counting the number of bytes of the off-chip message, and inserting the 32-bit space every 4K-4 or 2K-4 bytes. For the first 32bit inserted into a message, the 32bit needs to be inserted after pkt_len, so that the module can accurately identify the queue number and whether the message is an off-chip storage message when the on-chip and off-chip messages are processed uniformly. After 32 bits are inserted, the data bit width is changed from 64 bits to 96 bits, and the data is converted into 1024 bits and aligned. In the figure, sop indicates a message start symbol, eop indicates a message end symbol, queue_no indicates which queue the currently input message belongs to, and interface_flag indicates whether or not the message is an off-chip storage message.
(1e) The DMA controller sends operation ending information to a processor core corresponding to the CPU processor system;
(2) The process of sending out the data block from the memory by the DMA controller is as follows:
(2a) After the CPU processor system data processing is completed, a new data message is generated and stored in the DDR space, the data message and the corresponding address information are read from the DDR space and sent to the DMA controller through the annular bus;
(2b) After receiving the data message sent by the CPU processor system, the DMA controller assembles a message format and sends the message format through the hardware forwarding module, after the sending is completed, a completion mark is fed back to the CPU processor system, and the CPU processor system obtains mark information in a polling mode.
Claims (6)
1. The message processing DMA system of the multi-core network processor is characterized by comprising an Ethernet interface module, a hardware forwarding module, a DMA controller, a CPU processor system and a DDR3/4 memory;
the Ethernet interface module is used for receiving the Ethernet message and sending the Ethernet message to the hardware forwarding module; and the message is received from the hardware forwarding module and sent out;
the hardware forwarding module is used for analyzing the Ethernet message and sending the analyzed message to the DMA controller; the message is received from the DMA controller for analysis and then is sent to the Ethernet interface module;
the DMA controller is used for generating a processor core ID for processing the message, sending a DMA request to the CPU processor system, receiving the DDR address sent by the CPU processor system and the length information for determining the transmission data block, and writing the corresponding data message into the DDR3/4 memory; the system is also used for receiving the data message sent by the CPU processor system, assembling the data message into a message format, sending the message format to the hardware forwarding module, and sending a DMA feedback completion mark to the CPU processor system;
the CPU processor system comprises a plurality of processor cores, wherein one processor core is used for distributing a DDR space in the DDR3/4 memory for managing idle pointers and adopting a linked list for management; the other processor cores are used for responding to the DMA request in a polling mode, after the DMA request sent to the corresponding processor core is polled, the corresponding processor core reads the DDR space to obtain an idle pointer, and sends down the DDR address and the length information for determining the data block to be transmitted to the DMA controller through the annular bus;
the DDR3/4 memory is used for storing data messages in a set format.
2. The DMA system of claim 1 wherein the DDR3/4 memory has a data storage format { next ptr, eop, pkt_len, pkt_data }, next ptr representing a next pointer, eop representing a message terminator, pkt_len representing a message length, and pkt_data representing message data.
3. The message processing method of the multi-core network processor is characterized by comprising the following steps of:
(1) The process of the DMA controller moving the data block to the memory is as follows:
(1a) After the multi-core network processor chip is electrified, one processor core of the CPU processor system allocates a DDR space for managing the idle pointer and adopts a linked list for management;
(1b) The Ethernet interface module receives the message and sends the message to the hardware forwarding module, the hardware forwarding module analyzes the message and then sends the message to the DMA controller, and the DMA controller generates a processor core ID for processing the message and sends a DMA request to the CPU processor system;
(1c) The processor core of the CPU processor system responds to the DMA request in a polling mode, after the DMA request sent to the corresponding processor core is polled, the corresponding processor core reads the DDR space to acquire an idle pointer, and issues a DDR address to the DMA controller and decides to transmit the length information of the data block;
(1d) After receiving the related information of the DDR address, the DMA controller stores corresponding data in a DDR space in a linked list mode, and executes the burst length of one operation, wherein the burst length is configured according to the requirement;
(1e) The DMA controller sends operation ending information to a processor core corresponding to the CPU processor system;
(2) The process of sending out the data block from the memory by the DMA controller is as follows:
(2a) After the CPU processor system data processing is completed, a new data message is generated and stored in the DDR space, the data message and the corresponding address information are read from the DDR space and sent to the DMA controller;
(2b) After receiving the data message sent by the CPU processor system, the DMA controller assembles a message format and sends the message format through the hardware forwarding module, after the sending is completed, a completion mark is fed back to the CPU processor system, and the CPU processor system obtains mark information in a polling mode.
4. A method for processing a message in a multi-core network processor according to claim 3, wherein the data storage format in the DDR space is { next ptr, eop, pkt_len, pkt_data }, next ptr represents a next pointer, eop represents a message terminator, pkt_len represents a message length, and pkt_data represents message data.
5. The method for processing a packet in a multi-core network processor according to claim 3, wherein in step (1 c), when the processor core issues a DDR address to the DMA controller, the processor core determines a data length, if the data length is smaller than a set value, directly issues the DDR address to the DMA controller and determines to transfer length information of a data block, and if the data length is greater than the set value, then applies for a next-hop idle pointer to the DDR space, and issues the next-hop idle pointer to the DMA controller by operating a register.
6. A method for processing a message in a multi-core network processor according to claim 3, wherein the data message in the DDR space is stored in a linked list form in units of 2KB/4KB, each 2KB/4KB data message needs to have a next ptr and eop, and the next ptr and eop are stored in the starting position of the 2KB/4KB data message; the DMA controller performs byte insertion processing on the data message when storing the corresponding data in the DDR space in the form of a linked list, and the specific processing process is as follows: inserting the data message into a 32-bit space at intervals of 2KB/4KB, wherein 27 bits are next ptr,1bit is eop, and 4 bits are free space; where next ptr represents the next pointer and eop represents the end of message symbol.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210091507.7A CN114490467B (en) | 2022-01-26 | 2022-01-26 | Message processing DMA system and method of multi-core network processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210091507.7A CN114490467B (en) | 2022-01-26 | 2022-01-26 | Message processing DMA system and method of multi-core network processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114490467A CN114490467A (en) | 2022-05-13 |
| CN114490467B true CN114490467B (en) | 2024-03-19 |
Family
ID=81475346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210091507.7A Active CN114490467B (en) | 2022-01-26 | 2022-01-26 | Message processing DMA system and method of multi-core network processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114490467B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115190175B (en) * | 2022-07-18 | 2023-07-14 | 浪潮(北京)电子信息产业有限公司 | Connection processing method, system, electronic device, server and readable storage medium |
| CN115529275B (en) * | 2022-11-28 | 2023-04-07 | 中国人民解放军国防科技大学 | Message processing system and method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1517881A (en) * | 2003-01-06 | 2004-08-04 | ض� | Memory management free pointer library |
| CN1741455A (en) * | 2004-08-29 | 2006-03-01 | 中兴通讯股份有限公司 | Method for controlling PCI device utilizing network processor micro-engine |
| JP2010211322A (en) * | 2009-03-06 | 2010-09-24 | Renesas Electronics Corp | Network processor, reception controller, and data reception processing method |
| CN105511954A (en) * | 2014-09-23 | 2016-04-20 | 华为技术有限公司 | Method and device for message processing |
| CN109219805A (en) * | 2017-05-08 | 2019-01-15 | 华为技术有限公司 | A kind of multiple nucleus system memory pool access method, relevant apparatus, system and storage medium |
| CN111221759A (en) * | 2020-01-17 | 2020-06-02 | 深圳市风云实业有限公司 | Data processing system and method based on DMA |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7990987B2 (en) * | 2003-02-25 | 2011-08-02 | Topside Research, Llc | Network processor having bypass capability |
| US7613813B2 (en) * | 2004-09-10 | 2009-11-03 | Cavium Networks, Inc. | Method and apparatus for reducing host overhead in a socket server implementation |
| US20140334336A1 (en) * | 2013-05-10 | 2014-11-13 | Relay2, Inc. | Multi-Tenant Virtual Access Point- Network Resources Virtualization |
-
2022
- 2022-01-26 CN CN202210091507.7A patent/CN114490467B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1517881A (en) * | 2003-01-06 | 2004-08-04 | ض� | Memory management free pointer library |
| CN1741455A (en) * | 2004-08-29 | 2006-03-01 | 中兴通讯股份有限公司 | Method for controlling PCI device utilizing network processor micro-engine |
| JP2010211322A (en) * | 2009-03-06 | 2010-09-24 | Renesas Electronics Corp | Network processor, reception controller, and data reception processing method |
| CN105511954A (en) * | 2014-09-23 | 2016-04-20 | 华为技术有限公司 | Method and device for message processing |
| CN109219805A (en) * | 2017-05-08 | 2019-01-15 | 华为技术有限公司 | A kind of multiple nucleus system memory pool access method, relevant apparatus, system and storage medium |
| CN111221759A (en) * | 2020-01-17 | 2020-06-02 | 深圳市风云实业有限公司 | Data processing system and method based on DMA |
Non-Patent Citations (1)
| Title |
|---|
| 多核网络处理器共享存储控制系统设计与优化;彭毓佳;中国优秀硕士学位论文全文数据库 信息科技辑(2013第04期);第19-64页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114490467A (en) | 2022-05-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114490467B (en) | Message processing DMA system and method of multi-core network processor | |
| CN100470517C (en) | System and method for information handling system PCI express advanced switching | |
| CN107204110B (en) | Method for rapidly reading meter data based on broadband network | |
| CN111651377A (en) | Elastic shared cache architecture for on-chip message processing | |
| CN110177013A (en) | A kind of EtherCAT master-salve station design and implementation methods based on FPGA | |
| EP0223460B1 (en) | Real-time end of packet signal generator | |
| CN101894092A (en) | Multi-core CPU and inter-core communication method thereof | |
| CN111800226B (en) | Sideband management circuit and method based on hardware arbitration | |
| CN108462620B (en) | Gilbert-level SpaceWire bus system | |
| CN113852533B (en) | Multi-channel data communication system and method and electronic equipment | |
| CN113452591B (en) | Loop control method and device based on CAN bus continuous data frame | |
| CN108614792B (en) | 1394 transaction layer data packet storage management method and circuit | |
| CN113676386B (en) | FC-AE-1553 bus protocol message communication system | |
| CN113542148A (en) | Message aggregation method and device, network card and readable storage medium | |
| CN103560982B (en) | Bag apparatus and method is cut for what Interlaken enhancement mode was dispatched | |
| CN113141322A (en) | Data communication method, data communication device and computer storage medium | |
| CN112422485B (en) | Communication method and device of transmission control protocol | |
| CN103106177B (en) | Interconnect architecture and method thereof on the sheet of multi-core network processor | |
| CN103178943A (en) | Method, device and system for link adaption | |
| CN110830386B (en) | Message order preserving method, device and system | |
| CN117033296A (en) | Internal unified communication system and method for multi-CPU board card device | |
| CN114095901A (en) | Communication data processing method and device | |
| CN102932265A (en) | Data caching management device and method | |
| EP4322016A1 (en) | Integrated circuit, and data processing apparatus and method | |
| WO2022127448A1 (en) | Message transmission method, terminals and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |