CN114477779A - Multilayer glass substrate process and structure based on heterogeneous bonding - Google Patents

Multilayer glass substrate process and structure based on heterogeneous bonding Download PDF

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Publication number
CN114477779A
CN114477779A CN202111661338.8A CN202111661338A CN114477779A CN 114477779 A CN114477779 A CN 114477779A CN 202111661338 A CN202111661338 A CN 202111661338A CN 114477779 A CN114477779 A CN 114477779A
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Prior art keywords
glass substrate
layer
metal
multilayer glass
heterogeneous bonding
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CN202111661338.8A
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CN114477779B (en
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张名川
阮文彪
于大全
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Xiamen Yun Tian Semiconductor Technology Co ltd
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Xiamen Yun Tian Semiconductor Technology Co ltd
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    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C15/00—Surface treatment of glass, not in the form of fibres or filaments, by etching
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C17/00—Surface treatment of glass, not in the form of fibres or filaments, by coating
    • C03C17/22—Surface treatment of glass, not in the form of fibres or filaments, by coating with other inorganic material
    • C03C17/23—Oxides
    • C03C17/245—Oxides by deposition from the vapour phase
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C27/00—Joining pieces of glass to pieces of other inorganic material; Joining glass to glass other than by fusing
    • C03C27/06—Joining glass to glass by processes other than fusing
    • C03C27/08—Joining glass to glass by processes other than fusing with the aid of intervening metal
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C2217/00—Coatings on glass
    • C03C2217/20—Materials for coating a single layer on glass
    • C03C2217/21—Oxides
    • C03C2217/213—SiO2
    • C—CHEMISTRY; METALLURGY
    • C03—GLASS; MINERAL OR SLAG WOOL
    • C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
    • C03C2218/00—Methods for coating glass
    • C03C2218/10—Deposition methods
    • C03C2218/15—Deposition methods from the vapour phase
    • C03C2218/152—Deposition methods from the vapour phase by cvd

Abstract

The invention discloses a multilayer glass substrate process based on heterogeneous bonding, which comprises the steps of etching a groove on the surface of a glass substrate, depositing metal to form a metal circuit in the groove, and then covering an inorganic medium layer; then, manufacturing a Via connection structure connected with the metal circuit to obtain a single-layer unit; and (3) according to the wiring requirement, stacking at least two single-layer units up and down, enabling the Via connection structures to correspond, and forming the multilayer glass substrate through glass/metal heterogeneous bonding. The invention realizes the glass substrate structure embedded with multilayer wiring, can realize the line width and line distance of thin lines, meets the requirement of high-density wiring, and has better performance and wider application.

Description

Multilayer glass substrate process and structure based on heterogeneous bonding
Technical Field
The invention relates to the technical field of semiconductor packaging substrates, in particular to a multilayer glass substrate process and structure based on heterogeneous bonding.
Background
With the increasing requirements for high performance, small size, high reliability and ultra-low power consumption in chips and electronic products, the development of packaging technology is promoted. Compared with substrates made of other materials, the glass substrate can solve the problems of insufficient wiring density of an organic substrate and the like, and realizes higher-density interconnection between chips and between the chips and a packaging substrate.
In the application of the conventional glass substrate for packaging, a conductive column penetrating through the thickness direction is usually formed on the glass substrate, and interconnection of wiring layers on two opposite surfaces of the glass substrate is realized through the conductive column. With diversification of integrated circuit applications, the demand for three-dimensional integrated advanced packaging is more and more strong, and how to realize a multilayer rewiring structure of a glass substrate becomes a difficult problem.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a multilayer glass substrate process and structure based on heterogeneous bonding.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
a multilayer glass substrate process based on heterogeneous bonding comprises the following steps:
1) etching a groove on the upper surface of the glass substrate, and depositing metal to form a metal circuit in the groove;
2) depositing an inorganic medium layer on the upper surface of the glass substrate;
3) etching Via holes on the upper surface and the lower surface of the glass substrate respectively, filling metal to manufacture a Via connection structure connected with the metal circuit, and obtaining a single-layer unit;
4) manufacturing at least two single-layer units according to the wiring requirements and the methods of the steps 1) to 3); and (3) stacking at least two single-layer units up and down, enabling the Via connection structures to correspond, and forming the multilayer glass substrate through heterogeneous bonding.
Optionally, in step 1), a plating process is used to deposit metal in the trench, and then a CMP process is used to planarize the metal to be flush with the upper surface of the glass substrate.
Optionally, the inorganic dielectric layer is SiO2A layer or SiN layer with a thickness of 0.1-5 um.
Optionally, in step 3), metal is deposited in the Via holes of the upper and lower surfaces respectively by using an electroplating process, and then the metal is planarized by using a CMP process until the metal is flush with the upper and lower surfaces of the glass substrate respectively to form the Via connection structure.
Optionally, the heterogeneous bonding is to perform alignment and pre-bonding on a surface to be bonded at room temperature after activating the surface to be bonded, and then perform thermal annealing at 200-350 ℃.
Optionally, the method further includes a step of manufacturing a top rewiring layer and a bottom rewiring layer connected to the Via connection structure on the upper and lower surfaces of the multilayer glass substrate respectively.
Optionally, the method further includes the steps of manufacturing solder masks on the upper and lower surfaces of the multi-layer glass substrate, and manufacturing solder balls on the lower surface, wherein the solder balls are connected with the bottom rewiring layer.
Optionally, in step 1) and step 3), the metal is copper.
The multilayer glass substrate based on heterogeneous bonding prepared by the process comprises at least two single-layer units which are stacked up and down and pass through heterogeneous bonding, wherein each single-layer unit comprises a glass substrate and an inorganic medium layer arranged on the upper surface of the glass substrate, a metal circuit in the horizontal direction and a Via connection structure in the vertical direction are embedded in each single-layer unit, and the Via connection structures of the adjacent single-layer units are correspondingly connected.
The invention has the beneficial effects that:
1) the glass substrate structure with embedded multilayer wiring is realized, and compared with other material substrates, the glass substrate has lower dielectric loss; the line spacing of the thin line can be realized, and high-density wiring is met; the CTE is adjustable, and the reliability is better; the method has the advantages of compatibility with a wafer level process, higher flexibility and the like, and has better performance and wider application;
2) the multilayer glass substrate obtained by the process is integrated in structure, is realized by stacking basic units by adopting a semiconductor manufacturing process, and has simple and flexible process and high precision.
Drawings
Fig. 1 to 9 are schematic structural diagrams obtained by steps of a multilayer glass substrate process based on heterogeneous bonding according to an embodiment.
Detailed Description
The invention is further explained below with reference to the figures and the specific embodiments. The drawings are only schematic and can be easily understood, and the specific proportion can be adjusted according to design requirements. The definitions of the top and bottom relationships of the relative elements and the front and back sides of the figures described herein are understood by those skilled in the art to refer to the relative positions of the components and thus all of the components may be flipped to present the same components and still fall within the scope of the present disclosure.
Referring to fig. 1 to 9, in an embodiment of a multilayer glass substrate process based on heterogeneous bonding, at least two glass substrate single-layer units (taking 3 glass substrate single-layer units as an example) are first fabricated, and a multilayer glass substrate structure is formed through glass/metal heterogeneous bonding. In particular, the method comprises the steps of,
step 1, referring to fig. 1, a groove 1a is etched on the upper surface of a glass substrate 1, the glass substrate 1 is, for example, silicon dioxide glass, the thickness is 50 to 150um, and the depth of the groove 1a is 5um to 50 um;
step 2, referring to fig. 2, depositing metal in the trench 1a to form a metal line 2, depositing metal Cu in the trench 1a by seed layer sputtering, electroplating and other processes, and then thinning and flattening the metal Cu by a CMP (chemical mechanical polishing) process until the metal Cu is flush with the upper surface of the glass substrate 1, thereby obtaining a flat upper surface of the substrate;
step 3, referring to fig. 3, depositing SiO with a certain thickness on the upper surface of the substrate by CVD or the like2To obtain a complete layer of SiO2Layer 3 as an inorganic dielectric layer, SiO2The thickness of the layer 3 is 0.1um to 5 um;
step 4, refer to FIG. 4, in SiO2Etching Via holes on the layer 3 to expose part of the metal lines 2, filling metal to form upper Via connection structures 4 connected with the metal lines 2, depositing metal Cu in the Via holes by seed layer sputtering, electroplating and other processes, and then thinning and flattening the metal Cu by CMP (chemical mechanical polishing) process to SiO2The upper surface of the layer 3 is flush;
step 5, referring to fig. 5, etching Via holes exposing part of the metal lines 2 on the lower surface of the glass substrate 1, filling metal to manufacture a lower Via connection structure 5 connected with the metal lines 2, similarly, depositing metal Cu in the Via holes by seed layer sputtering, electroplating and other processes, and then thinning and flattening the metal Cu by a CMP (chemical mechanical polishing) process until the metal Cu is flush with the lower surface of the glass substrate 1;
through the steps 1 to 5, a glass substrate single-layer unit 100 is obtained, a metal circuit 2 with horizontal wiring and an upper Via connection structure 4 and a lower Via connection structure 5 which are vertically interconnected are embedded in the glass substrate, and rewiring in the glass substrate is realized; wherein SiO is adopted2Or a SiN layer having electrical properties similar to or better than glass, such as dielectric constant, loss, etc.; and can be used for the mixed bonding of copper/silicon oxide or copper/silicon nitride;
step 6, referring to fig. 6, according to the wiring requirements, the single- layer units 100, 200 and 300 are manufactured according to the method from step 1 to step 5;
step 7, referring to fig. 7, stacking the single- layer units 100, 200 and 300 up and down and making their Via connection structures correspond to each other, forming a multilayer glass substrate by glass/metal heterogeneous bonding, wherein the specific process of heterogeneous bonding is to firstly activate the surface to be bonded by adopting plasma or atomic beam and water vapor treatment modes, remove the natural oxide layer on the copper surface and increase the hydrophilicity of silicon oxide or silicon nitride; then aligning and pre-bonding the surface to be bonded at room temperature, and then thermally annealing under the condition of heating (200-350 ℃) to strengthen SiO2-SiO2Or SiN-SiN bonding degree, and forming a copper-copper bonding interface through internal stress generated by thermal expansion of copper and mutual diffusion of copper atoms;
step 8, referring to fig. 8, respectively manufacturing a top rewiring layer 6 and a bottom rewiring layer 7 connected with the corresponding Via connection structures on the upper surface and the lower surface of the multilayer glass substrate, wherein the adopted metal is copper;
step 9, referring to fig. 9, solder resists 8 are respectively formed on the upper and lower surfaces of the multilayer glass substrate, and solder balls 9 connected to the bottom rewiring layer 7 are formed on the lower surface.
Referring to fig. 9, the multilayer glass substrate structure based on glass/metal heterogeneous bonding obtained in this example includes 3 single- layer units 100, 200 and 300 stacked up and down and bonded through glass/metal heterogeneous bonding, each single-layer unit including a glass substrate 1 and SiO disposed on the upper surface of the glass substrate2Layer 3, metal embedded in single layer unit in horizontal directionThe circuit 2, an upper Via connection structure 4 and a lower Via connection structure 5 in the vertical direction are correspondingly connected, and the Via connection structures of the adjacent single-layer units are correspondingly connected; the upper surface of the multilayer glass substrate is also provided with a top rewiring layer 6 and a solder mask layer 8, and the pad structure can be Cu + OSP or Cu + NiAu; the lower surface of the multilayer glass substrate is also provided with a bottom rewiring layer 7, a solder mask layer 8 and solder balls 9.
Three-dimensional wiring is realized through the metal circuits of the single-layer units, the upper and lower Via connection structures, the top rewiring layer and the bottom rewiring layer; the glass substrate single-layer units are integrally connected through plane-plane butt-joint bonding, so that the glass substrate single-layer units have good mechanical property and electrical property, can exert lower dielectric loss of the glass substrate, can realize fine line width and line distance, meets the advantages of high-density wiring, adjustable CTE (coefficient of thermal expansion), better reliability, compatibility with wafer-level processes, higher flexibility and the like, and meets the requirement of high-performance complicated packaging. The semiconductor manufacturing process is adopted and is realized by stacking basic units, and the process is simple and flexible and has high precision.
The above embodiments are only used to further illustrate the process and structure of the present invention for a multilayer glass substrate based on heterogeneous bonding, but the present invention is not limited to the embodiments, and any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical spirit of the present invention fall within the protection scope of the technical solution of the present invention.

Claims (9)

1. A multilayer glass substrate process based on heterogeneous bonding is characterized by comprising the following steps:
1) etching a groove on the upper surface of the glass substrate, and depositing metal to form a metal circuit in the groove;
2) depositing an inorganic medium layer on the upper surface of the glass substrate;
3) etching Via holes on the upper surface and the lower surface of the glass substrate respectively, filling metal to manufacture a Via connection structure connected with the metal circuit, and obtaining a single-layer unit;
4) manufacturing at least two single-layer units according to the wiring requirements and the methods of the steps 1) to 3); and (3) stacking at least two single-layer units up and down, enabling the Via connection structures to correspond, and forming the multilayer glass substrate through heterogeneous bonding.
2. The multilayer glass substrate process based on heterogeneous bonding according to claim 1, wherein: in the step 1), metal is deposited in the groove by adopting an electroplating process, and then the metal is flattened to be flush with the upper surface of the glass substrate by adopting a CMP process.
3. The multilayer glass substrate process based on heterogeneous bonding according to claim 1, wherein: the inorganic medium layer is SiO2A layer or SiN layer with a thickness of 0.1-5 um.
4. The multilayer glass substrate process based on heterogeneous bonding according to claim 1, wherein: in the step 3), metals are respectively deposited in the Via holes of the upper surface and the lower surface by adopting an electroplating process, and then the metals are flattened by adopting a CMP process until the metals are respectively flush with the upper surface and the lower surface of the glass substrate to form the Via connecting structure.
5. The multilayer glass substrate process based on heterogeneous bonding according to claim 1, wherein: and the heterogeneous bonding is to perform alignment and pre-bonding on a surface to be bonded at room temperature after activating the surface to be bonded, and then perform thermal annealing at 200-350 ℃.
6. The multilayer glass substrate process based on heterogeneous bonding according to claim 1, wherein: and the step of respectively manufacturing a top rewiring layer and a bottom rewiring layer which are connected with the Via connecting structure on the upper surface and the lower surface of the multilayer glass substrate.
7. The multilayer glass substrate process based on heterogeneous bonding according to claim 6, wherein: the method also comprises the steps of manufacturing solder masks on the upper surface and the lower surface of the multilayer glass substrate respectively, and manufacturing solder balls connected with the bottom rewiring layer on the lower surface.
8. The multilayer glass substrate process based on heterogeneous bonding according to claim 1, wherein: in step 1) and step 3), the metal is copper.
9. A multilayer glass substrate based on heterogeneous bonding prepared by the process according to any one of claims 1 to 8, wherein: including upper and lower pile and establish and through two at least individual layer units of heterogeneous bonding, the individual layer unit includes glass substrate and the inorganic dielectric layer of locating the glass substrate upper surface, the individual layer unit embeds establishes the metal wire of horizontal direction and the Via connection structure of vertical direction, and the Via connection structure of adjacent individual layer unit corresponds and connects.
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184121B1 (en) * 1997-07-10 2001-02-06 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
WO2001099182A2 (en) * 2000-06-21 2001-12-27 Infineon Technologies North America Corp. Insitu diffusion barrier and copper metallization for improving reliability of semiconductor devices
US20020053730A1 (en) * 2000-10-24 2002-05-09 Naohiro Mashino Semiconductor device and production process thereof
US20060105565A1 (en) * 2004-11-12 2006-05-18 Chi-Wen Liu Method and apparatus for copper film quality enhancement with two-step deposition
US20080070410A1 (en) * 2006-09-13 2008-03-20 Dongbu Hitek Co., Ltd. Method for manufacturing capacitor using system in package
US20140127900A1 (en) * 2012-11-02 2014-05-08 Jingxun FANG Method of forming cu interconnects
CN106571334A (en) * 2016-10-26 2017-04-19 上海集成电路研发中心有限公司 Silicon wafer hybrid bonding method
US20210118698A1 (en) * 2018-06-08 2021-04-22 Toppan Printing Co.,Ltd. Method for manufacturing glass device, and glass device
US20210159177A1 (en) * 2019-11-27 2021-05-27 Mediatek Inc. Semiconductor package structure

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184121B1 (en) * 1997-07-10 2001-02-06 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
WO2001099182A2 (en) * 2000-06-21 2001-12-27 Infineon Technologies North America Corp. Insitu diffusion barrier and copper metallization for improving reliability of semiconductor devices
US20020053730A1 (en) * 2000-10-24 2002-05-09 Naohiro Mashino Semiconductor device and production process thereof
US20060105565A1 (en) * 2004-11-12 2006-05-18 Chi-Wen Liu Method and apparatus for copper film quality enhancement with two-step deposition
US20080070410A1 (en) * 2006-09-13 2008-03-20 Dongbu Hitek Co., Ltd. Method for manufacturing capacitor using system in package
US20140127900A1 (en) * 2012-11-02 2014-05-08 Jingxun FANG Method of forming cu interconnects
CN106571334A (en) * 2016-10-26 2017-04-19 上海集成电路研发中心有限公司 Silicon wafer hybrid bonding method
US20210118698A1 (en) * 2018-06-08 2021-04-22 Toppan Printing Co.,Ltd. Method for manufacturing glass device, and glass device
US20210159177A1 (en) * 2019-11-27 2021-05-27 Mediatek Inc. Semiconductor package structure

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