CN114477779B - Multi-layer glass substrate process and structure based on heterogeneous bonding - Google Patents
Multi-layer glass substrate process and structure based on heterogeneous bonding Download PDFInfo
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- CN114477779B CN114477779B CN202111661338.8A CN202111661338A CN114477779B CN 114477779 B CN114477779 B CN 114477779B CN 202111661338 A CN202111661338 A CN 202111661338A CN 114477779 B CN114477779 B CN 114477779B
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- layer
- glass substrate
- metal
- heterobonding
- layer glass
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Classifications
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C15/00—Surface treatment of glass, not in the form of fibres or filaments, by etching
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C17/00—Surface treatment of glass, not in the form of fibres or filaments, by coating
- C03C17/22—Surface treatment of glass, not in the form of fibres or filaments, by coating with other inorganic material
- C03C17/23—Oxides
- C03C17/245—Oxides by deposition from the vapour phase
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C27/00—Joining pieces of glass to pieces of other inorganic material; Joining glass to glass other than by fusing
- C03C27/06—Joining glass to glass by processes other than fusing
- C03C27/08—Joining glass to glass by processes other than fusing with the aid of intervening metal
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C2217/00—Coatings on glass
- C03C2217/20—Materials for coating a single layer on glass
- C03C2217/21—Oxides
- C03C2217/213—SiO2
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C2218/00—Methods for coating glass
- C03C2218/10—Deposition methods
- C03C2218/15—Deposition methods from the vapour phase
- C03C2218/152—Deposition methods from the vapour phase by cvd
Abstract
The invention discloses a multi-layer glass substrate process based on heterogeneous bonding, which is characterized in that a groove is etched on the surface of a glass substrate, metal is deposited in the groove to form a metal circuit, and then an inorganic medium layer is covered; then making a Via connection structure connected with the metal circuit to obtain a single-layer unit; and according to wiring requirements, stacking at least two single-layer units up and down, and enabling the Via connection structures to correspond to each other, and forming the multi-layer glass substrate through glass/metal heterobonding. The invention realizes the glass substrate structure embedded with multilayer wiring, can realize thin line width and line distance, satisfies high-density wiring, and has better performance and wider application.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging substrates, in particular to a multi-layer glass substrate process and structure based on heterobonding.
Background
With the increasing requirements of high performance, small size, high reliability and ultra-low power consumption in chips and electronic products, the packaging technology is promoted to break through and develop continuously. Compared with substrates made of other materials, the glass substrate can solve the problems of insufficient wiring density of the organic substrate and the like, and realizes higher-density interconnection between chips and between the chips and the packaging substrate.
In the prior art, a conductive post penetrating through the thickness direction is generally formed on a glass substrate, and interconnection of wiring layers on two opposite surfaces of the glass substrate is realized through the conductive post. With the diversification of integrated circuit applications, the demand for three-dimensional integrated advanced packaging is becoming stronger, and how to realize a multilayer rewiring structure of a glass substrate becomes a difficult problem.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a multi-layer glass substrate process and structure based on heterogeneous bonding.
In order to achieve the above object, the technical scheme of the present invention is as follows:
a multi-layer glass substrate process based on heterobonding, comprising the steps of:
1) Etching a groove on the upper surface of the glass substrate, and depositing metal into the groove to form a metal circuit;
2) Depositing an inorganic medium layer on the upper surface of the glass substrate;
3) Etching Via holes on the upper surface and the lower surface of the glass substrate respectively, and filling metal to manufacture a Via connection structure connected with a metal circuit to obtain a single-layer unit;
4) According to wiring requirements, manufacturing at least two single-layer units according to the methods of the steps 1) to 3); and stacking at least two single-layer units up and down, enabling the Via connection structures to correspond to each other, and forming the multi-layer glass substrate through heterobonding.
Optionally, in step 1), a metal is deposited in the trench using an electroplating process, and then planarized to be flush with the upper surface of the glass substrate using a CMP process.
Optionally, the inorganic medium layer is SiO 2 The thickness of the layer or SiN layer is 0.1 um-5 um.
Optionally, in step 3), metal is deposited in the Via holes on the upper and lower surfaces respectively by using an electroplating process, and then the metal is planarized by using a CMP process to be flush with the upper and lower surfaces of the glass substrate respectively to form the Via connection structure.
Optionally, the heterobonding is that after the surface to be bonded is activated, the surface to be bonded is aligned and pre-bonded at room temperature, and then is thermally annealed at 200-350 ℃.
Optionally, the method further comprises the step of manufacturing a top rewiring layer and a bottom rewiring layer which are connected with the Via connection structure on the upper surface and the lower surface of the multi-layer glass substrate respectively.
Optionally, the method further comprises the steps of manufacturing solder resists on the upper surface and the lower surface of the multi-layer glass substrate respectively, and manufacturing solder balls connected with the bottom rewiring layer on the lower surface.
Optionally, in step 1) and step 3), the metal is copper.
The multi-layer glass substrate based on heterogeneous bonding, which is prepared by the process, comprises at least two single-layer units which are stacked up and down and are bonded through heterogeneous bonding, wherein each single-layer unit comprises a glass substrate and an inorganic medium layer arranged on the upper surface of the glass substrate, a metal circuit in the horizontal direction and a Via connecting structure in the vertical direction are embedded in each single-layer unit, and the Via connecting structures of the adjacent single-layer units are correspondingly connected.
The beneficial effects of the invention are as follows:
1) The glass substrate structure embedded with the multilayer wiring is realized, and compared with substrates made of other materials, the glass substrate has lower dielectric loss; the thin line width and the line distance can be realized, and the high-density wiring is satisfied; the CTE is adjustable, and the reliability is better; the method is compatible with a wafer-level process, has the advantages of higher flexibility and the like, and has better performance and wider application;
2) The multilayer glass substrate obtained by the process is integrated in structure, is realized by stacking basic units by adopting a semiconductor manufacturing process, and has the advantages of simple and flexible process and high precision.
Drawings
Fig. 1 to 9 are schematic structural diagrams of steps of a heterojunction-based multi-layer glass substrate process according to an embodiment.
Detailed Description
The invention is further explained below with reference to the drawings and specific embodiments. The drawings of the present invention are merely schematic to facilitate understanding of the present invention, and specific proportions thereof may be adjusted according to design requirements. The definition of the context of the relative elements and the front/back of the figures described herein should be understood by those skilled in the art to refer to the relative positions of the elements and thus all the elements may be reversed to represent the same elements, which are all within the scope of the present disclosure.
Referring to fig. 1 to 9, in one embodiment of a multi-layer glass substrate process based on heterobonding, at least two single-layer glass substrate units (for example, 3 single-layer glass substrate units) are first fabricated, and a multi-layer glass substrate structure is formed by heterobonding glass/metal. In particular to a special-shaped glass fiber reinforced plastic composite material,
step 1, referring to FIG. 1, a trench 1a is etched on the upper surface of a glass substrate 1, wherein the glass substrate 1 is, for example, silica glass with a thickness of 50-150 um and a depth of 5-50 um of the trench 1 a;
step 2, referring to fig. 2, metal is deposited in the trench 1a to form a metal line 2, metal Cu is deposited in the trench 1a by a process such as seed layer sputtering, electroplating, etc., and then the metal Cu is thinned and planarized by a CMP (chemical mechanical polishing) process until it is flush with the upper surface of the glass substrate 1, thereby obtaining a flat upper surface of the substrate;
step 3, referring to FIG. 3, a certain thickness of SiO is deposited on the upper surface of the substrate by CVD or other process 2 Obtaining the whole SiO layer 2 Layer 3 as inorganic dielectric layer, siO 2 The thickness of the layer 3 is 0.1 um-5 um;
step 4, referring to FIG. 4, at SiO 2 The layer 3 is etched to expose a part of the metal line 2 to form Via holes, and the upper Via connection structure 4 connected with the metal line 2 is made by filling metal, and similarly, metal Cu is deposited in the Via holes by seed layer sputtering, electroplating, etc., and then the metal Cu is thinned and planarized by CMP (chemical mechanical polishing) process to SiO 2 The upper surface of layer 3 is flush;
step 5, referring to fig. 5, etching Via holes exposing part of the metal circuit 2 on the lower surface of the glass substrate 1, filling metal to make a lower Via connection structure 5 connected with the metal circuit 2, depositing metal Cu in the Via holes by processes such as seed layer sputtering, electroplating, etc., and then thinning and planarizing the metal Cu by CMP (chemical mechanical polishing) process until the metal Cu is flush with the lower surface of the glass substrate 1;
through the steps 1 to 5, a glass substrate single-layer unit 100 is obtained, a metal circuit 2 with horizontal wiring, an upper Via connecting structure 4 and a lower Via connecting structure 5 which are vertically interconnected are embedded in a glass substrate, and rewiring in the glass substrate is realized; wherein SiO is adopted 2 Or SiN layer, with and glass typeSimilar or better electrical properties, such as dielectric constant, loss, etc.; and can be used for copper/silicon oxide or copper/silicon nitride hybrid bonding;
step 6, referring to fig. 6, single-layer units 100, 200 and 300 are manufactured according to the wiring requirements and the methods from step 1 to step 5;
step 7, referring to fig. 7, stacking single-layer units 100, 200 and 300 up and down and making their Via connection structures correspond, forming a multi-layer glass substrate by glass/metal heterogeneous bonding, wherein the specific process of heterogeneous bonding is to activate the surface to be bonded by adopting a plasma or atomic beam and water vapor treatment mode, removing the natural oxide layer on the copper surface and increasing the hydrophilicity of silicon oxide or silicon nitride; then aligning and pre-bonding the surface to be bonded at room temperature, and thermally annealing under the condition of heating (200-350 ℃) to strengthen SiO 2 -SiO 2 Or SiN-SiN bonding degree, and forming a copper-copper bonding interface through internal stress generated by thermal expansion of copper and interdiffusion of copper atoms;
step 8, referring to fig. 8, respectively manufacturing a top rewiring layer 6 and a bottom rewiring layer 7 connected with corresponding Via connection structures on the upper surface and the lower surface of the multi-layer glass substrate, wherein the adopted metal is copper;
step 9, referring to fig. 9, solder resists 8 are formed on the upper and lower surfaces of the multi-layered glass substrate, respectively, and solder balls 9 connected to the bottom rewiring layer 7 are formed on the lower surface.
Referring to FIG. 9, the multi-layered glass substrate structure based on glass/metal heterobonding according to the present embodiment comprises 3 single-layer units 100, 200 and 300 stacked up and down and bonded by glass/metal heterobonding, each single-layer unit comprising a glass substrate 1 and SiO provided on the upper surface of the glass substrate 2 The layer 3 is characterized in that a metal circuit 2 in the horizontal direction, an upper Via connecting structure 4 and a lower Via connecting structure 5 in the vertical direction are embedded in each single-layer unit, and the Via connecting structures of the adjacent single-layer units are correspondingly connected; the upper surface of the multilayer glass substrate is also provided with a top rewiring layer 6 and a solder mask layer 8, and the bonding pad structure can be Cu+OSP or Cu+NiAu; the lower surface of the multi-layer glass substrate is also provided with a bottom rewiring layer 7, a solder resist layer 8 and solder balls 9.
Three-dimensional wiring is realized through the metal circuits of each single-layer unit, the upper Via connecting structure, the lower Via connecting structure, the top rewiring layer and the bottom rewiring layer; the integrated connection is realized through the planar-planar butt bonding of the single-layer units of the glass substrates, the integrated connection has better mechanical property and electrical property, the lower dielectric loss of the glass substrates can be exerted, the thin line width and the line distance can be realized, the high-density wiring is met, the CTE is adjustable, the reliability is better, the advantages of compatibility with wafer-level technology, higher flexibility and the like are realized, and the requirement of high-performance complex packaging is met. The semiconductor manufacturing process is realized by stacking basic units, and the process is simple and flexible and has high precision.
The above embodiments are only used to further illustrate a heterogeneous bonding-based multi-layer glass substrate process and structure of the present invention, but the present invention is not limited to the embodiments, and any simple modification, equivalent variation and modification made to the above embodiments according to the technical substance of the present invention falls within the scope of the technical solution of the present invention.
Claims (7)
1. A multi-layer glass substrate process based on heterobonding, comprising the steps of:
1) Etching a groove on the upper surface of the glass substrate, depositing metal in the groove to form a metal circuit of a horizontal wiring, and flattening the metal to be level with the upper surface of the glass substrate;
2) Depositing an inorganic medium layer on the upper surface of the glass substrate, wherein the inorganic medium layer is SiO 2 The thickness of the layer or SiN layer is 0.1 um-5 um;
3) Etching Via holes on the upper surface and the lower surface of the glass substrate respectively, and filling metal to manufacture a Via connection structure in the vertical direction connected with the metal circuit, so as to obtain a single-layer unit;
4) According to wiring requirements, manufacturing at least two single-layer units according to the method of the steps 1) to 3); and stacking at least two single-layer units up and down and enabling the Via connection structures to correspond to each other, activating the surface to be bonded, aligning and pre-bonding the surface to be bonded at room temperature, thermally annealing at 200-350 ℃, and forming the multi-layer glass substrate through heterogeneous bonding.
2. The heterobonding-based multi-layer glass substrate process of claim 1, wherein: in step 1), metal is deposited in the grooves by adopting an electroplating process, and then the metal is planarized to be level with the upper surface of the glass substrate by adopting a CMP process.
3. The heterobonding-based multi-layer glass substrate process of claim 1, wherein: in the step 3), metal is deposited in the Via holes on the upper surface and the lower surface respectively by adopting an electroplating process, and then the metal is flattened to be level with the upper surface and the lower surface of the glass substrate respectively by adopting a CMP process, so that the Via connection structure is formed.
4. The heterobonding-based multi-layer glass substrate process of claim 1, wherein: and the method further comprises the step of respectively manufacturing a top rewiring layer and a bottom rewiring layer which are connected with the Via connection structure on the upper surface and the lower surface of the multi-layer glass substrate.
5. The heterobonding-based multi-layer glass substrate process of claim 4, wherein: and a step of manufacturing solder masks on the upper and lower surfaces of the multi-layer glass substrate, respectively, and manufacturing solder balls connected with the bottom rewiring layer on the lower surface.
6. The heterobonding-based multi-layer glass substrate process of claim 1, wherein: in step 1) and step 3), the metal is copper.
7. The heterobond-based multi-layer glass substrate prepared by the process of any one of claims 1-6, wherein: the glass substrate comprises at least two single-layer units which are stacked up and down and are in heterogeneous bonding through plane-plane butt joint, wherein each single-layer unit comprises a glass substrate and an inorganic medium layer arranged on the upper surface of the glass substrate, a metal circuit in the horizontal direction and a Via connecting structure in the vertical direction are embedded in each single-layer unit, and the Via connecting structures of the adjacent single-layer units are correspondingly connected.
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| CN202111661338.8A CN114477779B (en) | 2021-12-30 | 2021-12-30 | Multi-layer glass substrate process and structure based on heterogeneous bonding |
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| US6184121B1 (en) * | 1997-07-10 | 2001-02-06 | International Business Machines Corporation | Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same |
| WO2001099182A2 (en) * | 2000-06-21 | 2001-12-27 | Infineon Technologies North America Corp. | Insitu diffusion barrier and copper metallization for improving reliability of semiconductor devices |
| CN106571334A (en) * | 2016-10-26 | 2017-04-19 | 上海集成电路研发中心有限公司 | Silicon wafer hybrid bonding method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2002134658A (en) * | 2000-10-24 | 2002-05-10 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| US7189650B2 (en) * | 2004-11-12 | 2007-03-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for copper film quality enhancement with two-step deposition |
| KR100741917B1 (en) * | 2006-09-13 | 2007-07-24 | 동부일렉트로닉스 주식회사 | Method for manufacturing capacitor by using sip |
| US8772157B2 (en) * | 2012-11-02 | 2014-07-08 | Shanghai Huali Microelectronics Corporation | Method of forming Cu interconnects |
| JP7298603B2 (en) * | 2018-06-08 | 2023-06-27 | 凸版印刷株式会社 | Glass device manufacturing method |
| US20210159177A1 (en) * | 2019-11-27 | 2021-05-27 | Mediatek Inc. | Semiconductor package structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6184121B1 (en) * | 1997-07-10 | 2001-02-06 | International Business Machines Corporation | Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same |
| WO2001099182A2 (en) * | 2000-06-21 | 2001-12-27 | Infineon Technologies North America Corp. | Insitu diffusion barrier and copper metallization for improving reliability of semiconductor devices |
| CN106571334A (en) * | 2016-10-26 | 2017-04-19 | 上海集成电路研发中心有限公司 | Silicon wafer hybrid bonding method |
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