CN114220745A - Back-to-face wafer-level hybrid bonding three-dimensional stacking method - Google Patents

Back-to-face wafer-level hybrid bonding three-dimensional stacking method Download PDF

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Publication number
CN114220745A
CN114220745A CN202111534068.4A CN202111534068A CN114220745A CN 114220745 A CN114220745 A CN 114220745A CN 202111534068 A CN202111534068 A CN 202111534068A CN 114220745 A CN114220745 A CN 114220745A
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wafer
bonding
face
stacking method
dimensional stacking
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CN202111534068.4A
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戴风伟
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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Priority to CN202111534068.4A priority Critical patent/CN114220745A/en
Publication of CN114220745A publication Critical patent/CN114220745A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H01L2221/68386—Separation by peeling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

Abstract

The invention relates to a back-to-face wafer-level hybrid bonding three-dimensional stacking method, which comprises the following steps: providing a first wafer; the first wafer comprises a through silicon via positioned in the first wafer, a first interconnecting line positioned on the front surface of the first wafer, a first bonding pad positioned on the first interconnecting line, and a first passivation protective layer wrapping the first interconnecting line and the first bonding pad; thinning the back surface of the first wafer to expose the through silicon via; manufacturing a second interconnection line, a second bonding pad and a second passivation protective layer on the back of the first wafer; carrying out chemical mechanical polishing on the front surface of the second wafer to expose a third bonding pad; and carrying out hybrid bonding on the back surface of the first wafer and the front surface of the second wafer.

Description

Back-to-face wafer-level hybrid bonding three-dimensional stacking method
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a back-to-face wafer-level hybrid bonding three-dimensional stacking method.
Background
The wafer bonding technology is that two mirror polished homogeneous or heterogeneous wafers are tightly combined through chemical and physical actions, and after the wafers are combined, atoms on an interface are acted by external force to react to form covalent bonds to be combined into a whole, so that the combined interface achieves specific bonding strength. Hybrid bonding (including insulator-insulator bonding, semiconductor-semiconductor bonding, and metal-metal bonding) is a common wafer bonding method, and is widely used in the field of 3D chips.
Wafer-level hybrid bonding stacking based on Through Silicon Vias (TSVs) requires manufacturing of bonding pads and Chemical Mechanical Polishing (CMP) processing aiming at the front and back surfaces of a thin wafer (20-100um), the integration process has very high requirements on flatness and warpage of the surface of the wafer, the conventional temporary bonding process is mostly adopted to process the back surface of the wafer in the existing scheme, but the process cannot be carried out due to the fact that the flatness (thickness deviation TTV is less than 3um) and the warpage of the wafer (less than 30um) cannot meet the process requirements, and the temporary bonding material cannot bear the temperature of hybrid bonding and annealing process (250 and 400 ℃), so that the process cannot be carried out. Furthermore, conventional bonding schemes, in which at least one layer of chips is bonded face-to-face, add complexity to the design and routing.
Disclosure of Invention
The invention aims to provide a back-to-face wafer-level hybrid bonding three-dimensional stacking method, which adopts permanent bonding to replace temporary bonding to assist in completing the whole process flow of wafer-level hybrid bonding, solves the problems of TSV outcrop uniformity, flatness and wafer warping in the prior art, can realize bonding and annealing processes with a carrier, finally realizes layer-by-layer stacking with a chip facing downwards, and avoids face-to-face bonding of the chip.
According to the invention, the aforementioned task is solved by a back-to-face wafer-level hybrid bonding three-dimensional stacking method comprising the following steps:
providing a first wafer; the first wafer comprises a through silicon via positioned in the first wafer, a first interconnecting line positioned on the front surface of the first wafer, a first bonding pad positioned on the first interconnecting line, and a first passivation protective layer wrapping the first interconnecting line and the first bonding pad;
thinning the back surface of the first wafer to expose the through silicon via;
manufacturing a second interconnection line, a second bonding pad and a second passivation protective layer on the back of the first wafer;
carrying out chemical mechanical polishing on the front surface of the second wafer to expose a third bonding pad;
and carrying out hybrid bonding on the back surface of the first wafer and the front surface of the second wafer.
In a preferred embodiment of the present invention, before the step of thinning the back surface of the first wafer, the method further includes:
performing chemical mechanical polishing on the front surface of the first wafer, removing part of the first passivation protective layer, and exposing the first bonding pad;
carrying out chemical mechanical polishing treatment on the slide glass with the silicon oxide layer;
and bonding the front surface of the first wafer and the carrier with the silicon oxide layer.
In a further preferred embodiment of the invention, it is provided that the carrier sheet and the silicon oxide layer are removed.
In a further preferred embodiment of the invention, provision is made for back-to-face wafer-level hybrid bonding steps to be carried out repeatedly to complete a back-to-face hybrid bonded stack of multilayer wafers.
In a further preferred embodiment of the invention, it is provided that the material of the passivation layer is silicon oxide or silicon nitride.
In a further preferred embodiment of the present invention, it is provided that the second bonding pad on the back side of the first wafer is bonded to the third bonding pad on the front side of the second wafer;
SiO is carried out on the second passivation protection layer on the back surface of the first wafer and the third passivation protection layer on the front surface of the second wafer2-SiO2And (4) direct bonding.
In a further preferred embodiment of the invention, provision is made for the first passivation layer and the silicon oxide layer to be SiO-coated2-SiO2And directly bonding to realize bonding of the first wafer and the carrier.
In the inventionIn a further preferred embodiment, the front side of the first wafer and the carrier with the silicon oxide layer are subjected to chemical mechanical polishing, so that the first passivation layer on the front side of the first wafer and the surface of the silicon oxide layer reach SiO2-SiO2The process requirement of direct bonding.
In a further preferred embodiment of the invention, it is provided that the carrier is removed by wafer thinning and plasma etching.
In a further preferred embodiment of the invention, it is provided that the back side of the first wafer is thinned by a chemical mechanical polishing process.
The invention has at least the following beneficial effects: the back-to-face wafer-level hybrid bonding three-dimensional stacking method disclosed by the invention has the advantages that temporary bonding is replaced by permanent bonding, the whole process flow of the wafer-level hybrid bonding is completed in an auxiliary manner, the problems of TSV exposure uniformity, flatness and wafer warping in the prior art are solved, bonding and annealing processes with a carrier can be realized, the chips are stacked layer by layer with the face down, face-to-face bonding of the chips is avoided, and the back-to-face wafer-level hybrid bonding three-dimensional stacking method has the advantages of simple process and low cost.
Drawings
To further clarify the above and other advantages and features of embodiments of the present invention, a more particular description of embodiments of the invention will be rendered by reference to the appended drawings. It is appreciated that these drawings depict only typical embodiments of the invention and are therefore not to be considered limiting of its scope. In the drawings, the same or corresponding parts will be denoted by the same or similar reference numerals for clarity.
FIG. 1 shows a flow diagram of a back-to-face wafer level hybrid bonding three-dimensional stacking method according to an embodiment of the invention; and
fig. 2A to 2G are schematic cross-sectional views illustrating a process of fabricating a back-to-face wafer-level hybrid bonded three-dimensional stacked structure according to an embodiment of the invention.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal".
It should also be noted herein that in the description of the present invention, the terms "central", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the embodiments of the present invention describe the process steps in a specific order, however, this is only for convenience of distinguishing the steps, and does not limit the order of the steps.
FIG. 1 shows a flow diagram of a back-to-face wafer level hybrid bonding three-dimensional stacking method according to an embodiment of the invention; fig. 2A to 2G are schematic cross-sectional views illustrating a process of fabricating a back-to-face wafer-level hybrid bonded three-dimensional stacked structure according to an embodiment of the invention.
First, a "back-to-face wafer level hybrid bond" refers to the back side of a wafer forming a bond with the front side of another wafer. The front side of the wafer typically includes functional areas such as device areas (or active areas), interconnect lines, etc., and the back side of the wafer is the side opposite the front side.
As shown in fig. 1, a back-to-face wafer-level hybrid bonding three-dimensional stacking method includes:
in step 101, a first wafer is provided. As shown in fig. 2A, the first wafer 100 has completed the fabrication of Through Silicon Vias (TSVs) 101, first Cu interconnect lines 103, first Cu bond pads 104, and first passivation protection layer 105. The passivation protection layer 105 is made of silicon oxide or silicon nitride. The first Cu interconnect lines 103 are made by a damascene process. The through silicon vias 101 are located inside the first wafer 100 and electrically connected to Cu interconnection lines 103. The pins 102 are located on the front side of the first wafer 101. First Cu interconnect lines 103 are located on the front side of the first wafer 101 and are electrically connected to the pins 102. The first Cu bond pad 104 is located on the first Cu interconnect line 103 and electrically connected to the first Cu interconnect line 103. The first passivation protective layer 105 wraps the first Cu bond pad 104 and the first Cu interconnect line 103.
It should be understood by those skilled in the art that the material of the Cu interconnect and the Cu bonding pad in the above embodiments is not limited to Cu, and those skilled in the art can use other conductive metal materials to form the interconnect and the bonding pad based on actual requirements.
In step 102, the front side of the first wafer 100 is subjected to a chemical mechanical polishing process to remove a portion of the passivation layer and expose the first Cu bonding pad. The first passivation layer 105 on the front side of the first wafer is brought to SiO by a chemical mechanical polishing process2-SiO2The process requirement of direct bonding.
In step 103, the slide with the silicon oxide layer is subjected to a chemical mechanical polishing process. The surface of the silicon oxide layer on the carrier is made to SiO by chemical mechanical polishing2-SiO2The process requirement of direct bonding. In the embodiment of the invention, the carrier is generally a monocrystalline silicon wafer, and other materials can be selected for the carrier, such as a glass carrier, an organic substrate, a metal substrate, a ceramic substrate, a substrate formed by combining an organic substrate and a metal substrate, or other similar materials. It will be understood by those skilled in the art that flat surfaces of a particular strength may be used as the carrier sheet in the present invention.
At step 104, as shown in fig. 2B, the front side of the first wafer 100 and the carrier sheet 201 with the silicon oxide layer are bonded. By subjecting the first passivation protective layer 105 and the silicon oxide layer 202 to SiO2-SiO2And directly bonded to achieve bonding of the first wafer 100 and the carrier 201.
In step 105, as shown in fig. 2C, the back surface of the first wafer 100 is thinned to expose the through-silicon vias 101. In one embodiment of the present invention, the back side of the first wafer 100 may be thinned using a chemical mechanical polishing process.
In step 106, as shown in fig. 2D, a second Cu interconnection line 106, a second Cu bonding pad 107 and a second passivation layer 108 are fabricated on the back side of the first wafer 100. When the second Cu interconnection line 106 and the second Cu bonding pad 107 are manufactured, a seed layer is deposited, the seed layer adopts Cu, then a line is photoetched, and then Cu is deposited to form the Cu interconnection line and the Cu bonding pad. The material of the second passivation protection layer 108 is silicon oxide or silicon nitride. The second Cu interconnection line 106 is electrically connected to the through-silicon via 101, and the second Cu bonding pad 107 is electrically connected to the second Cu interconnection line 106. The second passivation layer 108 wraps the second Cu interconnection line 106 and the second Cu bonding pad 107, and a surface of the second Cu bonding pad 107 is exposed.
At step 107, the front side of the second wafer 300 is chemically mechanically polished, exposing the third Cu bond pad 304, as shown in fig. 2D. The second wafer 300 has the same structure as the first wafer 100.
At step 108, as shown in fig. 2E, the back side of the first wafer 100 and the front side of the second wafer 300 are hybrid bonded. The second Cu bond pad 107 on the back side of the first wafer 100 is bonded to the third Cu bond pad 304 on the front side of the second wafer 300, and the second blunt Cu bond pad on the back side of the first wafer 100The passivation layer 108 is SiO with the third passivation layer 305 on the front side of the second wafer 3002-SiO2And (4) direct bonding.
In other embodiments of the present invention, repeating steps 105 through 108 may achieve hybrid bonded stacking of multi-layer wafers.
At step 109, the carrier sheet 201 and the silicon oxide layer 202 are removed as shown in fig. 2F and 2G. And removing the carrier by wafer thinning and plasma silicon etching.
The invention has at least the following beneficial effects: the back-to-face wafer-level hybrid bonding three-dimensional stacking method disclosed by the invention adopts permanent bonding to replace temporary bonding, assists in completing the whole process flow of the wafer-level hybrid bonding, solves the problems of TSV outcrop uniformity, flatness and wafer warping in the prior art, can realize bonding and annealing process with a carrier, finally realizes layer-by-layer stacking with the chip facing downwards, avoids face-to-face bonding of the chip, and has the advantages of simple process and low cost.
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims (10)

1. A back-to-face wafer-level hybrid bonded three-dimensional stacking method, comprising:
providing a first wafer; the first wafer comprises a through silicon via positioned in the first wafer, a first interconnecting line positioned on the front surface of the first wafer, a first bonding pad positioned on the first interconnecting line, and a first passivation protective layer wrapping the first interconnecting line and the first bonding pad;
thinning the back surface of the first wafer to expose the through silicon via;
manufacturing a second interconnection line, a second bonding pad and a second passivation protective layer on the back of the first wafer;
carrying out chemical mechanical polishing on the front surface of the second wafer to expose a third bonding pad;
and carrying out hybrid bonding on the back surface of the first wafer and the front surface of the second wafer.
2. The back-to-face wafer level hybrid bonding three-dimensional stacking method of claim 1, wherein the step of thinning the back side of the first wafer further comprises:
performing chemical mechanical polishing on the front surface of the first wafer, removing part of the first passivation protective layer, and exposing the first bonding pad;
carrying out chemical mechanical polishing treatment on the slide glass with the silicon oxide layer;
and bonding the front surface of the first wafer and the carrier with the silicon oxide layer.
3. The back-to-face wafer level hybrid bonded three dimensional stacking method of claim 1 or 2, further comprising removing the carrier sheet and silicon oxide layer.
4. The back-to-face wafer level hybrid bonded three dimensional stacking method of claim 1, wherein the back-to-face wafer level hybrid bonding step is repeatedly performed to complete a back-to-face hybrid bonded stack of multi-layered wafers.
5. The back-to-face wafer level hybrid bonding three-dimensional stacking method of claim 1, wherein the passivation protection layer is made of silicon oxide or silicon nitride.
6. The back-to-face wafer level hybrid bonding three-dimensional stacking method of claim 1, wherein the second bonding pad on the back side of the first wafer is bonded to the third bonding pad on the front side of the second wafer;
the first waferSiO the second passivation protective layer on the back and the third passivation protective layer on the front of the second wafer2-SiO2And (4) direct bonding.
7. The back-to-face wafer level hybrid bonding three-dimensional stacking method of claim 2, wherein the first passivation protection layer and the silicon oxide layer are SiO deposited by2-SiO2And directly bonding to realize bonding of the first wafer and the carrier.
8. The back-to-face wafer level hybrid bonding three-dimensional stacking method of claim 2, wherein the front side of the first wafer and the carrier with the silicon oxide layer are subjected to chemical mechanical polishing to make the first passivation layer on the front side of the first wafer and the surface of the silicon oxide layer reach SiO2-SiO2The process requirement of direct bonding.
9. The back-to-face wafer-level hybrid bonding three-dimensional stacking method of claim 3, wherein the carrier is removed by wafer thinning and plasma silicon etching.
10. The back-to-face wafer level hybrid bonding three-dimensional stacking method of claim 1, wherein the back side of the first wafer is thinned using a chemical mechanical polishing process.
CN202111534068.4A 2021-12-15 2021-12-15 Back-to-face wafer-level hybrid bonding three-dimensional stacking method Pending CN114220745A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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