CN114464543A - Extensible implant micro-system heterogeneous integration method without leveling process - Google Patents

Extensible implant micro-system heterogeneous integration method without leveling process Download PDF

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Publication number
CN114464543A
CN114464543A CN202111563305.XA CN202111563305A CN114464543A CN 114464543 A CN114464543 A CN 114464543A CN 202111563305 A CN202111563305 A CN 202111563305A CN 114464543 A CN114464543 A CN 114464543A
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chip
carrier
bare chip
layer
microsystem
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洪慧
王浩传
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Hangzhou Dianzi University
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Hangzhou Dianzi University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses an extensible implant micro-system heterogeneous integration method without a leveling process, wherein the conventional biological implantable equipment meets the requirements of multifunction and miniaturization integration, a silicon substrate is used in the traditional heterogeneous integration process to match with an integrated circuit photoetching process, deep chip grooves are formed by adopting the technologies of deep silicon etching and the like to prevent chips, the precision of the chip thinning process is greatly required, bottom filling materials are usually adopted to level the chips and the silicon substrate, and the thin chips are extremely easy to crack; large-scale mass production of heterogeneous integrated implanted microsystems is limited; according to the invention, the PDMS material is used as a carrier to coat the devices to be integrated, so that the carrier substrate for integrating various devices for subsequent process RDL wiring can be formed without a leveling process; the conductive adhesive is used for connecting and packaging the chips, so that microsystem heterogeneous integration of chips with various architectures and SMD devices is realized; the heterogeneous integrated batch manufacturing capability of the implantable device is improved.

Description

Extensible implant micro-system heterogeneous integration method without leveling process
Technical Field
The invention relates to the field of implanted integrated processes, in particular to an extensible implant microsystem heterogeneous integration method without a leveling process.
Background
The implanted microsystem equipment is used for connecting and monitoring human physiological activity signals, such as activity characteristics of heartbeats, sweat and the like, monitoring human physiological activity in real time, and timely discovering and processing abnormal states. The implanted microsystem has wide application prospect in the aspects of medical implantable equipment and the like.
The existing implanted physiological monitoring microsystem mainly uses a flexible substrate with a polyimide base to carry out integration based on a Printed Circuit Board Assembly (PCBA) process to realize miniaturization and flexibility, however, the existing PCBA implanted monitoring system generally has the defects of large size and high power consumption, wherein the smallest volume is also 15 multiplied by 12mm3Limiting its implantation in such severely restricted areas of the brain.
In recent years, significant progress has been made in fully implanted microsystems that employ a system-on-chip (SoC) integration scheme, enabling miniaturization, high channel count, full implant, and multi-modal integration. However, due to the area limitation of the implanted integrated circuit, the monolithic integrated circuit cannot integrate large-area capacitors, which limits the power of the electrical stimulation. The limitation on power seriously restricts the application of the fully-implanted brain-computer interface system in neuroscience, biomedical treatment and the like, which puts demands on realizing a miniaturized system with heterogeneous integration.
In the traditional heterogeneous integration process, a silicon substrate is used to match with the integrated circuit photoetching process, deep chip grooves are formed by adopting the technologies of deep silicon etching and the like to prevent the damage to the internal circuits of the chip, and the chip needs to be thinned to about 50 mu m. The precision of the chip thinning process has a great influence on subsequent processing, so that the chip and the silicon substrate are generally leveled by adopting the underfill, but due to the characteristic of an extremely thin chip, the chip is easy to crack in the leveling process, and the large-scale batch manufacturing of the heterogeneous integrated implanted micro-system is limited. There is a need for an implantable chip manufacturing process that is relatively small and not susceptible to chipping during manufacture.
Disclosure of Invention
The invention aims to solve the defects of the prior art and provides an expandable implant micro-system heterogeneous integration method without a leveling process.
In order to solve the problems, the invention adopts the following technical scheme:
an expandable implant microsystem heterogeneous integration method without a leveling process comprises the following steps:
step 1: embedding the bare chip and the surface mounting device into a polydimethylsiloxane carrier;
step 2: constructing a plurality of layers of rewiring layers in the traditional subsequent process;
and step 3: and finishing the mounting of the packaged chip and the surface mounting device on the surface of the multilayer rewiring layer, and protecting the chip pins to obtain the integrated microsystem.
Further, the process of embedding the bare chip and the surface mount device into the polydimethylsiloxane carrier in the step 1 includes:
step 11: accurately placing a bare chip and a surface mounting device on a carrier substrate; wherein the carrier substrate comprises glass and silicon materials;
step 12: pouring and curing with a dimethyl siloxane fluid;
step 13: and stripping the cured dimethyl siloxane carrier from the glass or silicon substrate.
Further, the step 11 of completing the placement of the bare chip and the surface mount device on the carrier substrate includes the following steps:
step 111: cleaning the surface of the carrier substrate by ion cleaning;
step 112: coating photoresist on the carrier substrate in a spin coating mode, wherein the photoresist is used for adhering a bare chip and a surface mounting device;
step 113: the precise placement of the bare chip and the surface mount device is achieved through a laser calibration method.
Further, in the step 111, the ion cleaning is performed by using ionized water, and drying is performed by using nitrogen.
Further, the spin coating in step 112 is performed at 3000rpm for 50 seconds; after the rotation is stopped, the mixture is cured for 10min in an environment with the set temperature of 90 ℃.
Further, when the polydimethylsiloxane fluid is poured in the step 12, the polydimethylsiloxane is required to coat the bare chip and the surface mounting device.
Further, the step of constructing a multilayer redistribution layer in step 2 includes:
step 21: exposing the chip and the surface mounting device pin through a photoetching process; wherein the chip is a naked chip embedded with polydimethylsiloxane;
step 22: SiO2 is deposited on the exposed surface of the pin to serve as a passivation layer;
step 23: and forming a multilayer rewiring layer by using a dielectric material and a wiring material by adopting a traditional post-processing process.
Further, in step 23, the dielectric material of the multiple redistribution layers is polyimide, and the wiring material is a copper wire.
Further, the step 3 of completing the surface mount of the surface package chip and the surface mount device and protecting the chip pins specifically includes the following steps:
step 31: coating conductive adhesive on the welding spots of the surface layer of the multilayer redistribution layer in the step 2;
step 32: according to the conductive adhesive, completing external chip packaging and external surface mounting device mounting;
step 33: curing the conductive adhesive at the welding points;
step 34: and coating the edge of the pin of the packaged chip with a filling material and curing.
Further, in the step 3, the obtained integrated microsystem includes a PDMS carrier, a first bare chip and SMD device, a copper wiring layer, polyimide, a second package chip and SMD device, and a filler; the bare chip and the SMD device I are positioned in the PDMS carrier, and pins of the bare chip and the SMD device I are arranged close to the upper surface of the PDMS carrier; the upper surface of the PDMS carrier is also provided with a plurality of layers of RDL wiring layers, and pins of the bare chip and the SMD device I are connected with wiring materials in the RDL wiring layers; the multilayer RDL wiring layer is also connected with a packaging chip and a SMD device II, and the packaging chip and the SMD device II are arranged on the RDL wiring layer on the outermost layer; and filling materials are arranged around the pins connected with the multilayer RDL wiring layer, and the pins are coated by the filling materials.
The invention has the beneficial effects that:
by using PDMS as a carrier material and combining with the process flow steps, compared with the traditional silicon substrate-based heterogeneous integration process, the precision requirement of chip thinning is reduced, the process of leveling the chip added with the underfill and the silicon substrate can be eliminated, and the precision requirement of the photoetching-based heterogeneous integration process is reduced;
by coating and wrapping PDMS, SMD devices with different thicknesses can be integrated in a carrier, so that peripheral circuits of a chip, such as a crystal oscillator, a resistor, a capacitor and the like, can be implanted, the integration density of a system is improved, and the micro system is ensured to have smaller volume;
by coating the conductive adhesive on the RDL wiring layer, the packaged chip and the peripheral circuit thereof can be secondarily integrated, so that the flexibility of the heterogeneous integration process is improved.
Drawings
FIG. 1 is a flow chart of an implant microsystem heterogeneous integration process of the present invention;
fig. 2 is a structural view of an implant microsystem heterogeneous integrated system of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The first embodiment is as follows:
as shown in fig. 1, a method for heterogeneous integration of an expandable implant microsystem without a leveling process comprises the following steps:
step 1: embedding a bare chip and a Surface Mount Device (SMD) into a Polydimethylsiloxane (PDMS) carrier;
step 2: constructing a multilayer redistribution layer (RDL) in the traditional subsequent process;
and step 3: and finishing the surface mounting of the packaged chip and the SMD device on the surface of the RDL layer, and protecting chip pins to obtain the integrated microsystem.
The bare chip is polished before embedding the bare chip and the SMD device in step 1, and in this example, the thickness of the bare chip is required to be polished to less than 90 μm by rotation. The process of embedding the bare chip and the SMD device into the PDMS carrier includes:
step 11: accurately placing a bare chip and an SMD device on a carrier substrate; wherein the carrier substrate comprises glass, silicon, or the like;
step 12: pouring and coating by using PDMS fluid, and curing;
step 13: and stripping the cured PDMS carrier from the glass or silicon substrate.
The placement of the bare chip and the SMD device on the carrier substrate is completed in step 11, comprising the steps of:
step 111: cleaning the surface of the carrier substrate by ion cleaning;
step 112: coating photoresist on the carrier substrate in a spin coating mode, wherein the photoresist is used for adhering a bare chip and a surface mounting device;
step 113: the precise placement of the bare chip and the SMD device is realized by a laser calibration method.
The ion cleaning in step 111 is in this case cleaning with ionized water and drying with nitrogen; the carrier substrate is a glass plate.
Spin coating is applied at step 112, which is performed for 50 seconds at 3000rpm in this example, to form a sacrificial layer for bonding the device, and curing is performed for 10min at a set temperature of 90 ℃ after the spin is stopped.
In step 113, the die is placed with the die surface facing the carrier substrate, the die surface representing the side of the die where the leads are disposed.
When the PDMS fluid is poured in step 12, the PDMS is required to cover the bare chip and the SMD device.
The step of constructing a multilayer RDL wiring layer in the step 2 comprises the following steps:
step 21: exposing the chip and the pins of the SMD device through a photoetching process; wherein the chip is a naked chip embedded with polydimethylsiloxane;
step 22: SiO2 is deposited on the exposed surface of the pin to serve as a passivation layer;
step 23: multilayer RDL wiring is formed using dielectric materials and wiring materials using conventional post-processing techniques.
In step 22, the purpose of exposing the pins and depositing SiO2 on the pins is to prevent the wires inside the RDL wiring layer from affecting the chip and SMD device inside the PDMS carrier when the RDL wiring layer is subsequently disposed.
In step 23, the dielectric material of the multilayer RDL wiring is polyimide, the wiring material is copper wire, metal wiring is formed by the existing photolithography process, system interconnection is completed, and multilayer RDL wiring is formed.
The step 3 of finishing the surface mounting of the surface packaging chip and the SMD device and protecting the pins of the chip specifically comprises the following steps:
step 31: coating conductive adhesive at welding spots on the surface layer of the multilayer RDL wiring layer in the step 2;
step 32: according to the conductive adhesive, completing external chip packaging and external SMD device mounting;
step 33: curing the conductive adhesive at the welding points;
step 34: and coating the edge of the pin of the packaged chip with a filling material and curing.
In step 33, curing of the conductive paste is achieved by ultraviolet irradiation.
In step 34, the curing of the filler is completed by heating, wherein the heating temperature is 160 ℃.
As shown in fig. 2, in step 3, the obtained integrated microsystem includes a PDMS carrier, a first bare chip and SMD device, a copper wiring layer, polyimide, a second packaged chip and SMD device, and a filler; the bare chip and the SMD device I are positioned in the PDMS carrier, and pins of the bare chip and the SMD device I are arranged close to the upper surface of the PDMS carrier; the upper surface of the PDMS carrier is also provided with a plurality of layers of RDL wiring layers, and pins of the bare chip and the SMD device I are connected with wiring materials in the RDL wiring layers; the multilayer RDL wiring layer is also connected with a packaging chip and a SMD device II, and the packaging chip and the SMD device II are arranged on the RDL wiring layer on the outermost layer; and filling materials are arranged around the pins connected with the multilayer RDL wiring layer, and the pins are coated by the filling materials.
In the implementation process, the PDMS carrier is adopted, the bare chip and the SMD device are wrapped in a fluid state, and then curing molding is carried out, so that the device can be suitable for integration of devices with various sizes, and the device has high flexibility; after a PDMS carrier is used for integrating a device, a copper metal layer and a polyimide dielectric layer are laminated by a traditional post-processing technology to form an RDL wiring layer, so that the interconnection of a system structure is realized; the RDL wiring layer on the surface layer is interconnected with the packaged chip and other SMD devices through conductive adhesive, and the pins of the packaged chip are protected by using filling materials, so that extensible integration of various architecture devices is formed.
The above description is only one specific example of the present invention and should not be construed as limiting the invention in any way. It will be apparent to persons skilled in the relevant art(s) that, having the benefit of this disclosure and its principles, various modifications and changes in form and detail can be made without departing from the principles and structures of the invention, which are, however, encompassed by the appended claims.

Claims (10)

1. An expandable implant microsystem heterogeneous integration method without a leveling process is characterized by comprising the following steps:
step 1: embedding the bare chip and the surface mounting device into a polydimethylsiloxane carrier;
step 2: constructing a plurality of layers of rewiring layers in the traditional subsequent process;
and step 3: and finishing the mounting of the packaged chip and the surface mounting device on the surface of the multilayer rewiring layer, and protecting the chip pins to obtain the integrated microsystem.
2. The method for the heterogeneous integration of the expandable implant microsystem without the leveling process as claimed in claim 1, wherein the process of embedding the bare chip and the surface mount device into the polydimethylsiloxane carrier in step 1 comprises:
step 11: accurately placing a bare chip and a surface mounting device on a carrier substrate; wherein the carrier substrate comprises glass and silicon materials;
step 12: pouring and curing with a dimethyl siloxane fluid;
step 13: and stripping the cured dimethyl siloxane carrier from the glass or silicon substrate.
3. The method of claim 2, wherein the step 11 of completing the placement of the bare chip and the surface mount device on the carrier substrate comprises the steps of:
step 111: cleaning the surface of the carrier substrate by ion cleaning;
step 112: coating photoresist on the carrier substrate in a spin coating mode, wherein the photoresist is used for adhering a bare chip and a surface mounting device;
step 113: the precise placement of the bare chip and the surface mount device is achieved through a laser calibration method.
4. The method of claim 3, wherein the step 111 of ion cleaning is ion water cleaning and nitrogen drying.
5. The method of claim 3, wherein the step 112 of spin coating is performed at 3000rpm for 50 s; after the rotation is stopped, the mixture is cured for 10min in an environment with the set temperature of 90 ℃.
6. The method of claim 2, wherein the polydimethylsiloxane fluid is poured in step 12 to coat the bare chip and the surface mount device.
7. The method of claim 1, wherein the step of building multiple redistribution layers in step 2 comprises:
step 21: exposing the chip and the surface mounting device pin through a photoetching process; wherein the chip is a naked chip embedded with polydimethylsiloxane;
step 22: SiO2 is deposited on the exposed surface of the pin to serve as a passivation layer;
step 23: and forming a multilayer rewiring layer by using a dielectric material and a wiring material by adopting a traditional post-processing process.
8. The method for the heterogeneous integration of the expandable implant microsystem without the leveling process as claimed in claim 7, wherein in the step 23, the dielectric material of the multiple redistribution layers is polyimide, and the wiring material is copper wire.
9. The method of claim 1, wherein the step 3 of completing surface mount chip and surface mount device attachment and chip pin protection comprises the following steps:
step 31: coating conductive adhesive on the welding spots of the surface layer of the multilayer redistribution layer in the step 2;
step 32: according to the conductive adhesive, completing external chip packaging and external surface mounting device mounting;
step 33: curing the conductive adhesive at the welding spots;
step 34: and coating the edge of the pin of the packaged chip with a filling material and curing.
10. The method for heterogeneous integration of the expandable implant microsystem without the leveling process as claimed in claim 9, wherein the integrated microsystem obtained in step 3 comprises a PDMS carrier, a first bare chip and SMD device, a copper wiring layer, polyimide, a second packaged chip and SMD device, and a filler; the bare chip and the SMD device I are positioned in the PDMS carrier, and pins of the bare chip and the SMD device I are arranged close to the upper surface of the PDMS carrier; the upper surface of the PDMS carrier is also provided with a plurality of layers of RDL wiring layers, and pins of the bare chip and the SMD device I are connected with wiring materials in the RDL wiring layers; the multilayer RDL wiring layer is also connected with a packaging chip and a SMD device II, and the packaging chip and the SMD device II are arranged on the RDL wiring layer on the outermost layer; and filling materials are arranged around the pins connected with the multilayer RDL wiring layer, and the pins are coated by the filling materials.
CN202111563305.XA 2021-12-20 2021-12-20 Extensible implant micro-system heterogeneous integration method without leveling process Pending CN114464543A (en)

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