CN114464523A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN114464523A
CN114464523A CN202210234273.7A CN202210234273A CN114464523A CN 114464523 A CN114464523 A CN 114464523A CN 202210234273 A CN202210234273 A CN 202210234273A CN 114464523 A CN114464523 A CN 114464523A
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top surface
fin structure
material layer
protective layer
fin
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曹志军
刘轶群
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Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
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Shanghai IC R&D Center Co Ltd
Shanghai IC Equipment Material Industry Innovation Center Co Ltd
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Priority to CN202210234273.7A priority Critical patent/CN114464523A/en
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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
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    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
    • C23C16/45563—Gas nozzles
    • C23C16/45568—Porous nozzles
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/46—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
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Abstract

The invention provides a semiconductor device and a manufacturing method thereof, which are applied to the field of semiconductors. In the manufacturing method of the semiconductor device, after the fin structure is formed on the substrate, the protective layer with certain thickness and special material is formed on the top surface and the side walls on the two sides of the fin structure, and then the subsequent process of the FinFET device is carried out on the substrate with the fin structure, so that the loss of the fin structure caused by the subsequent process of the FinFET device can be avoided under the action of the protective layer, the fin structure can finally keep relatively large Critical Dimension (CD), and meanwhile, the size of the second shallow trench for forming the source and drain of the FinFET device and the size of the epitaxial contact surface wrapped in the Gate are increased due to the existence of the protective layer, namely, the problem that the source and drain of the FinFET device are not beneficial to being formed in the small-size fin structure in the prior art is solved.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
Transistor devices have a variety of configurations, such as planar devices, FinFET devices, vertical devices, and the like. FinFET devices are commonly used in modern IC products. A FinFET device may include a single active fin (i.e., a single semiconductor structure) or multiple fins (i.e., multiple semiconductor structures). Such fins have a long axis that is oriented substantially horizontally with respect to an upper surface of the semiconductor substrate on which the FinFET device is formed.
At present, as the semiconductor industry enters smaller nano technology process nodes, such as below 5nm technology nodes, and as the channel length of MOS devices is further reduced, in order to solve the short channel effect of MOS devices, MOS devices are developed from the conventional planar structure, and the channel length of MOS devices is continuously reduced, so that the short channel effect of MOS devices is particularly applicable to the three-dimensional structure of fin field effect transistors (finfets). The structure has the advantages that the fin-type grid electrode is surrounded on three sides, the static control capability of the grid electrode is improved, and the short channel effect is reduced.
However, since the prior art techniques, after forming the fin structure of a FinFET device on a semiconductor substrate by a photolithography and/or etching process, it may be desirable to fill a portion of the isolation material between adjacent fin structures and then anneal, during which, the high temperature processing environment of the process typically results in a relatively large CDloss of the Fin structure, and also results in a significant CDloss when the Fin surface is grown multiple times, which requires the Fin structure to have a relatively large CD before etching, however, as the process node advances downward, the area of the transistor, the size of the fin structure gradually decreases, the etching process faces a larger aspect ratio, during the etching process of the fin structure, large CD is difficult to guarantee, and the small CD of the fin structure is difficult to counteract the consumption of subsequent processes, hardly reaches FinCD size required by final design, and is not beneficial to the growth of a source and drain epitaxial layer.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, and aims to solve the problems that the size of a fin structure is continuously consumed in the subsequent process and the source and drain electrodes of the FinFET device are not favorably formed in the small-size fin structure along with the continuous reduction of the size of the fin structure of the FinFET device in the prior art.
In a first aspect, to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, the method at least comprising the steps of:
step S1, providing a substrate, on which a plurality of discrete fin structures are formed;
step S2, forming a protective layer which covers the top surface and the side wall of the fin structure and extends to cover the surface of the substrate exposed by the gap between the adjacent fin structures;
step S3, forming a filler material layer on the surface of the protection layer, wherein the filler material layer at least fills the gap between the adjacent fin structures;
step S4, performing subsequent processes on the substrate including the protection layer and the filling material layer to form a FinFET device structure including a source region, a drain region, and a metal gate.
Further, the top surface of the filler material layer formed in step S3 is higher than the top surface of the protection layer covering the top surface of the fin structure;
the manufacturing method may further include, after the step S3:
and carrying out top surface planarization on the filling material layer until the top surface of the protective layer covered on the fin structure top surface is exposed.
Further, after the step S3, the manufacturing method may further include:
etching back the filling material layer to expose the protective layer covered on the top surface of each fin structure and the side wall with partial height;
forming a dummy gate spanning over a plurality of the fin structures and surrounding sidewalls and a top surface of a partial region of the fin structures;
forming a source electrode and a drain electrode in the fin structures at two sides of each virtual grid electrode, and removing the virtual grid electrodes to expose the fin structures between the source electrode and the drain electrode for forming a channel;
and forming a metal gate on the surface of the fin structure between the exposed source electrode and the exposed drain electrode.
Further, after forming a source and a drain in the fin structure on both sides of each of the dummy gates and removing the dummy gates to expose the fin structure between the source and the drain for forming a channel, the manufacturing method may further include:
and removing the protective layer on the top surface and the side wall of the fin structure between the exposed source electrode and the exposed drain electrode for forming the channel, and enabling the top surface of the protective layer remaining on the side wall of the fin structure to be at least flush with the top surface of the filling material layer remaining in the gap between the adjacent fin structures.
Further, after the etching back the filling material layer to expose the protective layer covering on the top surface of each fin structure and on the sidewall of a partial height, the manufacturing method may further include:
and removing the protective layer covered on the exposed top surface of each fin structure and the side wall of partial height, and enabling the top surface of the protective layer left on the side wall of the fin structure to be at least flush with the top surface of the filling material layer left in the gap between the adjacent fin structures.
Further, after removing the protective layer on the top surface and the sidewalls of the fin structure between the exposed source and drain electrodes for forming the channel, or after removing the protective layer covering the top surface and the sidewalls of the partial height of each exposed fin structure, the manufacturing method may further include:
the top surface of the remaining protective layer on the side wall of the fin structure is lower than the top surface of the filling material layer remaining in the gap between the adjacent fin structures, so that a plurality of first shallow trenches are surrounded by the remaining filling material layer, the fin structure and the remaining protective layer on the side wall of the fin structure;
and filling an isolation material layer in each first shallow trench, so that the top surface of the filled first shallow trench is flush with the top surface of the filling material layer remained in the gap between the adjacent fin structures.
Further, the material of the filling material layer and the isolating material layer may be the same.
Further, the substrate may be a silicon substrate, and the material of the protective layer may include germanium silicide.
Further, the step of forming a source and a drain in the fin structure on both sides of each of the dummy gates may include:
removing the substrate in the fin structures in partial areas on two sides of the virtual grid electrode and the protective layers on the side walls on two sides of the substrate so as to form second shallow trenches in the fin structures on two sides of the virtual grid electrode respectively;
and depositing an epitaxial material layer in the second shallow trench so that the epitaxial material layer at least fills the second shallow trench to form the source and the drain.
Further, the epitaxial material layer includes at least one of silicon, silicon phosphide, silicon carbon phosphide and germanium silicide.
In a second aspect, based on the same inventive concept, the present invention also provides a semiconductor device, which can be manufactured by the manufacturing method as described above.
Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:
in the manufacturing method of the semiconductor device, after the fin structure is formed on the substrate, a protective layer with certain thickness and special material is formed on the top surface and the side walls on the two sides of the fin structure, and then the subsequent process of the FinFET device is carried out on the substrate with the fin structure, so that the loss of the fin structure caused by the subsequent process of the FinFET device can be avoided under the action of the protective layer, the fin structure can finally keep relatively large Critical Dimension (CD), and meanwhile, the size of a second shallow trench for forming a source and a drain of the FinFET device and the size of a channel epitaxial contact surface wrapped in Gate are increased due to the existence of the protective layer, namely, the problem that the source and the drain of the device are not beneficial to forming in the small-size fin structure in the prior art is solved.
Furthermore, in the method for forming the FinFET device provided by the present invention, after the fin structure is formed, the protective layer is formed on the top surface and the sidewalls on both sides of the fin structure, so that when filling and etching the STI material (filling material layer) in the gap between the adjacent fin structures in the subsequent process, the protective layer formed on the top surface of the fin structure can be used as an etching stop layer instead of forming an etching stop layer for defining the etching stop position of the STI material separately, thereby saving the manufacturing cost of the FinFET device.
Drawings
FIG. 1 is a flow chart of a method of fabricating a semiconductor device according to the present invention;
FIGS. 2a to 2j are schematic structural diagrams of a semiconductor device in a manufacturing process according to an embodiment of the present invention;
wherein the reference numbers are as follows:
100-a substrate; a 110-fin structure;
120/120' -protective layers; 130/130' -a layer of filler material;
101-a first shallow trench; 102-a second shallow trench;
140-a virtual gate; 150-source/drain;
160-metal gate; 170-layer of isolating material.
Detailed Description
As mentioned in the background, in the prior art, after the Fin structure of the FinFET device is formed on the semiconductor substrate by the photolithography and/or etching process, a portion of isolation material needs to be filled between adjacent Fin structures, and then annealing is performed, while in the annealing process, due to the high temperature processing environment of the process, the CDloss of a relatively large Fin structure is usually caused, and in addition, the FinCD is obviously consumed by the thin film that is directly grown on the Fin for multiple times, which requires that the Fin structure has a relatively large CD before etching, but as the process node advances downwards, the area of the transistor and the size of the Fin structure gradually decrease, the etching process faces a larger aspect ratio, it is difficult to ensure that the large CD is present at the current station during the etching of the Fin structure, and the CD of the small Fin structure is difficult to offset the consumption of the subsequent process and thus cannot be made into the final required size of the FinCD, secondly, the growth of the epitaxial layer of the source and drain electrodes is not facilitated.
Therefore, the invention provides a semiconductor device and a manufacturing method thereof, and aims to solve the problems that the size of a fin structure is continuously consumed in the subsequent process and the source and drain electrodes of the FinFET device are not favorably formed in the small-size fin structure along with the continuous reduction of the size of the fin structure of the FinFET device in the prior art.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, the manufacturing method of the semiconductor device comprises the following steps:
in step S1, a substrate having a plurality of discrete fin structures formed thereon is provided.
Step S2, forming a protection layer covering the top surface and the sidewalls of the fin structures and extending to cover the surface of the substrate exposed by the gaps between adjacent fin structures.
In step S3, a filler material layer is formed on the surface of the protection layer, wherein the filler material layer at least fills the gap between the adjacent fin structures.
Step S4, performing subsequent processes on the substrate including the protection layer and the filling material layer to form a FinFET device structure including a source region, a drain region, and a metal gate.
That is, in the method for manufacturing a semiconductor device provided by the present invention, after the fin structure is formed on the substrate, a protective layer with a certain thickness and a special material is formed on the top surface and the sidewalls on both sides of the fin structure, and then the subsequent process of the FinFET device is performed on the substrate on which the fin structure is formed, so that the Critical Dimension (CD) of the fin structure is increased while the loss of the fin structure by the subsequent process of the FinFET device is avoided under the action of the protective layer, thereby increasing the size of the second shallow trench for forming the source and drain of the FinFET device, i.e., solving the problem that the formation of the source and drain of the FinFET device is not facilitated in the small-sized fin structure in the prior art.
The semiconductor device and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements. In describing the embodiments of the present invention in detail, the cross-sectional views illustrating the structure of the device are not enlarged partially in a general scale for convenience of illustration, and the schematic drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Fig. 2a to 2j are schematic structural diagrams of a semiconductor device in a manufacturing process according to an embodiment of the invention.
In step S1, referring specifically to fig. 2a, a substrate 100 is provided, the substrate 100 having a plurality of discrete fin structures 110 formed thereon. The substrate 100 may be any suitable substrate known in the art, and may be, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and further includes a multilayer structure composed of these semiconductors, or may be Silicon On Insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or may be double-side polished silicon wafers (DSP), or may be ceramic substrates such as alumina, quartz, glass substrates, or the like. Illustratively, the substrate 100 in this embodiment may be, for example, a silicon substrate. Also, the silicon substrate 100 is particularly useful for providing a platform for operation in subsequent processes to create FinFET devices.
In this embodiment, a patterned photoresist layer (not shown) may be formed on the surface of the substrate 100, and the substrate 100 is etched using the patterned photoresist layer as a mask, so as to form a plurality of discrete fin structures 110 in the substrate 100. While adjacent ones of the fin structures 110 are separated by a void.
In step S2, referring specifically to fig. 2b, a protection layer 120 is formed, wherein the protection layer 120 covers the top surface and the sidewalls of the fin structures 110 and extends to cover the surface of the substrate 100 exposed by the gaps between adjacent fin structures 110.
In this embodiment, after the plurality of fin structures 110 separated by the voids are formed in step S1, a protective layer 120 with a certain thickness may be formed on the surface (top surface and sidewalls) of each fin structure 110 by using a reduced pressure chemical vapor deposition epitaxy process RPCVD, and at the same time, a protective layer 120 may be formed on the substrate 100 at the bottom of the void between the adjacent fin structures 110. The material of the protection layer 120 may be a single crystal material having the same crystal orientation as the silicon in the silicon substrate 100, such as germanium silicide.
In step S3, referring to fig. 2c in particular, a filler material layer 130 is formed on the surface of the protection layer 120, and the filler material layer 130 at least fills the gap between the adjacent fin structures 110.
The material of the filling material layer 130 may be an isolation material such as oxide or nitride, for example, silicon dioxide, silicon nitride, or the like.
In this embodiment, after the protective layer 120 is formed in the step S2, a filler material layer 130 may be formed on the surface of the substrate 100, and the filler material layer 130 at least needs to fill the gap between the adjacent fin structures 110. However, the height of the filling material layer 130 in the direction perpendicular to the surface of the substrate 100 is usually higher than the height of the protection layer 120 formed on the top surface of the fin structure 110 when the filling material layer 130 is formed, and therefore, the CMP polishing process is also required for the filling material layer 130 in the conventional process flow for forming the FinFET device structure for this case.
Illustratively, when the top surface of the filling material layer formed in the step S3 is higher than the top surface of the protection layer 120 covering the top surface of the fin structure 110, the method for manufacturing a semiconductor device provided by the present invention may further include the following steps after the step S3:
step S3.1, performing top surface planarization on the filling material layer until the top surface of the protection layer 120 covered on the top surface of the fin structure 110 is exposed, so as to obtain the planarized filling material layer 130 as shown in fig. 2 c.
Obviously, in the step S3.1 provided by the present invention, it is not necessary to separately form an etching stop layer on the top surface of the fin structure 110 as in the prior art, but the protective layer 120 formed on the top surface of the fin structure 110 in the step S2 is directly used as the etching stop layer of this step, so that the top surface of the etched filling material layer 130 is flush with the top surface of the protective layer 120. Therefore, the method for forming the FinFET device can save the manufacturing cost of the FinFET device.
Moreover, in the process of etching the filling material layer 130 in the step S3.1, due to errors caused by an etching machine and manual operations, a part of the protection layer 120 on the top surface of the fin structure may be etched away at the same time when the filling material layer is etched, so that the protection layer 120 may also be used in the process of etching the filling material layer 130 in the step S3.1, thereby avoiding a problem that silicon materials on the top and side surfaces of the fin structure 110 are consumed when over-etching occurs, that is, ensuring the CD size of the fin structure of the FinFET device, so that the finally formed FinFET device meets actual design requirements.
In step S4, referring to fig. 2d to fig. 2j in particular, the substrate 100 including the protection layer 120 and the filling material layer 130 is subjected to a subsequent process to form a FinFET device structure including a source region, a drain region and a metal gate.
In this embodiment, after the fin structure 110, the protection layer 120 and the filler material layer 130 are formed, a dummy gate, a source region, a drain region and a metal gate of the FinFET device may be further formed. Specifically, the method can comprise the following steps:
step S4.1, referring to fig. 2d specifically, etching back the filling material layer 130 to obtain the filling material layer 130' shown in fig. 2d, so as to expose the protective layer 120 covering the top surface and the sidewall of a part of the height of each fin structure 110;
step S4.2, referring to fig. 2e in particular, forming a dummy gate 140, where the dummy gate 140 spans over a plurality of the fin structures 110 and surrounds the sidewalls and the top surface of the partial region of the fin structures 110;
step S4.3, referring to fig. 2g specifically, forming a source 150 and a drain 150 in the fin structure 110 on both sides of each of the dummy gates 140, and removing the dummy gates 140 at the same time to expose the fin structure 110 between the source 150 and the drain 150 for forming a channel;
step S4.4, referring specifically to fig. 2j, a metal gate 160 is formed on the surface of the fin structure between the exposed source 150 and drain 150, where the metal gate 160 surrounds the top surface and the sidewall of the fin structure 110 for forming the channel.
The material of the dummy gate 140 may be a polysilicon material, the material for forming the source 150 and the drain 150 may be an epitaxial material layer, and the epitaxial material layer may include at least one of silicon, silicon phosphide, silicon carbon phosphide and germanium silicide.
In this embodiment, after the step S3 is performed to etch the filling material layer 130 formed in the step S2 so that the top surface of the etched filling material layer 130 is flush with the top surface of the protection layer 120 on the top surface of the fin structure 110, the etching of the filling material layer 130 in the gap between adjacent fin structures 110 may be continued to remove the filling material layer 130 in the gap at a partial height, and simultaneously, the remaining part of the filling material layer 130' is in the gap. Then, a dummy gate 140, a source 150, a drain 150, and a metal gate 160 are formed on the substrate 100.
In particular, three ways of forming the subsequent electrical structure are provided in embodiments of the present invention.
The first method is as follows: referring specifically to fig. 2 f-2 h, a dummy gate 140, a source 150, a drain 150, and a metal gate 160 are formed on the top surface and the sidewalls of the fin structure 110, with the protective layer 120 remaining. Specifically, after the step of forming the dummy gate 140 in the step S4.2 (as shown in fig. 2 e), the step of forming the dummy gate 140 on the sidewalls and the top surface of the partial region of the fin structure 110 and spanning over the plurality of fin structures 110 may further include the following steps:
step S4.31, referring to fig. 2f specifically, removing the fin structure 110 located in the partial regions on both sides of the dummy gate 140 and the protective layer 120 located on the sidewalls of both sides of the fin structure 110, so as to form the second shallow trenches 102 in the fin structures 110 on both sides of the dummy gate 140 respectively;
step S4.32, referring specifically to fig. 2g, depositing an epitaxial material layer (not shown) in the second shallow trench 102 and on both sides of the upper trench, so that the epitaxial material layer (not shown) at least fills the second shallow trench 102 to form the source 150 and the drain 150;
step S4.33, specifically referring to fig. 2h, the exposed top surface and the exposed protective layer 120 on the sidewall of the fin structure 110 between the source 150 and the drain 150 for forming a channel are removed, and the filling material layer 130 is etched back, so that the top surface of the remaining protective layer 120 'on the sidewall of the fin structure 110 is at least flush with the top surface of the remaining filling material layer 130' in the gap between the adjacent fin structures 110.
In this embodiment, after the dummy gate 140 is formed in the step S4.2, the dummy gate 140 may be used as a self-alignment, and then the source 150 and the drain 150 are formed in the fin structure 110 and the single crystal protection layer where both sides of the dummy gate 140 and the bottom of the source and the drain are exposed. Wherein the epitaxial material layer filled in the second shallow trench 102 may include at least one of silicon, silicon phosphide, silicon carbon phosphide and germanium silicide. Illustratively, in the embodiments of the present invention, the epitaxial material layer may be a germanium silicide. In the manufacturing method of the FinFET device provided by the present invention, before the second shallow trenches are formed, the protective layers are formed on the side edges of the two sides of the fin structure, so as to further protect the Critical Dimension (CD) of each fin structure 110, and therefore, when the second shallow trenches 102 are formed in step S4.31, the dimension of the second shallow trenches for forming the source and drain of the FinFET device, which are formed by the second shallow trenches, is also increased while the CD that can selectively grow the source and drain under the Gate is also increased, thereby solving the problem that in the prior art, it is not favorable for forming the source and drain of the FinFET device in the small-sized fin structure.
It should be noted that, assuming that all the drawings provided in the embodiments of the present invention are cross-sectional views in the X direction obtained by cutting in the horizontal direction of the formed semiconductor structure, there is a front-to-back positional distance deviation between the source/drain 150 and the dummy gate 140 (metal gate 160) in the Y direction as viewed from the Y direction perpendicular to the X direction, that is, the source 150 and the drain 150 are arranged on both sides of the dummy gate 140 (metal gate 160) in the Y direction. Therefore, when the second shallow trench 102 shown in fig. 2f (the shallow trench 102 is used for finally forming the source/drain 150) and the source/drain 150 shown in fig. 2g are formed through an etching and filling process, fig. 2f and 2g only show the second shallow trench 102 and the source/drain 150, but do not show the fin structure 110 located behind the source/drain 150 along the Y direction and the protection layer 120 located on the surface of the fin structure 110, and are directly embodied by the dummy gate 140 covered on the surface of the protection layer 120. Since step S4.33 is to etch away the protection layer 120 on the surface of the fin structure 110 between the source 150 and the drain 150, so as to finally form the metal gate 160 on the surface, in order to show the specific form of step S4.33 to remove the protection layer 120 on the surface of the fin structure 110 between the source 150 and the drain 150, fig. 2h and fig. 2i and 2j below provided by the present invention are cross-sectional views along the X direction of the semiconductor substrate obtained by shifting back across the source/drain along the Y direction.
It should be noted that, after step S4.33, a step of forming the metal gate 160 as shown in fig. 2i and fig. 2j is also included, and since this step is a prior art, the present invention will not be described in detail.
The second method comprises the following steps: the dummy gate 140, the source 150, the drain 150, and the metal gate 160 are formed on the top surface and the sidewalls of the fin structure 110 after the protective layer 120 is removed. Specifically, after the step S4.1 shown in fig. 2d is to etch back the filling material layer 130 to expose the protective layer 120 covering the top surface and the sidewall with a partial height of each fin structure 110, and before the step S4.2 shown in fig. 2e is to form a dummy gate 140, where the dummy gate 140 spans over the plurality of fin structures 110 and surrounds the sidewall and the top surface of a partial region of the fin structures 110, the method may further include the following steps:
step S4.11, referring to fig. 2i specifically, the protective layer 120 covering the top surface of each exposed fin structure 110 and the sidewalls of a partial height is removed, and the top surface of the remaining film layer on the sidewalls of the fin structures 110 is at least flush with the top surface of the filling material layer 130' remaining in the gaps between adjacent fin structures.
In this embodiment, before forming the dummy gate 140, the step S4.1 of selectively etching back the filling material layer 130 by using a wet etching process or a dry etching process may be performed to expose the protective layer 120 covering the top surface and the sidewall of a portion of the height of each fin structure 110; then, the step S4.2 is performed again to form the dummy gate 140 by crossing over the plurality of fin structures 110 and surrounding the sidewalls and the top surface of the partial region of the fin structures 110. Then the following steps are executed:
step S4.12, referring to fig. 2f specifically, removing the fin structure 110 located in the partial regions on both sides of the dummy gate 140 and the protective layer 120 located on the sidewalls of both sides of the fin structure 110, so as to form the second shallow trenches 102 in the fin structures 110 on both sides of the dummy gate 140 respectively;
step S4.13, referring to fig. 2g specifically, depositing an epitaxial material layer in the second shallow trench 102, so that the epitaxial material layer at least fills the second shallow trench 102 and forms a certain thickness on both sides of the channel in the dummy gate, so as to form the source 150 and the drain 150.
As can be seen from the above description of the first and second manners, the removal of the protection layer 120 covering the exposed top surface and the partial height sidewall of each fin structure 110 before or after the formation of the dummy gate 140 does not affect the critical dimension of the second shallow trench 102.
The third method comprises the following steps: the dummy gate 140, the source 150, the drain 150, and the metal gate 160 are formed without removing the protective layer 120 on the top surface and the sidewalls of the fin structure 110 during the formation of the FinFET device structure.
In this embodiment, an implementation may also be provided, in which the protective layer 120 covering the top surface and the sidewall of a part of the height of each fin structure 110 is not removed before or after the formation of the dummy gate 140, but the dummy gate 140, the source 150, the drain 150, and the metal gate 160 of the FinFET device structure are further formed directly under the protection of the protective layer. The third method may be implemented if the material of the protection layer formed in step S2 is selected appropriately, for example, the material etching is germanium silicide.
Thereafter, referring specifically to fig. 2j, a metal gate material layer is deposited at the position where the dummy gate 140 (deleted) was originally formed, so as to form the metal gate 160.
It should be noted that, in either the first or the second or the third mode, during the process of forming the second shallow trenches 102 in the fin structures 110 on both sides of the dummy gate 140, there may occur a problem of over-etching the fin structures 110 on both sides of the dummy gate 140 due to human error of an etching machine or an operator, so that the top surfaces of the second shallow trenches 102 formed are lower than the top surfaces of the filling material layers 130' remaining in the gap between the adjacent fin structures 110, as shown in fig. 2h, and therefore, for this problem, after selectively removing the exposed protective layer 120 on the top surfaces and the sidewalls of the fin structures 110 between the source 150 and the drain 150 for forming a channel in the step S4.33, or after selectively removing the exposed protective layer 120 on the top surfaces and the sidewalls of the respective fin structures 110 and on the sidewalls of a part of the height in the step S4.11, the method may further comprise:
referring specifically to fig. 2h and fig. 2i, the top surface of the remaining protection layer 120 'on the sidewall of the fin structure 110 is lower than the top surface of the filling material layer 130' remaining in the gap between adjacent fin structures 110, so as to enclose a plurality of first shallow trenches 101 by the remaining filling material layer 130 ', the fin structure 110 and the remaining protection layer 120' on the sidewall of the fin structure 110; filling an isolation material layer in each first shallow trench 101 so that the top surface of the first shallow trench 101 after filling is flush with the top surface of the filling material layer 130' remaining in the gap between the adjacent fin structures 110 or directly etching back the filling layer 130 to make the filling layers 130 and 101 flush. Wherein the material of the filling material layer 130' and the isolating material layer 170 is the same. Illustratively, the material of the isolation material layer 170 may be silicon dioxide or silicon nitride.
Further, the present invention also provides a semiconductor device based on the same inventive concept as the manufacturing method of the semiconductor device as described above. Specifically, the semiconductor device formed is a FinFET device, and the formation process may refer to all embodiments of the manufacturing method of the semiconductor device as described above, and will not be described in detail herein.
In summary, in the manufacturing method of the semiconductor device provided by the present invention, after the fin structure is formed on the substrate, the protective layer with a certain thickness and a special material is formed on the top surface and the sidewalls on both sides of the fin structure, and then the subsequent process of the FinFET device is performed on the substrate with the fin structure formed thereon, so that the Critical Dimension (CD) of the fin structure is protected while the loss of the fin structure by the subsequent process of the FinFET device is avoided under the action of the protective layer, thereby increasing the size of the second shallow trench for forming the source/drain of the FinFET device; in addition, in the first mode, the epitaxial contact size in the virtual gate is increased, that is, the problem that in the prior art, the source and drain electrodes of the FinFET device are not easy to form in a small-size fin structure is solved.
Furthermore, in the method for forming the FinFET device provided by the present invention, after the fin structure is formed, the protective layer is formed on the top surface and the sidewalls on both sides of the fin structure, so that when filling and etching the STI material (filling material layer) in the gap between the adjacent fin structures in the subsequent process, the protective layer formed on the top surface of the fin structure can be used as an etching stop layer instead of forming an etching stop layer for defining the etching stop position of the STI material separately, thereby saving the manufacturing cost of the FinFET device.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the present invention.
Further, it will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of exemplary embodiments according to the present invention.
Spatially relative terms, such as "below … …," "above … …," "below," "above … …," "above," "upper" and "lower" may be used herein for ease of description to describe the spatial relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (11)

1. A method of manufacturing a semiconductor device, comprising at least the steps of:
step S1, providing a substrate, on which a plurality of discrete fin structures are formed;
step S2, forming a protective layer which covers the top surface and the side wall of the fin structure and extends to cover the surface of the substrate exposed by the gap between the adjacent fin structures;
step S3, forming a filler material layer on the surface of the protection layer, wherein the filler material layer at least fills the gap between the adjacent fin structures;
step S4, performing subsequent processes on the substrate including the protection layer and the filling material layer to form a FinFET device structure including a source region, a drain region, and a metal gate.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a top surface of the filler material layer formed in step S3 is higher than a top surface of a protective layer covering a top surface of the fin structure;
after the step S3, the method further includes:
and carrying out top surface planarization on the filling material layer until the top surface of the protective layer covered on the fin structure top surface is exposed.
3. The method for manufacturing a semiconductor device according to claim 2, wherein after the step S3, the method further comprises:
etching back the filling material layer to expose the protective layer covered on the top surface of each fin structure and the side wall with partial height;
forming a dummy gate spanning over a plurality of the fin structures and surrounding sidewalls and a top surface of a partial region of the fin structures;
forming a source electrode and a drain electrode in the fin structures at two sides of each virtual grid electrode, and removing the virtual grid electrodes to expose the fin structures between the source electrode and the drain electrode for forming a channel;
and forming a metal gate on the surface of the fin structure between the exposed source electrode and the exposed drain electrode.
4. The method of manufacturing a semiconductor device according to claim 3, wherein after forming a source and a drain in the fin structure on both sides of each of the dummy gates and removing the dummy gates to expose the fin structure between the source and the drain for forming a channel, the method further comprises:
and removing the protective layer on the top surface and the side wall of the fin structure between the exposed source electrode and the exposed drain electrode for forming the channel, and enabling the top surface of the protective layer remaining on the side wall of the fin structure to be at least flush with the top surface of the filling material layer remaining in the gap between the adjacent fin structures.
5. The method of manufacturing a semiconductor device according to claim 3, wherein after said etching back said layer of filler material to expose said protective layer overlying a top surface of each of said fin structures and a portion of a height of a sidewall thereof, said method further comprises:
and removing the protective layer covered on the exposed top surface of each fin structure and the side wall of partial height, and enabling the top surface of the protective layer left on the side wall of the fin structure to be at least flush with the top surface of the filling material layer left in the gap between the adjacent fin structures.
6. The method of manufacturing a semiconductor device according to claim 4 or 5, wherein after removing the protective layer on the top surface and the sidewalls of the fin structure between the exposed source and drain for forming the channel, or after removing the protective layer covering on the top surface and the sidewalls of a part of the height of each of the exposed fin structures, the method further comprises:
the top surface of the remaining protective layer on the side wall of the fin structure is lower than the top surface of the filling material layer remaining in the gap between the adjacent fin structures, so that a plurality of first shallow trenches are surrounded by the remaining filling material layer, the fin structure and the remaining protective layer on the side wall of the fin structure;
and filling an isolation material layer in each first shallow trench, so that the top surface of the filled first shallow trench is flush with the top surface of the filling material layer remained in the gap between the adjacent fin structures.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the material of the filler material layer and the material of the spacer material layer are the same.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate is a silicon substrate, and a material of the protective layer includes germanium silicide.
9. The method of manufacturing a semiconductor device according to claim 3, wherein the step of forming a source and a drain in the fin structure on both sides of each of the dummy gates comprises:
removing the substrate in the fin structures in partial areas on two sides of the virtual grid electrode and the protective layers on the side walls on two sides of the substrate so as to form second shallow trenches in the fin structures on two sides of the virtual grid electrode respectively;
and depositing an epitaxial material layer in the second shallow trench so that the epitaxial material layer at least fills the second shallow trench to form the source and the drain.
10. A method for manufacturing a semiconductor device according to claim 9, wherein the epitaxial material layer comprises at least one of silicon, silicon phosphide, silicon carbophosphide and germanium silicide.
11. A semiconductor device produced by the production method according to any one of claims 1 to 10.
CN202210234273.7A 2022-03-10 2022-03-10 Semiconductor device and method for manufacturing the same Pending CN114464523A (en)

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