CN114461471A - Method, device and medium for judging PCIE link training process state - Google Patents
Method, device and medium for judging PCIE link training process state Download PDFInfo
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Abstract
The application discloses a method, a device and a medium for judging PCIE link training process state, and relates to the technical field of computers. Firstly, establishing a PCIE link between bridge equipment and terminal equipment; then polling the real-time information of each register of the bridge equipment; and finally, determining each state in the PCIE link training process according to the real-time information of each register, so that a user can conveniently look up PCIE link training state data in real time. Therefore, in the method, on one hand, each state in the PCIE link training process is acquired without the register outside the bridge device, and can be acquired only through the register of the bridge device; on the other hand, each state in the PCIE link training process is obtained according to the real-time information by polling the real-time information of each register of the bridge equipment, so that a user can be ensured to look up PCIE link training state data in real time.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, and a medium for determining a state of a PCIE link training process.
Background
PCI Express (PCIE), as a high-speed serial computer expansion bus standard, has been developed for about two decades, and is widely applied to products with different architectures, such as X86 architecture product, ARM architecture product, and the like, and is widely applied to products with different types, such as a server, a desktop, a mobile tablet, and the like. Peripheral devices of the PCIE interface are also various and huge in number, including a display card device, a storage device, and a network card device. Taking a server product as an example, in a research and development process, a server needs to perform compatibility development and testing on different types of PCIE devices, and not only can a newer PCIE device be used, but also an older PCIE device can be compatible. The PCIE link training state process is a process of negotiation connection between a PCIE interface of the server and an external PCIE equipment link, and research personnel consult each state information of the state process in real time, so that the PCIE link training state process plays a great help role in compatibility debugging of the PCIE equipment.
The existing special register of the processor chip is used for storing the link training state data, and the special register of the chip is only used for debugging and is not open to people except chip manufacturers. Some chip manufacturers require to purchase expensive debugging equipment, and the server needs to be changed from a normal mode to a debugging mode, so that the PCIE link training state data can be consulted in real time. For example, the intel processor chip, the user cannot look up the register storing the training state (keeping the user secret), and the user cannot look up the training state of the PCIE link in real time by purchasing additional hardware debugging equipment and modifying the server to the debugging mode and then by using the debugging equipment.
Therefore, how to facilitate the user to refer to the PCIE link training state data in real time is a problem that needs to be solved urgently by those skilled in the art.
Disclosure of Invention
The application aims to provide a method, a device and a medium for judging the PCIE link training process state, which are used for a user to look up PCIE link training state data in real time.
In order to solve the above technical problem, the present application provides a method for determining a state of a PCIE link training process, including:
establishing a PCIE link between bridge equipment and terminal equipment, wherein the bridge equipment is equipment with a register;
polling real-time information of each register of the bridge device;
and determining each state in the PCIE link training process according to the real-time information so as to facilitate a user to consult PCIE link training state data in real time.
Preferably, after determining each state in the PCIE link training process according to the real-time information, the method further includes:
storing each state into a state linked list;
and outputting the state data in the state linked list.
Preferably, the saving each state in the state linked list comprises:
under the condition that the previous state of the current state and the current state are the same state, judging whether the duration time of the state exceeds a first preset time or not;
if yes, the current state is stored in the state linked list;
if not, returning to the step of polling the real-time information of each register of the bridge equipment.
Preferably, the saving each state in the state linked list comprises:
and under the condition that the previous state of the current state and the current state are not the same, storing each state into the state linked list according to the sequence of the states.
Preferably, the judging whether the previous state of the current state and the current state are the same state comprises:
and under the condition that the previous state of the current state and the current state are respectively stored in corresponding storage areas, judging whether the previous state of the current state and the current state are the same state or not.
Preferably, after saving each of the states in the state linked list and before outputting the state data in the state linked list, the method further includes:
judging whether the number of the states in the state linked list reaches a threshold value;
if yes, entering the step of outputting the state data in the state linked list;
if not, returning to the step of polling the real-time information of each register of the bridge equipment.
Preferably, before the establishing a PCIE link between the bridge device and the terminal device, the method further includes:
setting a second preset time;
clearing the link prohibition bit of the bridge device within the second preset time.
In order to solve the above technical problem, the present application further provides a device for determining a state of a PCIE link training process, including:
the system comprises an establishing module, a receiving module and a processing module, wherein the establishing module is used for establishing a PCIE link between bridge equipment and terminal equipment, and the bridge equipment is equipment with a register;
the polling module is used for polling the real-time information of each register of the bridge equipment;
and the determining module is used for determining each state in the PCIE link training process according to the real-time information so as to facilitate a user to consult PCIE link training state data in real time.
In order to solve the above technical problem, the present application further provides a device for determining a state of a PCIE link training process, including:
a memory for storing a computer program;
and the processor is used for realizing the steps of the method for judging the state of the PCIE link training process when the computer program is executed.
In order to solve the above technical problem, the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the method for determining a state of a PCIE link training process is implemented.
The method for judging the PCIE link training process state comprises the steps that firstly, a PCIE link between bridge equipment and terminal equipment is established; then polling the real-time information of each register of the bridge equipment; and finally, determining each state in the PCIE link training process according to the real-time information of each register, so that a user can conveniently look up PCIE link training state data in real time. Therefore, in the method, on one hand, each state in the PCIE link training process is not required to be acquired through a register outside the bridge device, and can be acquired only through the register of the bridge device; on the other hand, by polling the real-time information of each register of the bridge device, each state in the PCIE link training process is acquired according to the real-time information of each bridge device, so that it is ensured that a user can refer to PCIE link training state data in real time.
In addition, the application also provides a device for judging the PCIE link training process state and a computer readable storage medium, which correspond to the mentioned method for judging the PCIE link training process state, and the effect is the same as the above.
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In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
FIG. 1 is a flow chart of triggering an interrupt;
fig. 2 is a flowchart of a method for determining a PCIE link training process state provided in the present application;
fig. 3 is a schematic diagram of a PCIE link training state;
fig. 4 is a structural diagram of an apparatus for determining a PCIE link training process state according to an embodiment of the present application;
fig. 5 is a structural diagram of an apparatus for determining a PCIE link training process state according to another embodiment of the present application;
fig. 6 is a flowchart of a method for determining a state of a PCIE link training process in an application scenario according to this embodiment.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
The core of the application is to provide a method, a device and a medium for judging the PCIE link training process state, which are used for a user to consult PCIE link training state data in real time.
The PCIE link training state process is a process of negotiation connection between a PCIE interface of the server and an external PCIE equipment link, and research personnel consult each state information of the state process in real time, so that the PCIE link training state process plays a great help role in compatibility debugging of the PCIE equipment. In the present application, a System Management Interrupt (SMI) is used to determine a PCIE link training state process. FIG. 1 is a flow chart of triggering an interrupt. As shown in fig. 1, a user inputs slot silk-screen information data of an external PCIE card on a motherboard to a BMC page of a baseboard Management controller, and starts execution, a BMC information processor 1 converts the user input data into position information and stores the position information, and triggers System Management Interrupt (SMI), and an interrupt handler 2 handles Interrupts.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. Fig. 2 is a flowchart of a method for determining a state of a PCIE link training process according to the present application. As shown in fig. 2, the method includes:
s10: and establishing a PCIE link between the bridge equipment and the terminal equipment, wherein the bridge equipment is equipment with a register.
And in the interrupt processing process, judging the PCIE link training state. Fig. 3 is a schematic diagram of a PCIE link training state. As shown in fig. 3, each state of the PCIE link training process includes detection, polling, configuration, normal, power saving, looping, recovery, warm restart, and prohibition, and the state on the link is converted from the detection to the normal state through polling, configuration, and the like according to different conditions, so that the device starts to operate normally. When a fault that the link cannot be trained to a normal state is encountered, the reason of the fault is preliminarily diagnosed by recording each state of the link training process.
In the application, a PCIE standard register is adopted to judge the PCIE link training state process. The PCIE standard register is a series of registers specified by the PCIE specification, and there are many registers, and the slot status register, the link status register, and the correctable error status register are all single registers. Table 1 is a PCIE link training state mapping table. Each state of the PCIE link training process can be reflected by the PCIE standard register, in table 1, the on-site state belongs to the bit of the slot state register, the connection, training, connection width, and connection speed belong to the bit of the link state register, and the reception error belongs to the bit of the correctable error state register.
Table 1 link training state mapping table
Since the PCIE inserted into the server mainboard completes the link training process in the process of starting the server, when a new interrupt is generated, a client needs to retrain or the training does not make the equipment enter a normal working state in the process of starting the server. The designated device is retrained by sending an SMI interrupt. When the designated device is retrained, the bridge device needs to be disconnected from the downstream device and then connected, that is, a PCIE link between the bridge device and the terminal device is established.
S11: polling the registers of the bridge device for real-time information.
After the BIOS program is started, a basic program service library of a System Management Mode (SMM) is first constructed and initialized, an SMI interrupt program that determines a state of a PCIE link training process is registered in the program service library, and then it is determined whether a retrained SMI interrupt is generated, if no interrupt is generated, the process is ended, if a retrained SMI interrupt is generated, the System is switched to the SMM, and the SMI interrupt program that determines the state of the PCIE link training process is called to start execution.
In the interrupt program, firstly, the position information of the retrained bridge device, including a bus number, a device number and a function number, is read from the BMC, then whether the position information is correct or not is judged, if the position information is wrong (for example, no device exists at the position information), the interrupt program is quitted, and if the position information is correct, the information of a link state register, a slot state register and a correctable error state register of the bridge device is read according to the position information. When the information of each register of the bridge device is read according to the position information, the information is read through an IO port or a memory according to a standard reading method specified by the PCIE specification, and the bus number, the device number, the function number, and the register number of the device need to be input, so that the specified register can be read. After reading the information of each register, judging the training state of the current bridge device according to the truth table provided in table 1, and storing the current state into the state linked list. This state is the training state of the current bridge device when the device is not in the normal operating state.
And after the bridge equipment is reconnected with the downstream equipment, the PCIE link training state is judged by polling the real-time information of the PCIE standard register. Since the link training status changes in real time, the bits in the link status register, the slot status register, and the correctable error status register also change in real time. And reading the real-time information of the link status register, the slot status register and the correctable error status register.
S12: and determining each state in the PCIE link training process according to the real-time information so as to facilitate a user to consult PCIE link training state data in real time.
In step S11, the real-time information of each register of the bridge device is read, each bit is extracted, and the link training state is determined according to the truth table in table 1 to determine each state in the PCIE link training process. And converting each state data into a state character string value in a corresponding state, sending the string value corresponding to each state through a serial port, and allowing a user to look up state information of the PCIE link training process through a serial port terminal. It should be noted that, in this embodiment, the output mode of the status string value corresponding to each status data is not limited, the status data may be output after one status data is acquired or after a plurality of status data are acquired, the status data may be output immediately after the status data is acquired, or the data may be output when the user needs to refer to the data, and this is not limited here.
In the method for determining a state of a PCIE link training process provided in this embodiment, a PCIE link between a bridge device and a terminal device is first established; then polling the real-time information of each register of the bridge equipment; and finally, determining each state in the PCIE link training process according to the real-time information of each register, so that a user can conveniently look up PCIE link training state data in real time. Therefore, in the method, on one hand, each state in the PCIE link training process is not required to be acquired through a register outside the bridge device, and can be acquired only through the register of the bridge device; on the other hand, by polling the real-time information of each register of the bridge device, each state in the PCIE link training process is acquired according to the real-time information of each bridge device, so that it is ensured that a user can refer to PCIE link training state data in real time.
In the above embodiment, each state in the PCIE link training process is determined, so that the user can refer to each state in the PCIE link training process in real time. In order to facilitate the user to refer to each state in the PCIE link training process, in an embodiment, after determining each state in the PCIE link training process according to the real-time information, the method further includes:
storing each state in a state linked list;
and outputting the state data in the state linked list.
After determining each state in the PCIE link training process, when a user needs to refer to each state in the PCIE link training process, if the state data is separately stored, each state in the PCIE link training process may be unable to be correctly distinguished. If the PCIE link training process includes three states, the order states are detection, polling, and configuration, but if the states are not stored separately, the states cannot be distinguished, and the order of the states in the PCIE link training process cannot be understood. Therefore, each state can be stored in the state linked list, and in the state linked list, the occurrence sequence of each state in the PCIE link training process can be determined according to the sequence in the state linked list.
Each state is stored in the state linked list, the data in the state linked list needs to be further processed and can be looked up by a user, namely the training state data in the state linked list needs to be converted into the state character string values of the corresponding states, all the state character string values are sequentially sent out through the serial port, and the user can look up the state information of the PCIE link training process through the serial port terminal. The sequence of each state occurrence is recorded in the state linked list, so that each state can be output according to the sequence through the serial port, and a user can visually know the sequence of the states and the information of each state in the PCIE link training process.
In the embodiment, after each state in the PCIE link training process is determined according to the real-time information, each state is stored in the state linked list, and the state data in the state linked list is output.
In the above embodiment, each state data is stored in the state linked list, but the state data stored in the state linked list is output only when the state number reaches a certain number, so that if the same state is determined multiple times according to the real-time information of each register, the state data cannot be output, and thus, a user cannot refer to each state in the PCIE link training process. Thus saving the respective states into a state linked list includes:
under the condition that the previous state of the current state and the current state are the same state, judging whether the state duration time exceeds a first preset time;
if yes, saving the current state into a state linked list;
if not, returning to the step of polling the real-time information of each register of the bridge equipment.
Reading real-time information of each register of the bridge device, judging a link training state according to a truth table in table 1, and when a previous state of a current state and the current state are the same state, judging the timeout time of each state in order to output state data in a state linked list to a certain amount. When recording the duration time of each state, firstly recording the time of the timer before reading the real-time information of each register, and then recording the time of the timer again when judging that the previous state of the current state and the current state are the same state, thus obtaining the duration time of each state. When the duration time of each state exceeds a first preset time, storing the current state into a state linked list; and returning to the step of polling the real-time information of each register of the bridge equipment when the duration time of each state does not exceed the first preset time. The setting of the first preset time is not limited, and in implementation, an appropriate preset time is selected according to actual conditions.
The judgment of the timeout time of each state provided by this embodiment is performed, and since the state data in the state linked list can be output only when reaching a certain amount of data, the timeout time of each state is judged, so that the data in the state linked list can reach a certain amount, and then the user can refer to each state in the PCIE link training process.
In an embodiment, it may also happen that the previous state of the current state is not the same state as the current state. At this time, in order to make the user know each state and the sequence of each state in the PCIE link training process, in implementation, as a preferred implementation, the saving each state in the state linked list includes:
and under the condition that the previous state of the current state and the current state are not the same, storing each state into the state linked list according to the sequence of the states.
And when the previous state and the current state of the current state are not the same state by reading the real-time information of each register of the bridge equipment, storing each state into a state linked list according to the sequence of the states. If the previous state of the current state is state A and the current state is state B, when the state A is different from the state B, the state A data is firstly stored in the state linked list, and then the state B data is stored in the state A. Therefore, the previous state is in the state linked list, and then the current state is in the state linked list, namely, the states are stored in the state linked list according to the sequence of the states.
In this embodiment, under the condition that the previous state of the current state and the current state are not the same, the states are stored in the state linked list according to the sequence of the states, so that a user can conveniently know the states and the sequence of the states in the PCIE link training process.
In practice, in order to determine whether the previous state of the current state is the same as the current state, it is necessary to store the corresponding state after each state is obtained. In order to distinguish different states, as a preferred embodiment, the determining whether the previous state of the current state and the current state are the same state includes:
and under the condition that the previous state and the current state of the current state are respectively stored in the corresponding storage areas, judging whether the previous state and the current state of the current state are the same state or not.
After each state is obtained, the corresponding state is stored, so that the corresponding state can be conveniently compared with the next state, and whether the states are the same or not is judged. During storage, different states can be stored in the same storage area, and can also be stored in different storage areas. However, in the case of storing different states in the same storage area, it is necessary to ensure that the two states can be distinguished; and under the condition that the two states have corresponding storage areas, when judging whether the two states are the same state, the state values can be taken out from the respective corresponding storage areas for judgment, and then the two states can be effectively distinguished. If the information of each register is read for the first time, the initial value does not exist in the storage area, so the value of the state A can be stored in the storage area of the state A, then the information of each register is read, the corresponding bit value is converted into the link training state value and is stored in the storage area of the state B, and the comparison is carried out to judge whether the state A is the same as the state B or not.
The different storage areas are stored with different states, and when the two states are judged to be the same state, the state values can be taken out from the respective corresponding storage areas to be judged, so that the two states can be effectively distinguished, and the accuracy of judging whether the two states are the same state is improved.
When the number of states stored in the state linked list is small, incomplete recording of each state in the PCIE link training process may occur; when the amount of state data stored in the state linked list is large, the real-time information of each register needs to be read for many times, which increases the time for judging the state in the PCIE link training process. Therefore, in order to determine each state in the PCIE link training process in a short time, in implementation, after saving each state in the state linked list, before outputting state data in the state linked list, the method further includes:
judging whether the number of states in the state linked list reaches a threshold value;
if yes, entering a step of outputting state data in the state linked list;
if not, returning to the step of polling the real-time information of each register of the bridge equipment.
After each state is stored in the state linked list, under the condition that the state quantity in the state linked list reaches a threshold value, outputting state data in the state linked list; and when the number of the states in the state linked list does not reach the threshold value, returning to the step of polling the real-time information of each register of the bridge equipment again, namely acquiring new state data, and outputting the state data in the state linked list until the state data in the state linked list reaches the threshold value. In implementation, the setting of the threshold is not limited, the threshold should include each state in the PCIE link training process as much as possible, and the number of the thresholds should not be too large. In general, the state linked list can store 65 state data, 1 current state (no link training is performed again) and 64 training states in total, after the data is stored in the state linked list, whether the number of the states in the state linked list reaches 64 is judged, if not, the timer time is recorded again, the training state starts to be read, and if 64 states are reached, the last state B data is stored in the 65 th data in the state linked list.
In this embodiment, the state data in the state linked list is output when the state data in the state linked list reaches the threshold, so that a user can determine each state in the PCIE link training process in a short time.
Because the PCIE inserted in the server mainboard finishes the link training process in the starting process of the server, when new interruption occurs, a client needs to retrain or the training does not make the equipment enter a normal working state in the starting process. In order to ensure that the newly established link is not affected by the link that has been established in the booting process, in an implementation, as a preferred implementation manner, before establishing a PCIE link between the bridge device and the terminal device, the method further includes:
setting a second preset time;
clearing the link inhibit bit of the bridge device within a second preset time.
In order to disconnect and reconnect the bridge device to the downstream device, a second preset time is set, and the link inhibit bit of the bridge device is cleared within the second preset time. The setting of the second time is not limited, and in practice, an appropriate second preset time can be selected according to actual situations. And setting a link prohibition bit in the link controller of the bridge equipment, waiting for a second preset time, clearing the link prohibition bit, and carrying out link training again on the bridge equipment and the downstream equipment.
In order to disconnect and reconnect the bridge device and the downstream device, the second preset time is set, and then the link prohibition bit is cleared, which ensures that the newly established link is not affected by the established link in the boot process as much as possible, thereby ensuring that the user can acquire each state in the PCIE link training process as accurately as possible.
In the above embodiments, the method for determining the state of the PCIE link training process is described in detail, and the present application also provides an embodiment corresponding to the apparatus for determining the state of the PCIE link training process. It should be noted that the present application describes the embodiments of the apparatus portion from two perspectives, one from the perspective of the function module and the other from the perspective of the hardware.
Fig. 4 is a structural diagram of an apparatus for determining a PCIE link training process state according to an embodiment of the present application. The present embodiment is based on the angle of the function module, including:
the establishing module 10 is configured to establish a PCIE link between a bridge device and a terminal device, where the bridge device is a device with a register;
the polling module 11 is used for polling the real-time information of each register of the bridge equipment;
the determining module 12 is configured to determine each state in the PCIE link training process according to the real-time information, so that a user refers to PCIE link training state data in real time.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
In the apparatus for determining a state of a PCIE link training process provided in this embodiment, a PCIE link between a bridge device and a terminal device is first established through an establishing module; then polling the real-time information of each register of the bridge equipment through a polling module; and finally, determining each state in the PCIE link training process according to the real-time information through a determining module. Therefore, in the device, on one hand, each state in the PCIE link training process is not required to be acquired through a register outside the bridge equipment, and can be acquired only through the register of the bridge equipment; on the other hand, by polling the real-time information of each register of the bridge device, each state in the PCIE link training process is acquired according to the real-time information of each bridge device, so that it is ensured that a user can refer to PCIE link training state data in real time.
Fig. 5 is a block diagram of an apparatus for determining a PCIE link training process state according to another embodiment of the present application. In this embodiment, based on a hardware angle, as shown in fig. 5, the apparatus for determining a state of a PCIE link training process includes:
a memory 20 for storing a computer program;
the processor 21 is configured to implement the steps of the method for determining the PCIE link training process status as mentioned in the foregoing embodiment when executing the computer program.
The device for determining the state of the PCIE link training process provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.
The processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The Processor 21 may be implemented in hardware using at least one of a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), and a Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in a wake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a Graphics Processing Unit (GPU) which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 21 may further include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.
The memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing the following computer program 201, wherein after being loaded and executed by the processor 21, the computer program can implement relevant steps of the method for determining the state of the PCIE link training process disclosed in any one of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202, data 203, and the like, and the storage manner may be a transient storage manner or a permanent storage manner. Operating system 202 may include, among others, Windows, Unix, Linux, and the like. The data 203 may include, but is not limited to, data related to the above-mentioned method of determining the status of the PCIE link training process, and the like.
In some embodiments, the means for determining the status of the PCIE link training process may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
Those skilled in the art will appreciate that the structure shown in fig. 5 does not constitute a limitation on the means for determining the PCIE link training process status, and may include more or fewer components than those shown.
The device for judging the state of the PCIE link training process provided by the embodiment of the application comprises a memory and a processor, wherein when the processor executes a program stored in the memory, the following method can be realized: the effect of the method for judging the PCIE link training process state is the same as that of the method.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps as set forth in the above-mentioned method embodiments.
It is understood that, if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The computer-readable storage medium provided by the present application includes the above-mentioned method for determining the state of the PCIE link training process, and the effect is the same as above.
In order to make those skilled in the art better understand the technical solution of the present application, the present application is further described in detail below with reference to fig. 6. Fig. 6 is a flowchart of a method for determining a state of a PCIE link training process in an application scenario according to this embodiment. As shown in fig. 6, the method includes:
s13: registering an SMI interrupt service program;
s14: judging whether SMI interruption is generated, if so, entering step S15, otherwise, ending;
s15: calling an SMI interrupt program;
s16: acquiring position information;
s17: judging whether the position information is correct or not; if yes, the process proceeds to step S18, otherwise, the process proceeds to step S35;
s18: judging the current training state and storing the current training state in a state linked list;
s19: starting training by re-linking;
s20: recording the time of a timer;
s21: reading the relevant state register information;
s22: judging whether the state information is read for the first time; if yes, go to step S23, S21; if not, go to step S24;
s23: judging a training state and storing a state A;
s24: judging a training state and storing a state B;
s25: judging whether the states A and B are the same; if yes, go to steps S26, S27; if not, the flow proceeds to steps S29, S30 and S31;
s26: recording the time of a timer;
s27: judging whether the time is out; if yes, go to steps S28, S31; if not, returning to the step S21;
s28: storing the state A data into a state linked list;
s29: storing the state A data into a state linked list;
s30: saving the state B data to the state A;
s31: whether the state number of the state linked list reaches 64; if yes, go to step S32, otherwise, go back to step S20;
s32: storing the state B data into a state linked list;
s33: converting the state linked list data;
s34: transmitting the state information through a serial port;
s35: the SMI interrupt routine is exited.
Therefore, in the flow chart, on one hand, each state in the PCIE link training process does not need to be acquired by a register outside the bridge device, but can be acquired only by each register of the bridge device; on the other hand, by polling the real-time information of each register of the bridge device, each state in the PCIE link training process is acquired according to the real-time information of each bridge device, so that it is ensured that a user can refer to PCIE link training state data in real time.
The method, the apparatus, and the medium for determining the state of the PCIE link training process provided in the present application are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed in the embodiment corresponds to the method disclosed in the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A method for judging the state of a PCIE link training process is characterized by comprising the following steps:
establishing a PCIE link between bridge equipment and terminal equipment, wherein the bridge equipment is equipment with a register;
polling real-time information of each register of the bridge device;
and determining each state in the PCIE link training process according to the real-time information so as to facilitate a user to consult PCIE link training state data in real time.
2. The method of claim 1, wherein after determining each state in the PCIE link training process according to the real-time information, the method further comprises:
storing each state into a state linked list;
and outputting the state data in the state linked list.
3. The method of claim 2, wherein the storing each state in a state linked list comprises:
under the condition that the previous state of the current state and the current state are the same state, judging whether the duration time of the state exceeds a first preset time or not;
if yes, the current state is stored in the state linked list;
if not, returning to the step of polling the real-time information of each register of the bridge equipment.
4. The method of claim 2, wherein the storing each state in a state linked list comprises:
and under the condition that the previous state of the current state and the current state are not the same, storing each state into the state linked list according to the sequence of the states.
5. The method of claim 3 or 4, wherein determining whether a previous state of the current state and the current state are the same state comprises:
and under the condition that the previous state of the current state and the current state are respectively stored in corresponding storage areas, judging whether the previous state of the current state and the current state are the same state or not.
6. The method according to claim 3 or 4, wherein after the saving of each of the states in a state linked list and before the outputting of the state data in the state linked list, the method further comprises:
judging whether the number of the states in the state linked list reaches a threshold value;
if yes, entering the step of outputting the state data in the state linked list;
if not, returning to the step of polling the real-time information of each register of the bridge equipment.
7. The method according to claim 1, wherein before the establishing the PCIE link between the bridge device and the terminal device, the method further comprises:
setting a second preset time;
clearing the link prohibition bit of the bridge device within the second preset time.
8. An apparatus for determining a state of a PCIE link training process, comprising:
the system comprises an establishing module, a receiving module and a processing module, wherein the establishing module is used for establishing a PCIE link between bridge equipment and terminal equipment, and the bridge equipment is equipment with a register;
the polling module is used for polling the real-time information of each register of the bridge equipment;
and the determining module is used for determining each state in the PCIE link training process according to the real-time information so as to facilitate a user to consult PCIE link training state data in real time.
9. An apparatus for determining a state of a PCIE link training process, comprising:
a memory for storing a computer program;
a processor configured to implement the steps of the method for determining a status of a PCIE link training process according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, having a computer program stored thereon, where the computer program is executed by a processor to implement the steps of the method for determining the status of a PCIE link training process according to any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210073387.8A CN114461471A (en) | 2022-01-21 | 2022-01-21 | Method, device and medium for judging PCIE link training process state |
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| CN202210073387.8A CN114461471A (en) | 2022-01-21 | 2022-01-21 | Method, device and medium for judging PCIE link training process state |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115314416A (en) * | 2022-07-15 | 2022-11-08 | 苏州浪潮智能科技有限公司 | Network card state automatic detection method and device, electronic equipment and storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115314416A (en) * | 2022-07-15 | 2022-11-08 | 苏州浪潮智能科技有限公司 | Network card state automatic detection method and device, electronic equipment and storage medium |
| CN115314416B (en) * | 2022-07-15 | 2023-07-14 | 苏州浪潮智能科技有限公司 | Network card state automatic detection method and device, electronic equipment and storage medium |
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Application publication date: 20220510 |