CN115168119A - PCIE (peripheral component interface express) link detection method, device and medium for server - Google Patents
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Abstract
The application relates to the field of server bus design and discloses a method, a device and a medium for detecting a PCIE link of a server. And under the condition of no error reporting, calling the error injection script to construct an error scene and judging whether the BIOS log contains error records and alarm information corresponding to the error scene, so that the test of the alarm capability of the server is realized. By adopting the technical scheme, the BIOS log is also called after the server is normally started, and whether an error exists in the starting process of the server or not is judged. And when no error exists, an error scene is established, whether the BIOS log can normally record the error is verified, and the stability of the PCIE link is verified more comprehensively.
Description
Technical Field
The present application relates to the field of server bus design, and in particular, to a method, an apparatus, and a medium for detecting a PCIE link of a server.
Background
A PCIE device is an indispensable Component in a server, and the performance, calculation, and function of the server are related to the PCIE device, and the PCIE device also relates to calculation, storage, a network, and the like of the server, and plays an important role in the use of the server.
In the prior art, whether the connection of the PCIE device is stable is determined by determining whether the server can be normally started, but the stability of the connection of the PCIE device cannot be comprehensively reflected only by whether the server can be started, and in subsequent use of the PCIE device, connection may be interrupted due to an undiscovered error, which affects the service.
Therefore, how to comprehensively detect the stability of a connection link of a PCIE device is an urgent problem to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide a method, a device and a medium for detecting a PCIE link of a server, which are used for providing more comprehensive detection when detecting the stability of the PCIE link.
In order to solve the above technical problem, the present application provides a method for detecting a PCIE link of a server, including:
after the server is normally started, executing a preset program to call a BIOS log;
judging whether the BIOS log has error report;
if no error is reported, calling a preset error injection script to construct an error scene;
after the registration script is operated, judging whether the BIOS log contains error records and alarm information corresponding to the error scene;
and if not, determining that the PCIE link is unstable.
Preferably, the method further comprises the following steps:
after the error record and the alarm information corresponding to the error scene are obtained, the PCIE link is recovered and whether the recovery of the PCIE link is successful or not is confirmed;
and if the recovery is successful, entering the step of confirming that the PCIE link is stable, and if the recovery is unsuccessful, entering the step of confirming that the PCIE link is unstable.
Preferably, if the error scenario is a plurality of recoverable error scenarios, the recovering the PCIE link and determining whether the recovery of the PCIE link is successful includes:
restarting the server to recover the PCIE link or calling a preset script to recover the PCIE link;
judging whether the PCIE link is recovered successfully;
if yes, returning to the step of calling the preset error injection script to construct the error scene until the construction of all the recoverable error scenes is completed.
Preferably, if the error scenario is an unrecoverable error scenario, the recovering the PCIE link and determining whether the PCIE link is successfully recovered includes:
and sending prompt information to perform manual recovery and manually judging whether the PCIE link is successfully recovered.
Preferably, after confirming that the PCIE link recovery is successful, the method further includes:
calling a resource allocation script to create a plurality of server resource allocation scenes;
and confirming the stability of the PCIE link resource allocation according to the resource allocation result.
Preferably, after confirming that the PCIE link recovery is successful, the method further includes:
and judging whether the training and initialization of the PCIE link are normal or not, and if so, entering the step of confirming the stability of the PCIE link.
In order to solve the above technical problem, the present application further provides a device for detecting a PCIE link of a server, where the device includes:
the calling module is used for executing a preset program to call the BIOS log after the server is normally started;
the first judgment module is used for judging whether the BIOS log has errors or not;
the construction module is used for calling a preset error injection script to construct an error scene if no error is reported;
the second judgment module is used for judging whether the BIOS log contains error records and alarm information corresponding to the error scene after the registration script is operated;
and the confirming module is used for confirming that the PCIE link is stable if the PCIE link is stable, and confirming that the PCIE link is unstable if the PCIE link is not stable.
Preferably, the method further comprises the following steps:
the recovery module is used for recovering the PCIE link and confirming whether the PCIE link is successfully recovered or not after the error record and the alarm information corresponding to the error scene are obtained;
and if the recovery is successful, entering the step of confirming that the PCIE link is stable, and if the recovery is unsuccessful, entering the step of confirming that the PCIE link is unstable.
Preferably, the method further comprises the following steps:
the resource allocation module is used for calling a resource allocation script to create a plurality of server resource allocation scenes after the PCIE link is successfully recovered; and confirming the stability of the PCIE link resource allocation according to the resource allocation result.
Preferably, the method further comprises the following steps:
and the training and initialization module is used for judging whether the training and initialization of the PCIE link are normal or not after the PCIE link is confirmed to be successfully recovered, and if so, entering the step of confirming that the PCIE link is stable.
In order to solve the above technical problem, the present application further provides another server PCIE link detection apparatus, where the apparatus includes a memory for storing a computer program;
a processor, configured to implement the steps of the server PCIE link detection method as described above when the computer program is executed.
In order to solve the technical problem, the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the server PCIE link detection method are implemented.
According to the PCIE link detection method for the server, after the server is normally started, the preset program is executed to call the BIOS log, and whether the PCIE link is stable or not is judged according to whether an error exists in the BIOS log or not. And under the condition of no error report, calling a preset error injection script to construct an error scene, and after the registration script is operated, judging whether the BIOS log contains error records and alarm information corresponding to the error scene, so that the test of the alarm capability of the server is realized, and further, if the BIOS log can normally record errors, the PCIE link is confirmed to be stable, otherwise, the PCIE link is confirmed to be unstable. Compared with the prior art, the stability of the PCIE link can be determined only by whether the server can be normally started or not, and the stability of the actual PCIE link cannot be comprehensively and accurately reflected. When no error exists, an error scene is also constructed, whether the BIOS log can normally record the error is verified, the stability of the PCIE link is verified more comprehensively, and the inaccuracy of PCIE link detection caused by accident is avoided.
In addition, the server PCIE link detection apparatus and medium provided in the present application correspond to the server PCIE link detection method described above, and the effect is the same as above.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart of a PCIE link detection method of a server according to an embodiment of the present application;
fig. 2 is a structural diagram of a PCIE link detection apparatus of a server according to an embodiment of the present application;
fig. 3 is a structural diagram of another server PCIE link detection apparatus according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
PCIE uses the popular point-to-point serial connection in the industry, and compared to PCI and earlier shared parallel architectures of computer buses, each device has its own dedicated connection, and does not need to request bandwidth from the entire bus, and can increase the data transmission rate to a very high frequency, reaching a high bandwidth that PCI cannot provide. The PCIE is a bus interface of a new generation at present (the PCIE with a video card, a sound card, and a solid state disk is more common), and is used to replace an original novel bus interface of the PCI that has reached a bottleneck in improving system performance, so that an extremely high bandwidth can be provided, and the demand of the system is met. The PCIE bus supports a bidirectional transmission mode and a data sub-channel transmission mode, where the data sub-channel transmission mode is an x1, x2, x4, x8, x12, and x16 multi-channel connection of the PCIE bus, the x1 unidirectional transmission bandwidth may reach 250MB/s, and the bidirectional transmission bandwidth may reach 500MB/s.
Currently, in the field of server bus design, PCIE is the latest bus and interface standard, and includes different bus bit widths of X1, X4, X8, X16, and the like. The PCIE specification is connected from 1 lane to 32 lanes, and has very strong scalability, so as to meet different requirements of different system devices on data transmission bandwidths. In order to meet high scalability, PCIE has become an indispensable expansion interface, and usually some RAID cards, SAS cards, HBA cards, and other devices of the PCIE interface are extrapolated to meet different customer requirements, and the signal quality of PCIE directly affects the functions and performance of these extrapolated cards. In order to ensure that the extrapolated PCIE device can stably and efficiently operate, the PCIE link and the stability must meet the PCIE protocol specification. In research and development tests, the quality of a PCIE signal indirectly represents the state and bandwidth of a PCIE link, and the stability of the PCIE signal is usually verified by measuring key parameters such as the bandwidth and the rate of the PCIE link.
However, in the existing test, whether the PCIE device connection is stable is determined by determining whether the server can be normally started, but the stability of the device connection cannot be fully reflected only by whether the server can be started, and in subsequent use of the device, connection interruption may be caused by an undiscovered error, which affects service execution.
The core of the application is to provide a method, a device and a medium for detecting a PCIE link of a server, which are used for providing more comprehensive detection when detecting the stability of the PCIE link.
In order that those skilled in the art will better understand the disclosure, the following detailed description is given with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for detecting a PCIE link of a server according to an embodiment of the present application, and as shown in fig. 1, the method includes:
s10: and after the server is normally started, executing a preset program to call the BIOS log.
The execution subject in this embodiment may be a PCIE link detection device in a server, which implements communication with a connected client (e.g., a RAID card, an SAS card, and an HBA card). It should be noted that, before performing PCIE link detection, an add-in card should be inserted into a server in advance, and in order to comprehensively test a PCIE link of the server, interfaces with various bit widths on the server should be inserted into corresponding devices to cover all bandwidth and rate scenarios supported by the server.
The Basic Input Output System (BIOS) is a set of programs that is fixed on a ROM chip on a main board in a computer, and stores the most important Basic Input and Output programs of the computer, a self-test program after power-on, and a System self-starting program, and can read and write specific information set by the System from a CMOS. Its primary function is to provide the lowest level, most direct hardware setup and control for the computer. In addition, the BIOS provides some system parameters to the operating system. The change of system hardware is hidden by BIOS, and programs use BIOS functions rather than directly control the hardware. Modern operating systems ignore the abstraction layer provided by BIOS and directly control the hardware components.
In step S10, after the server is normally started, a preset program is called, the BIOS log is automatically called, and whether an error record exists in the log is detected. It can be understood that after the external plug-in card is inserted, the server refreshes the BIOS image, and during the starting process, the server also automatically detects the log filtering, the system command, and the key parameters of the device tree to perform the preliminary environmental detection. After the server is normally started, the BIOS log is called to judge whether error reporting records exist or not, and the stability of the running environment of the server is further guaranteed.
It can be understood that if the server is not started normally or the BIOS log has an error report record, it indicates that there is a problem in the PCIE connection between the server and the client, and the relevant information of the error can be obtained through the BIOS log without performing subsequent steps. If there is no error in the BIOS, it is necessary to verify whether the server can report an error normally, so step S12 is performed.
S11: and judging whether the BIOS log has error, if not, entering the step S12.
S12: and calling a preset error injection script to construct an error scene.
In step S12, when there is no error report in the BIOS log, a preset error injection script is called to construct an error scene. In this embodiment, an error scene is constructed to perform error injection on the PCIE link, so as to determine whether the server can perform error reporting normally, thereby implementing detection of server alarm. In specific implementation, a plurality of error scenes can be constructed according to the error injection script so as to detect the alarm capacity of the server more comprehensively.
S13: after the registration script is run, whether the BIOS log contains error records and alarm information corresponding to the error scene is judged, if yes, the step S14 is executed, and if not, the step S15 is executed.
S14: and confirming that the PCIE link is stable.
S15: confirming that the PCIE link is unstable.
In step S13, the verification of the server alarm capability is realized by determining whether the BIOS log includes the error record and the alarm information corresponding to the constructed error scenario, which further explains the stability of the PCIE link. It is understood that, in the case that an error scene is constructed and the BIOS log records errors, the errors should be repaired for detection of other error scenes.
According to the method for detecting the PCIE link of the server, after the server is normally started, the preset program is executed to call the BIOS log, and whether the PCIE link is stable or not is judged according to whether error reporting exists in the BIOS log or not. And under the condition of no error report, calling a preset error injection script to construct an error scene, and after the registration script is operated, judging whether the BIOS log contains error records and alarm information corresponding to the error scene, so that the test of the alarm capability of the server is realized, and further, if the BIOS log can normally record errors, the PCIE link is confirmed to be stable, otherwise, the PCIE link is confirmed to be unstable. Compared with the prior art, the stability of the PCIE link can be determined only by whether the server can be normally started or not, and the stability of the actual PCIE link cannot be comprehensively and accurately reflected. When no error exists, an error scene is also constructed, whether the BIOS log can normally record the error is verified, the stability of the PCIE link is verified more comprehensively, and the inaccuracy of PCIE link detection caused by accident is avoided.
In a specific implementation, after the BIOS log records an error corresponding to an error scenario, the error needs to be repaired to use a subsequent PCIE link.
On the basis of the above embodiment, in this embodiment, the method further includes:
after acquiring error records and alarm information corresponding to the error scene, recovering the PCIE link and confirming whether the PCIE link is successfully recovered;
and if the recovery is successful, entering a step of confirming that the PCIE link is stable, and if the recovery is unsuccessful, entering a step of confirming that the PCIE link is unstable.
In this embodiment, after the PCIE link is recovered to eliminate the error, the PCIE link may be used for subsequent use. In specific implementation, in order to implement a complete test on a PCIE link, there may be multiple error scenarios, and therefore, after the PCIE link is successfully recovered, the step of calling a preset error injection script to construct an error scenario needs to be returned, and tests on other error scenarios are performed until the construction of all error scenarios is completed.
In order to better meet the actual use condition and more accurately detect the stability of the PCIE link, the constructed errors comprise recoverable errors and unrecoverable errors. The recoverable error is an error that can be automatically repaired by the server, and the error can be recovered by restarting, for example. Unrecoverable errors cannot be recovered by restarting the server, and manual recovery is required. By constructing recoverable errors and unrecoverable errors, the stability of the PCIE link is tested in a mode closer to the actual use condition.
In a specific implementation, if the error scenario is a plurality of recoverable error scenarios, recovering the PCIE link and determining whether the PCIE link is recovered successfully includes:
restarting the server to recover the PCIE link or calling a preset script to recover the PCIE link;
judging whether the PCIE link is recovered successfully;
if yes, returning to the step of calling the preset error injection script to construct the error scene until the construction of all recoverable error scenes is completed.
It can be understood that, when the error scenario is multiple recoverable error scenarios, the server may recover the PCIE link by restarting or invoking a preset script, so as to eliminate the error. The recovery process of the PCIE link does not need manual intervention, so that a corresponding running program can be set, after the PCIE link is successfully recovered, the step of calling the preset error injection script to construct an error scene is returned, the test of other error scenes is realized, and the construction of all recoverable error scenes is completed.
According to the method for detecting the PCIE link of the server, provided by the embodiment of the application, for a plurality of recoverable error scenes, the PCIE link can be recovered by restarting the server or calling the preset script, and other error scenes can be still constructed after the PCIE link is successfully recovered, so that the test efficiency of the PCIE link of the server is improved, and the stability of the PCIE link of the server is more accurately detected through a plurality of tests.
It can be understood that manual recovery is required when the error scene is an unrecoverable error scene. In a specific implementation, the steps in the above embodiments may be automatically performed by setting a corresponding running program.
Therefore, in this embodiment, when the error scenario is an unrecoverable error scenario, recovering the PCIE link and determining whether the PCIE link is successfully recovered includes:
and sending prompt information to prompt manual recovery and manually judge whether the PCIE link is successfully recovered.
In this embodiment, the prompt information prompts a technician to manually recover the PCIE link, so as to test the stability of the PCIE link when the error is an unrecoverable error.
In specific implementation, besides the tests on the alarm of the server and the connection of the PCIE link, other tests may be performed.
For example, after the PCIE link recovery is confirmed to be successful, a resource allocation script may also be called to create a variety of server resource allocation scenarios; and confirming the stability of PCIE link resource allocation according to the resource allocation result. After the PCIE link is confirmed to be successfully recovered, whether the training and initialization of the PCIE link are normal or not can be judged, and if the training and initialization of the PCIE link are normal, the step of confirming that the PCIE link is stable is carried out.
It should be noted that, the tests disclosed in this embodiment should be performed when the PCIE link is successfully repaired and it is ensured that no error is reported in the server. The PCIE link stability is tested more comprehensively through the PCIE link resource allocation, the PCIE link training and the initialization test.
In the above embodiments, a detailed description is given to a server PCIE link detection method, and the present application also provides an embodiment corresponding to a server PCIE link detection apparatus. It should be noted that the present application describes the embodiments of the apparatus portion from two perspectives, one is from the perspective of the function module, and the other is from the perspective of the hardware.
Fig. 2 is a structural diagram of a server PCIE link detection apparatus provided in an embodiment of the present application, and as shown in fig. 2, the apparatus includes:
the calling module 10 is used for executing a preset program to call the BIOS log after the server is normally started;
the first judging module 11 is configured to judge whether the BIOS log has an error;
the construction module 12 is configured to invoke a preset error injection script to construct an error scene if no error is reported;
the second judging module 13 is configured to judge whether the BIOS log includes an error record and alarm information corresponding to an error scene after the registration script is run;
the determining module 14 is configured to determine that the PCIE link is stable if the determination result is positive, and determine that the PCIE link is not stable if the determination result is negative.
It should be noted that the structure shown in fig. 2 does not limit the server PCIE link detection apparatus, and in other embodiments, the server PCIE link detection apparatus may further include:
the recovery module is used for recovering the PCIE link and confirming whether the PCIE link is successfully recovered or not after the error record and the alarm information corresponding to the error scene are obtained;
and if the recovery is successful, entering the step of confirming that the PCIE link is stable, and if the recovery is unsuccessful, entering the step of confirming that the PCIE link is unstable.
The resource allocation module is used for calling a resource allocation script to create a plurality of server resource allocation scenes after the PCIE link is confirmed to be successfully recovered; and confirming the stability of the PCIE link resource allocation according to the resource allocation result.
And the training and initialization module is used for judging whether the training and initialization of the PCIE link are normal or not after the PCIE link is confirmed to be successfully recovered, and if the training and initialization are normal, entering the step of confirming the stability of the PCIE link.
Since the embodiment of the apparatus portion and the embodiment of the method portion correspond to each other, please refer to the description of the embodiment of the method portion for the embodiment of the apparatus portion, and details are not repeated here.
According to the PCIE link detection device for the server, after the server is normally started, the preset program is executed to call the BIOS log, and whether the PCIE link is stable or not is judged according to whether an error exists in the BIOS log or not. And under the condition of no error report, calling a preset error injection script to construct an error scene, and after the registration script is operated, judging whether the BIOS log contains error records and alarm information corresponding to the error scene, so that the test of the alarm capability of the server is realized, and further, if the BIOS log can normally record errors, the PCIE link is confirmed to be stable, otherwise, the PCIE link is confirmed to be unstable. Compared with the prior art that the stability of the PCIE link can be determined only by whether the server can be normally started or not, and the stability of the actual PCIE link cannot be comprehensively and accurately reflected, by adopting the technical scheme, the BIOS log is also called after the server is normally started, and whether errors exist in the starting process of the server or not is judged. When no error exists, an error scene is also constructed, whether the BIOS log can normally record the error is verified, the stability of the PCIE link is verified more comprehensively, and the inaccuracy of PCIE link detection caused by accident is avoided.
Fig. 3 is a structural diagram of another server PCIE link detection apparatus provided in the embodiment of the present application, and as shown in fig. 3, the apparatus includes: a memory 20 for storing a computer program;
the processor 21 is configured to implement the steps of the method for detecting a PCIE link of a server according to the above embodiment when executing the computer program.
The PCIE link detection device of the server provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.
The processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The Processor 21 may be implemented in hardware using at least one of a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), and a Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with a Graphics Processing Unit (GPU) which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, the processor 21 may further include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.
The memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing the following computer program 201, where after being loaded and executed by the processor 21, the relevant steps of the server PCIE link detection method disclosed in any one of the foregoing embodiments can be implemented. In addition, the resources stored in the memory 20 may also include an operating system 202, data 203, and the like, and the storage manner may be a transient storage manner or a permanent storage manner. Operating system 202 may include, among others, windows, unix, linux, and the like. Data 203 may include, but is not limited to, pre-set programs, error-filled scripts, and the like.
In some embodiments, the server PCIE link detection apparatus may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
Those skilled in the art will appreciate that the architecture shown in fig. 3 does not constitute a limitation of the server PCIE link detection means and may include more or fewer components than those shown.
The server PCIE link detection apparatus provided in the embodiment of the present application includes a memory and a processor, and when the processor executes a program stored in the memory, the following method can be implemented: after the server is normally started, executing a preset program to call a BIOS log; judging whether the BIOS log has error report; if no error is reported, calling a preset error injection script to construct an error scene; after the registration script is run, judging whether the BIOS log contains error records and alarm information corresponding to the error scene; if yes, the PCIE link is confirmed to be stable, and if not, the PCIE link is confirmed to be unstable.
According to the server PCIE link detection device, after the server is normally started, the preset program is executed to call the BIOS log, and whether the PCIE link is stable or not is judged according to whether error reporting exists in the BIOS log or not. And calling a preset error injection script to construct an error scene under the condition of no error report, and judging whether the BIOS log contains error records and alarm information corresponding to the error scene after running the registration script, so that the alarm capability of the server is tested, and if the BIOS log can normally record errors, the PCIE link is confirmed to be stable, otherwise, the PCIE link is confirmed to be unstable. Compared with the prior art that the stability of the PCIE link can be determined only by whether the server can be normally started or not, and the stability of the actual PCIE link cannot be comprehensively and accurately reflected, by adopting the technical scheme, the BIOS log is also called after the server is normally started, and whether errors exist in the starting process of the server or not is judged. When no error exists, an error scene is also constructed, whether the BIOS log can record the error normally is verified, the stability of the PCIE link is verified more comprehensively, and inaccuracy of PCIE link detection caused by accident is avoided.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps as set forth in the above-mentioned method embodiments.
It is to be understood that if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solutions. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
According to the computer-readable storage medium provided by the application, after the server is normally started, the preset program is executed to call the BIOS log, and whether the PCIE link is stable or not is judged according to whether an error exists in the BIOS log or not. And under the condition of no error report, calling a preset error injection script to construct an error scene, and after the registration script is operated, judging whether the BIOS log contains error records and alarm information corresponding to the error scene, so that the test of the alarm capability of the server is realized, and further, if the BIOS log can normally record errors, the PCIE link is confirmed to be stable, otherwise, the PCIE link is confirmed to be unstable. Compared with the prior art, the stability of the PCIE link can be determined only by whether the server can be normally started or not, and the stability of the actual PCIE link cannot be comprehensively and accurately reflected. When no error exists, an error scene is also constructed, whether the BIOS log can record the error normally is verified, the stability of the PCIE link is verified more comprehensively, and inaccuracy of PCIE link detection caused by accident is avoided.
The method, the apparatus, and the medium for detecting the PCIE link of the server provided in the present application are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, without departing from the principle of the present application, the present application can also make several improvements and modifications, and those improvements and modifications also fall into the protection scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.
Claims (9)
1. A PCIE link detection method for a server is characterized by comprising the following steps:
after the server is normally started, executing a preset program to call a BIOS log;
judging whether the BIOS log has error report;
if no error is reported, calling a preset error injection script to construct an error scene;
after the registration script is operated, judging whether the BIOS log contains error records and alarm information corresponding to the error scene;
and if not, determining that the PCIE link is unstable.
2. The server PCIE link detection method of claim 1, further comprising:
after the error record and the alarm information corresponding to the error scene are obtained, the PCIE link is recovered and whether the recovery of the PCIE link is successful or not is confirmed;
and if the recovery is successful, entering the step of confirming that the PCIE link is stable, and if the recovery is unsuccessful, entering the step of confirming that the PCIE link is unstable.
3. The method according to claim 2, wherein the error scenario is a plurality of recoverable error scenarios, and the recovering the PCIE link and determining whether the PCIE link is recovered successfully comprises:
restarting the server to recover the PCIE link or calling a preset script to recover the PCIE link;
judging whether the PCIE link is recovered successfully;
if so, returning to the step of calling the preset error injection script to construct the error scene until the construction of all the recoverable error scenes is completed.
4. The method of claim 3, wherein if the error scenario is an unrecoverable error scenario, the recovering the PCIE link and determining whether the PCIE link is successfully recovered includes:
and sending prompt information to perform manual recovery and manually judging whether the PCIE link is successfully recovered.
5. The server PCIE link detection method according to claim 2, further comprising, after confirming that the PCIE link recovery is successful:
calling a resource allocation script to create a plurality of server resource allocation scenes;
and confirming the stability of the PCIE link resource allocation according to the resource allocation result.
6. The server PCIE link detection method of claim 5, wherein after confirming that the PCIE link is recovered successfully, further comprising:
and judging whether the training and initialization of the PCIE link are normal or not, and if so, entering the step of confirming the stability of the PCIE link.
7. A server PCIE link detection device is characterized by comprising:
the calling module is used for executing a preset program to call the BIOS log after the server is normally started;
the first judgment module is used for judging whether the BIOS log has error report;
the construction module is used for calling a preset error injection script to construct an error scene if no error is reported;
the second judgment module is used for judging whether the BIOS log contains error records and alarm information corresponding to the error scene after the registration script is operated;
and the confirming module is used for confirming that the PCIE link is stable if the PCIE link is stable, and confirming that the PCIE link is unstable if the PCIE link is not stable.
8. A PCIE link detection device of a server is characterized by comprising a memory for storing computer programs;
a processor configured to implement the steps of the server PCIE link detection method according to any one of claims 1 to 6 when executing the computer program.
9. A computer-readable storage medium, wherein a computer program is stored on the computer-readable storage medium, and when executed by a processor, the computer program implements the steps of the server PCIE link detection method according to any one of claims 1 to 6.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210727080.5A CN115168119A (en) | 2022-06-24 | 2022-06-24 | PCIE (peripheral component interface express) link detection method, device and medium for server |
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| CN202210727080.5A CN115168119A (en) | 2022-06-24 | 2022-06-24 | PCIE (peripheral component interface express) link detection method, device and medium for server |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116582471A (en) * | 2023-07-14 | 2023-08-11 | 珠海星云智联科技有限公司 | PCIE equipment, PCIE data capturing system and server |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116582471A (en) * | 2023-07-14 | 2023-08-11 | 珠海星云智联科技有限公司 | PCIE equipment, PCIE data capturing system and server |
| CN116582471B (en) * | 2023-07-14 | 2023-09-19 | 珠海星云智联科技有限公司 | PCIE equipment, PCIE data capturing system and server |
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