CN114461272A

CN114461272A - Method and system for reconstructing storage module in digital integrated circuit design

Info

Publication number: CN114461272A
Application number: CN202210099756.0A
Authority: CN
Inventors: 程振洪; 秦信刚; 秦泰; 熊庭刚
Original assignee: 709th Research Institute of CSIC
Current assignee: 709th Research Institute of CSIC
Priority date: 2022-01-27
Filing date: 2022-01-27
Publication date: 2022-05-10

Abstract

The invention provides a reconstruction method and a reconstruction system of a storage module in digital integrated circuit design. And then calculating the times of instantiating required for completing the reconstruction of the storage module, and splitting and reconnecting the signal lines according to the mapping relation of the port names before and after the reconstruction of the storage module to form a new storage module instantiating structure. And finally, replacing the corresponding codes in the RTL source code file to form a new storage module instantiated structure, and completing the reconstruction of the storage module. The method realizes the RTL behavior level reconstruction of the memory module, has the characteristics of high accuracy and rapid and repeated iteration optimization, and can improve the efficiency of digital integrated circuit design.

Description

Method and system for reconstructing storage module in digital integrated circuit design

Technical Field

The invention belongs to the technical field of digital integrated circuit design, and particularly relates to a method and a system for reconstructing a storage module in digital integrated circuit design.

Background

The memory is a common information storage module in a digital circuit, has multiple attributes such as data port bit width, storage depth, address bit width, and the like, and is generally used for solving the problem of temporary storage of data inside a chip, for example, as a data Cache for data caching function and an instruction Cache. An IP release package (issue packet) issued by an IP vendor, in which a memory is generally built in a register form, and is sometimes called as a sram (static memory), has a characteristic of high-speed random access, and is very suitable for designing a high-speed digital circuit. However, sram also has the disadvantages of large area and power consumption, so that sram is replaced in the front-end function design process and replaced by a memory module generated by a special memory design tool in the target process, thereby achieving the purpose of reducing area and power consumption.

A conventional method for replacing a memory instantiated structure in RTL (register transfer level) is shown in fig. 1, and comprises the following steps:

step 1: searching positions where memory instantiated structures to be replaced appear in all RTL (register transfer level) source files, and manually calculating parameters of data bit width, storage depth and address bit width in each instantiated parameter;

step 2: generating a new memory library file for a digital front-end design stage in a memory compiling tool according to each memory instantiated parameter, and meeting the time sequence performance of the design requirement after multiple parameter iterations;

and step 3: opening an RTL source file which is not replaced by the memory in an RTL source file directory by using a text editor;

and 4, step 4: manually carrying out name instantiation replacement of the memory and reconnection of the signal line one by one on each memory instantiation code to be replaced in the RTL source code according to the memory name and the port definition in the generated memory library file;

and 5: judging whether the RTL source file is completely replaced, if not, entering a step 3, and if so, entering a step 6;

step 6: the operation is ended.

The operation steps are simplified, and the difficulty in replacing the memory instantiated structure mainly comprises the following steps:

1. in step 1, globally defined parameters need to be searched, and the globally defined parameters are substituted into the memory module instantiated position in the RTL source code to calculate parameters such as data bit width and storage depth, so as to generate a new memory. The step is usually carried out manually in a traditional mode, the operation times are increased linearly along with the memory instantiation times, the repeatability is high, and errors are easy to occur.

2. In step 4, the new memory needs to replace the instantiated structure of the original memory, and the original port connection signal of the memory needs to be disconnected and reconnected to the new memory, which is complicated. If the time sequence optimization problem is considered in the memory generation process, and the size of the newly generated memory is possibly smaller than that of the original memory, the memory cutting problem is also considered in the replacement process. In the conventional mode, memory splicing replacement is completed by manually modifying the RTL source code, which is not reliable, time-consuming and not beneficial to time sequence iteration.

Disclosure of Invention

Aiming at the defects of the prior art, the invention aims to provide a reconstruction method and a reconstruction system of a memory module in digital integrated circuit design, aiming at solving the problems that the conventional reconstruction method of the memory module manually searches global definition parameters, manually modifies RTL source codes to finish memory splicing replacement, is easy to make mistakes, consumes time and is not beneficial to time sequence iteration.

In order to achieve the above object, in a first aspect, the present invention provides a method for reconstructing a memory module in a digital integrated circuit design, including the following steps:

searching all parameter parameters in all RTL source files, analyzing the searched parameter parameters and storing the parameter parameters into a global parameter table; the parameter is a global parameter;

searching the name of an original storage module in all RTL source files, finding the instantiation structure of the original storage module based on the name of the original storage module, extracting the information of the instantiation structure of the original storage module, storing the extracted information into a self-defined hash table, and finishing the initialization of the hash table; the hash table is used for storing the information of the original storage module, the information of the new storage module and the matching relationship information between the original storage module and the new storage module;

updating the instantiated parameters of the original storage module in the hash table into decimal analyzed parameters based on the global parameter table; the instantiation parameters comprise: data end bit width, storage depth and address bit width;

fixing two instantiated parameters of the storage depth and the address bit width of a new storage module to corresponding preset values, designing a data port bit width value of the new storage module by an iteration method until the new storage module obtained by design meets the time sequence design requirement, and taking the data port bit width value at the moment as a data port bit width design value of the new storage module; keeping the name of the new storage module in a hash table;

respectively obtaining port lists of an original storage module and a new storage module, establishing a matching relation between the ports of the original storage module and the new storage module, and storing the matching relation into a hash table;

determining the instantiation times of the new storage module after replacing the original storage module according to the data port bit width value of the original storage module and the data port bit width design value of the new storage module, generating an instantiation structure of the new storage module, and storing the instantiation structure of the new storage module in a hash table;

and replacing the instantiation structure of the original storage module in the RTL source file by the instantiation structure of the new storage module in the hash table, outputting the updated RTL source file, and completing reconstruction of the original storage module.

Optionally, the designing the bit width value of the data port of the new memory module by the iterative method until the new memory module obtained by the designing meets the time sequence design requirement specifically includes the following steps:

s10, determining the initial value of the data port bit width of the new storage module;

s20, presetting a width division coefficient, and setting an initial value of the width division coefficient to 1;

s30, dividing the initial value of the data port bit width by the width division coefficient and rounding up to obtain a new data port bit width value;

s40, generating a new storage module according to the preset values of the storage depth and the address bit width and the new data port bit width value;

and S50, judging whether the new memory module generated in the step S40 meets the time sequence design requirement, if so, taking the new data port bit width value as the data port bit width design value of the new memory module, if not, multiplying the width division coefficient by 2 to be taken as a new width division coefficient, and entering the step S30.

Optionally, the data structure of the customized hash table includes:

the device comprises a storage module instantiated index storage area, an original storage module instantiated parameter storage area, an original storage module name storage area, a new storage module name storage area, an original storage module and external signal connection relation storage area, a storage module port mapping relation storage area, an original storage module instantiated code interval storage area and a new storage module instantiated code storage area;

the storage module instantiation index storage area is used for storing the RTL source file name and the instantiation name of the storage module in the RTL source file;

the original storage module instantiated parameter storage area is used for storing the data end bit width, the storage depth and the address bit width of the original storage module;

the original storage module and external signal connection relation storage area is used for storing the port name and the external signal of the original storage module and the corresponding connection relation between the port name and the external signal;

the storage module port mapping relation storage area is used for storing a port list of an original storage module, a port list of a new storage module and a mapping relation corresponding to the two lists; the port list includes: the device comprises a clock port, a write enable port, a write data port, a read enable port, a read data port and an address port;

and the original storage module instantiated code interval storage area is used for storing an instantiated starting line number and an instantiated ending line number of the original storage module.

Optionally, the determining, according to the data port bit width value of the original memory module and the data port bit width design value of the new memory module, the number of instantiations of the new memory module after replacing the original memory module with the new memory module to generate the instantiating structure of the new memory module specifically includes the following steps:

dividing the data port bit width value of the original storage module by the data port bit width design value, and rounding up to obtain the number of instantiations;

the instantiation name of the new storage module is formed by splicing the instantiation name and the instantiation index of the original storage module, 1 is added to the instantiation index of the new storage module once, until the instantiation index value is the instantiation frequency and is reduced by 1, and the generation of the new storage module instantiation structure is completed; the generated instantiation index of a new instantiation structure is returned to 0;

signals of a clock port, a write enable port, a read enable port and an address port in the original storage module instantiation structure are directly connected to the new instantiation structure body without bit division; except for the last instantiation of the new storage module, signals of a write data port and a read data port need to be divided by using an instantiation index and then are connected to a new instantiation structure;

when the new storage module is instantiated for the last time, for a write data port, except that an instantiation index is needed to be used for signal segmentation, high-order bit filling 0 operation is needed to be carried out on the high-order bit according to the characteristic of bit width matching, and the number of 0 to be filled in the high-order bit is determined by multiplying a data port bit width design value by the number of instantiations minus a data port bit width value of the original storage module; for the read data port, a signal which is matched with the bit width of the read data port of the new memory module needs to be additionally defined to be connected to the new instantiated structural body, and the signal is connected to the original read data signal after being shortened according to the bit width.

Optionally, the parsing and storing the searched parameter into the global parameter table specifically includes the following steps:

for each RTL source file, matching parameters line by line to define grammar, and classifying according to the grammar: defining the parameter values as numerical values, converting the numerical values into decimal numbers, and classifying the decimal numbers into an analyzed parameter table; if the parameter value is not defined as a numerical value, if the parameter value does not contain an operator, classifying the parameter value into an indirect parameter table, and if the parameter value contains the operator, classifying the parameter value into an undefined parameter table;

carrying out iterative analysis on the indirect parameter table, finishing parameter value replacement of the indirect parameter table through searching the analyzed parameter table in each round, merging the parameter values into the analyzed parameter table after each time of replacement until the analysis of all parameters in the indirect parameter table is finished;

and carrying out iterative analysis on the undefined parameter table, finishing parameter value replacement of the undefined parameter table by searching the analyzed parameter table in each round, then calculating based on the replaced parameter value, and merging the calculation result of the parameter value into the analyzed parameter table until the analysis of all parameters in the undefined parameter table is finished.

Optionally, the updating the instantiated parameter of the original storage module in the hash table to a decimal resolved parameter based on the global parameter table specifically includes the following steps:

for each instantiation parameter of the original storage module in the hash table, firstly extracting operators in the instantiation parameter, wherein the operators comprise arithmetic operators and logical operators; taking the extracted operator as a separator of the instantiated parameter, and further separating each sub-parameter forming the instantiated parameter;

respectively and correspondingly replacing each separated sub-parameter by a decimal value in the global parameter table for calculation by inquiring the global parameter table;

and calculating a final decimal value of the instantiation parameters based on operators forming the instantiation parameters and the replaced sub-parameters, and updating the final decimal value of the instantiation parameters to a corresponding position in the hash table.

Optionally, the replacing, by the instantiation structure of the new storage module in the hash table, the instantiation structure of the original storage module in the RTL source file, and outputting the updated RTL source file specifically includes the following steps:

filtering all the new instantiated structure linked lists belonging to the RTL source file from the hash table by using the name of the RTL source file;

taking the initial row number of the instantiated structural body to be replaced as a key word, and performing descending arrangement on the elements of the linked list;

and sequentially taking out each instantiated structural body of the sorted linked list, and replacing codes between the instantiated starting line and the instantiated finishing line of the original storage module in the RTL source file.

In a second aspect, the present invention provides a system for reconfiguring a memory module in a digital integrated circuit design, comprising

The instantiated parameter analyzing unit is used for searching all parameter parameters in all RTL source files, analyzing the searched parameter parameters and storing the parameter parameters into the global parameter table; the parameter is a global parameter;

the system comprises a Hash table initialization unit, a storage unit and a processing unit, wherein the Hash table initialization unit is used for searching the names of original storage modules in all RTL source files, finding the instantiation structure of the original storage modules based on the names of the original storage modules, extracting the information of the instantiation structure of the original storage modules, storing the extracted information into a user-defined Hash table and completing initialization of the Hash table; the hash table is used for storing the information of the original storage module, the information of the new storage module and the matching relationship information between the original storage module and the new storage module;

the instantiated parameter updating unit is used for updating the instantiated parameters of the original storage module in the hash table into decimal analyzed parameters based on the global parameter table; the instantiation parameters comprise: data end bit width, storage depth and address bit width;

the new storage module design unit is used for fixing two instantiated parameters, namely the storage depth and the address bit width, of the new storage module to corresponding preset values, designing a data port bit width value of the new storage module through an iteration method until the new storage module obtained through design meets the time sequence design requirement, and taking the data port bit width value at the moment as a data port bit width design value of the new storage module; keeping the name of the new storage module in a hash table;

the port relation determining unit is used for respectively acquiring port lists of the original storage module and the new storage module, establishing a matching relation between the ports of the original storage module and the new storage module, and storing the matching relation into a hash table;

the new instantiation structure generation unit is used for determining the instantiation times of the new storage module after replacing the original storage module according to the data port bit width value of the original storage module and the data port bit width design value of the new storage module so as to generate the instantiation structure of the new storage module and store the instantiation structure of the new storage module into the hash table;

and the storage module reconstruction unit is used for replacing the instantiated structure of the original storage module in the RTL source file by adopting the instantiated structure of the new storage module in the hash table, outputting the updated RTL source file and completing reconstruction of the original storage module.

Optionally, the new memory module designing unit designs the data port bit width value of the new memory module by an iterative method until the new memory module obtained by design meets the time sequence design requirement, and specifically includes the following steps:

s10, determining the initial value of the data port bit width of the new storage module; s20, presetting a width division coefficient, and setting an initial value of the width division coefficient to 1; s30, dividing the initial value of the data port bit width by the width division coefficient and rounding up to obtain a new data port bit width value; s40, generating a new storage module according to the preset values of the storage depth and the address bit width and the new data port bit width value; and S50, judging whether the new memory module generated in the step S40 meets the time sequence design requirement, if so, taking the new data port bit width value as the data port bit width design value of the new memory module, if not, multiplying the width division coefficient by 2 to be taken as a new width division coefficient, and entering the step S30.

Optionally, the new instantiation structure generating unit determines the number of instantiations of the new storage module after replacing the original storage module according to the data port bit width value of the original storage module and the data port bit width design value of the new storage module, so as to generate the instantiation structure of the new storage module, and specifically includes the following steps: dividing the data port bit width value of the original storage module by the data port bit width design value, and rounding up to obtain the number of instantiations; the instantiation name of the new storage module is formed by splicing the instantiation name and the instantiation index of the original storage module, 1 is added to the instantiation index of the new storage module once, until the instantiation index value is the instantiation frequency and is reduced by 1, and the generation of the new storage module instantiation structure is completed; the generated instantiation index of a new instantiation structure is returned to 0; signals of a clock port, a write enable port, a read enable port and an address port in the original storage module instantiation structure are directly connected to the new instantiation structure body without bit division; except for the last instantiation of the new storage module, signals of a write data port and a read data port need to be divided by using an instantiation index and then are connected to a new instantiation structure; when the new storage module is instantiated for the last time, for a write data port, except that an instantiation index is needed to be used for signal segmentation, high-order bit filling 0 operation is needed to be carried out on the high-order bit according to the characteristic of bit width matching, and the number of 0 to be filled in the high-order bit is determined by multiplying a data port bit width design value by the number of instantiations minus a data port bit width value of the original storage module; for the read data port, a signal which is matched with the bit width of the read data port of the new memory module needs to be additionally defined to be connected to the new instantiated structural body, and the signal is connected to the original read data signal after being shortened according to the bit width.

Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:

The invention provides a method and a system for reconstructing a storage module in digital integrated circuit design, wherein the extracted storage parameters can generate a report form, so that the report form is convenient for inspection and secondary development and use; the reconstruction speed is high, and because the time sequence iteration can be repeatedly carried out, the optimal memory module reconstruction parameter can be quickly found, and the circuit performance is improved; compared with the mode of manually rewriting RTL codes, the method is difficult to make errors, and the code writing errors are easy to occur in manual rewriting.

Drawings

FIG. 1 is a flow diagram of a method for replacing a memory instantiated structure in a conventional RTL file;

FIG. 2 is a flow chart of a method for reconfiguring a memory module according to an embodiment of the present invention;

FIG. 3 is a schematic flow chart of a method for reconfiguring a memory module in a digital integrated circuit design according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a memdit data structure provided in the embodiment of the present invention;

FIG. 5 is a schematic diagram of step S1 in the main flow chart provided by the embodiment of the present invention;

FIG. 6 is a schematic diagram of step S2 in the main flow chart provided by the embodiment of the present invention;

FIG. 7 is a schematic diagram of step S3 in the main flow chart provided by the embodiment of the present invention;

FIG. 8 is a schematic diagram of step S4 in the main flow chart provided by the embodiment of the present invention;

FIG. 9 is a schematic diagram of step S5 in the main flow chart provided by the embodiment of the present invention;

FIG. 10 is a schematic diagram of step S6 in the main flow chart provided by the embodiment of the present invention;

FIG. 11 is a block diagram illustrating step S7 of the main process according to the present invention;

FIG. 12 is a block diagram of a reconstruction system for a memory module according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Fig. 2 is a flowchart of a reconstruction method of a storage module according to an embodiment of the present invention, as shown in fig. 2, including the following steps:

s101, searching all parameter parameters in all RTL source files, analyzing the searched parameter parameters and storing the parameter parameters into a global parameter table; the parameter is a global parameter;

s102, searching the names of the original storage modules in all RTL source files, finding the instantiated structure of the original storage modules based on the names of the original storage modules, extracting the information of the instantiated structure of the original storage modules, storing the extracted information in a self-defined hash table, and finishing initialization of the hash table; the hash table is used for storing the information of the original storage module, the information of the new storage module and the matching relationship information between the original storage module and the new storage module;

s103, updating the instantiated parameters of the original storage module in the hash table into decimal analyzed parameters based on the global parameter table; the instantiation parameters comprise: data end bit width, storage depth and address bit width;

s104, fixing two instantiated parameters of the storage depth and the address bit width of the new storage module as corresponding preset values, designing a data port bit width value of the new storage module by an iteration method until the new storage module obtained by design meets the time sequence design requirement, and taking the data port bit width value at the moment as a data port bit width design value of the new storage module; keeping the name of the new storage module in a hash table;

s105, respectively obtaining port lists of the original storage module and the new storage module, establishing a matching relation between the ports of the original storage module and the new storage module, and storing the matching relation into a hash table;

s106, determining the instantiation times of the new storage module after replacing the original storage module according to the data port bit width value of the original storage module and the data port bit width design value of the new storage module, generating the instantiation structure of the new storage module, and storing the instantiation structure of the new storage module into a hash table;

s107, replacing the instantiated structure of the original storage module in the RTL source file by the instantiated structure of the new storage module in the hash table, outputting the updated RTL source file, and completing reconstruction of the original storage module.

Before explaining the technical solution, it is necessary to introduce a typical memory instantiated structure syntax example shown as follows to facilitate understanding of the following method:

in the memory instantiation structure syntax, dynamic _ sram is the module name of the memory, and the inside of a pair of brackets immediately after the # number is the instantiation parameter table of the memory. From row 2 to row 4, the comma separates 3 instantiated parameters, which are the address bit WIDTH ($ log2(ORG _ DEPTH × 2)), the storage DEPTH (ORG _ DEPTH × 2), and the data port bit WIDTH (CMD1_ WIDTH + CMD2_ WIDTH) of the memory. The values of the 3 instantiated parameters are obtained by operations (including logarithm, multiplication, and addition) from the respective sub-parameters (e.g., ORG _ DEPTH, CMD1_ WIDTH, and CMD2_ WIDTH). U _ ram on the 5 th row is an instantiated name of the memory, when the memory is instantiated, the instantiated names are different for the sake of grammatical differentiation, and for the same group of memories, a method of adding a suffix with a number after the instantiated name is conventionally adopted, such as u _ ram _0, u _ ram _1 and the like. Inside a pair of brackets immediately after u _ ram is the connection relationship of the port and the external signal: wherein the clock port (clk), port name clkin, is connected to the external signal ram _ clk, and so on, the write enable port (wren), port name wr, is connected to the external signal cmd _ wen; a write data port (D) having a port name D _ in, to which an external signal cmd _ datain is connected; a read enable port (rden), with port name rd, which is connected to an external signal cmd _ ren; an address port (A) with a port name addr, which is connected to an external signal cmd _ addr; a read data port (Q), with a port name Q _ out, is connected to an external signal cmd _ dataout.

Fig. 3 shows a main flow of a method for reconfiguring a memory module in a digital integrated circuit design according to the present invention as follows:

step S1: in all RTL source files, all parameter parameters are searched and classified for storage, then parameter analysis is carried out, and analysis results are stored in a global parameter table, grouped _ fact.

Step S2: and searching the original memory module name old _ module _ name in all RTL source files to find a memory instantiated structure, then extracting required information, and storing the information to a corresponding position of the memdit to complete the initialization of the memdit.

Step S3: and querying a global parameter table, replacing sub-parameters of the memory instantiation parameter in the memory, calculating to obtain a parameter decimal representation, and updating the parameter in the memory.

Step S4: fixing the storage depth and the address bit width, leading the data port bit width into a memory compiling tool as a variable parameter, iterating until the memory generated by compiling meets the design time sequence requirement, and then storing the new memory name into the new _ module _ name of the memdit.

Step S5: and acquiring a port list of a memory module, establishing a matching relation between a new memory and an original memory port, and storing the matching relation to a port _ map of the memory.

Step S6: and generating an instantiated structure of the new memory, and storing the instantiated structure to the new _ rtl of the memdit.

Step S7: and replacing the original memory instantiated structure in the RTL file by using new _ RTL of the memdit, and outputting the updated RTL file.

In the technical solution, the memdit used in the steps S1 to S7 includes the following information:

inst _ id, which stores the primary key used to index the element in the memdit, is equal to "RTL filename/inst _ name", inst _ name being the memory instance name in the RTL source code.

The parameter stores the original memory instantiation parameters, and comprises a data port bit width data _ width, a storage depth and an address bit width addr _ width.

old _ module _ name, storing the original memory module name.

new _ module _ name, storing the new memory module name.

And the port _ connect _ signal stores the connection relation between the original memory port and the external signal, and is formed by a key value pair port _ connect sequentially corresponding to a port name port _ name and the external signal port _ signal.

port _ map, storing a mapping relation of the memory port, which includes an original memory port table old _ port _ list and a new memory port table new _ port _ list, where the two port table elements correspond in sequence, and the port includes: clock (clk), write enable (wren), write data (D), read enable (rden), address (a), read data (Q).

instance _ range, which stores the line range of the instantiated structure code of the original memory, includes an instantiated start line number inst _ start _ no and an instantiated end line number inst _ end _ no.

new _ rtl, storing new memory instantiation code, which comprises one or more of signal line definition statement, signal line connection statement, and memory instantiation statement.

Fig. 4 explains the memdit data structure used in fig. 3, as follows.

The memdit is essentially a hash table, and is generally implemented by a dit () dictionary type in a script language such as python. It contains a dictionary primary key (key), i.e., the memory instantiation index inst _ id. inst _ id ═ RTL filename/inst _ name, "inst _ name being the memory name in the RTL source code. The purpose of not using the inst _ name alone as the inst _ id is to prevent the inst _ id primary key from being duplicated, because the verilog hardware description language allows the same instantiation name to be used in different modules, and the instantiation names of the same module must be different, so that the modules can be distinguished by adding the RTL file name. One data element in memdit may then be selected in the form of memdit [ inst _ id ] (where brackets [ ] are referred to as the take member operators, which will be applied multiple times later). In addition to the primary key, the memdit structure includes other data elements:

original memory instantiation parameter (parameter). The method comprises the data port bit width data _ width, the storage depth and the address bit width addr _ width. The parameters are extracted from a parameter table of a memory instantiated structure and then are obtained through partial _ fact analysis calculation of a global parameter table, and are expressed in decimal. In order to facilitate the retrieval of the corresponding parameters, the instantiation parameter can also be designed into a dictionary type data structure, the key name can use data _ width, depth and addr _ width, and the key value uses decimal numbers obtained after parameter analysis and calculation.

The original memory module name (old _ module _ name). It is a string that is specified in advance. In a single IP (Internet protocol) sending packet, an RTL (remote terminal) source code generally adopts a unified sram behavior model, and all the names of the original memory modules are consistent and only the instantiation parameters are different. Therefore, this memory module name only needs to be specified once.

New memory module name (new _ module _ name). It is a string that is determined when a new memory is generated by the memory compilation tool. In order to improve the identification degree of the new memory module name and facilitate batch processing of other tools, a naming rule of a generation module is generally specified in a memory design tool, such as "memory name + storage depth + data width + process node".

The original memory port is connected to an external signal (port _ connect _ signal). It is a dictionary data structure, and stores the key value pair of port name _ name and port connection signal port _ signal. Since the port in the module is not repeatable, it can be used as a key name, and the signal name connected to this port in the RTL source code is retrieved directly from the dictionary through the original memory port.

memory port mapping relationship (port _ map). The method comprises an original port table old _ port _ list and a new port table new _ port _ list, wherein the two port table elements correspond in sequence. The port elements in the two port _ lists are divided into: clock clk, write enable wren, write data D, read enable rden, address A, read data Q. The port _ map uses a linked list to solve the mapping relation in a position order corresponding mode, because the port types between the new memory and the original memory are generally the same, and the port numbers are also consistent.

The original memory instantiates a code interval (instance _ range). It includes an instantiation start line number inst _ start _ no and an instantiation end line number inst _ end _ no. Because the instantiated structure in the hardware description language verilog begins with the module name, with a symbol "); "end". Then the starting line inst _ start _ no of all memories can be located by searching the line starting with old _ module _ name, and the first can be found down from the starting line "); ", i.e., find the instantiation end line inst _ end _ no.

The new memory instantiated code (new _ rtl). New _ RTL is verilog code used to directly replace the original memory instantiated structure in RTL source code. The new _ rtl is generated in step S6.

Fig. 5 explains step S1 of fig. 3 as follows.

Step S1-1: a parameter table is created, paired _ fact (storing parsed parameters), index _ fact (storing indirect parameters), and undefined _ fact (storing undefined parameters). The process proceeds to step S1-2.

Step S1-2: the first line is read from an RTL source file that has not been parameter parsed. The flow proceeds to step S1-3.

Step S1-3: is the code line match the parameter syntax? If so, the process proceeds to step S1-4, otherwise, the process proceeds to step S1-9.

Step S1-4: is the parameter value a numerical value? If so, the process proceeds to step S1-5, otherwise, the process proceeds to step S1-6.

Step S1-5: and converting the parameter value into a decimal system and storing the decimal system into the paired _ fact. The flow proceeds to step S1-9.

Step S1-6: is the parameter value contain an operator? If so, the process proceeds to step S1-7, otherwise, the process proceeds to step S1-8.

Step S1-7: the parameter value is stored in indelect _ dit. The flow proceeds to step S1-9.

Step S1-8: the parameter values are stored in the undefined _ dct, ready for substitution and calculation. The flow proceeds to step S1-9.

Step S1-9: is there a next line in the source file? If so, the process proceeds to step S1-10, otherwise, the process proceeds to step S1-11.

Step S1-10: the next row of the source file is read. The flow proceeds to step S1-3.

Step S1-11: is there still a file to be parsed? If so, the process proceeds to step S1-2, otherwise, the process proceeds to step S1-12.

Step S1-12: is indeect _ fact null? If yes, go to step S1-15, otherwise go to step S1-13

Step S1-13: and querying from the segmented _ fact to replace the value of the inderect _ fact parameter. The flow proceeds to step S1-14.

Step S1-14: the replaced parameter is moved from index _ fact to paired _ fact. The flow proceeds to step S1-15.

Step S1-15: is undefined _ fact null? If so, the process proceeds to step S1-18, otherwise, the process proceeds to step S1-16.

Step S1-16: and querying from the partial _ fact to replace the value of the undefined _ fact parameter. The flow proceeds to step S1-17.

Step S1-17: the replaced undefined _ fact parameter is calculated and then moved to the partially _ fact. The flow proceeds to step S1-12.

Step S1-18: and (5) all the memory parameter analysis is finished, and the analysis result is stored in the global parameter table partial _ fact.

The parameter tables divided _ fact, index _ fact, and undefined _ fact in the above step S1 are preferably implemented in dictionary type, which facilitates retrieval of parameter values directly by parameter names. indirect parameters are stored in index _ fact, specific parameter values are obtained directly by inquiring partial _ fact, and calculation is not needed; undefined parameters are stored in undefined _ fact, and need to be queried and replaced in partial _ fact, and then evaluated in computation. The parameters of index _ fact and undefined _ fact resolutions are finally merged into the partial _ fact for subsequent resolution of the memory instantiation parameters. Step S1 is similar to recursion, and is implemented with a recursive structure in preference.

Fig. 6 explains step S2 of fig. 3 as follows.

Step S2-1: a data structure memdit for memory instantiation is created. The process proceeds to step S2-2.

Step S2-2: the original memory module name old _ module _ name is set. The flow proceeds to step S2-3.

Step S2-3: the first line is read from the RTL source file from which the instantiation parameters were not extracted. The flow proceeds to step S2-4.

Step S2-4: is the code line begin with old _ module _ name? If so, the process proceeds to step S2-7, otherwise, the process proceeds to step S2-5.

Step S2-5: is there a next line for the source file? If so, the process proceeds to step S2-6, otherwise, the process proceeds to step S2-16.

Step S2-6: the next row is read. The flow proceeds to step S2-4.

Step S2-7: record the line number to the instantiated start line number inst _ start _ no. The flow proceeds to step S2-8.

Step S2-8: whether a line of code is true "); "end? If so, the process proceeds to step S2-10, otherwise, the process proceeds to step S2-9.

Step S2-9: the next row is read. The flow proceeds to step S2-8.

Step S2-10: recording the line number to the instantiation end line number inst _ end _ no, and saving the RTL code between inst _ start _ no and inst _ end _ no to the instantiation structure inst _ body. The flow proceeds to step S2-11.

Step S2-11: extracting a memory instantiation name inst _ name in inst _ body, and recording a memory instantiation index inst _ id as RTL file name/inst _ name. The flow proceeds to step S2-12.

Step S2-12: extracting the instantiation parameters in the inst _ body and saving the instantiation parameters in the memdit [ inst _ id ] [ parameter ]. The flow proceeds to step S2-13.

Step S2-13: and extracting all port names port _ name and connected external signals port _ signal in inst _ body. And adding the port _ name as a key name and the port _ signal as a key value into the memdirect [ inst _ id ] [ port _ connect _ signal ] one by one. The flow proceeds to step S2-14.

Step S2-14: saving inst _ start _ no and inst _ end _ no to memrect [ inst _ id ] [ instance _ range ]. The flow proceeds to step S2-15.

Step S2-15: the line number switches to inst _ end _ no. The flow proceeds to step S2-16.

Step S2-16: is all the RTL source files fetched? If so, the process proceeds to step S2-17, otherwise, the process proceeds to step S2-3.

Step S2-17: the initialization of memdit ends.

In the old _ module _ name in the above step S2, the original RTL code generally has only one name, which is called parameterized memory module, such as dynamic _ sram in fig. 11, and this name is pre-known. Therefore, in most cases, the old _ module _ name needs to be set only once. If there are multiple parameterized memory modules in the original RTL code, each parameterized memory module needs to be substituted into step S2.

In the above step S2, the process of extracting the instantiation name, the instantiation parameter, the port and the external signal from the inst _ body may be implemented by using a regular expression.

Fig. 7 explains step S3 of fig. 3 as follows.

Step S3-1: memdict starts traversing from the first primary key (inst _ id). The process proceeds to step S3-2.

Step S3-2: the data member memdit [ inst _ id ] is selected. The flow proceeds to step S3-3.

Step S3-3: acquiring a memory instantiation parameter memory [ inst _ id ] [ parameter ]. The flow proceeds to step S3-4.

Step S3-4: and taking out memory instantiated parameters including data port bit width data _ width, storage depth and address bit width addr _ width. The flow proceeds to step S3-5.

Step S3-5: and calling a figure (x), wherein x sequentially takes data _ width, depth and addr _ width. Step S3-8 is entered until step S3-12 is completed, and step S3-6 is entered.

Step S3-6: is memdit traversed? If so, the process proceeds to step S3-14, otherwise, the process proceeds to step S3-7.

Step S3-7: the next inst _ id is selected. The process proceeds to step S3-2.

Step S3-8: enter method figure (x). The flow proceeds to step S3-9.

Step S3-9: the operator op in x is extracted. The flow proceeds to step S3-10.

Step S3-10: using op as a separator, the subparameter is separated from x. The flow proceeds to step S3-11.

Step S3-11: the partial _ dit is queried to replace the subparameter with a decimal representation. The flow proceeds to step S3-12.

Step S3-12: and obtaining a decimal result of x through operation. The flow proceeds to step S3-13.

Step S3-13: and updating the result to an instantiation parameter memdit [ inst _ id ] [ parameter ]. The flow proceeds to step S3-6.

Step S3-14: and finishing the calculation and updating of the memory instantiated parameter in the memdit.

In step S3-9, the operator op includes basic algebraic operations "add, subtract, multiply and divide" and "base 2 logarithmic operations".

Fig. 8 explains step S4 of fig. 3 as follows.

Step S4-1: memdict starts traversing from the first primary key (inst _ id). The process proceeds to step S4-2.

Step S4-2: the data member memdit [ inst _ id ] [ parameter ] is selected. The flow proceeds to step S4-3.

Step S4-3: and taking out memory instantiated parameters including data port bit width data _ width, storage depth and address bit width addr _ width. The flow proceeds to step S4-4.

Step S4-4: the width division coefficient ratio is set to 1. The flow proceeds to step S4-5.

Step S4-5: new memory data port bit width

The result of the division is rounded up. The flow proceeds to step S4-6.

Step S4-6: and (4) importing the new _ data _ width, depth and addr _ width into a memory compiling tool, and executing generation of a new memory library file. The flow proceeds to step S4-7.

Step S4-7: is the new memory meet timing requirements? If yes, the process goes to step S4-9, otherwise, the process goes to step S4-8.

Step S4-8: ratio × 2. The flow proceeds to step S4-5.

Step S4-9: and saving the new memory name generated by compiling to the memdict [ inst _ id ] [ new _ module _ name ]. The flow proceeds to step S4-10.

Step S4-10: is memdit traversed? If so, the process proceeds to step S4-12, otherwise, the process proceeds to step S4-11.

Step S4-11: the next inst _ id is selected. The process proceeds to step S4-2.

Step S4-12: and finishing the generation of the new memory library file.

In the above step S4-6, the memory compilation tool is generally referred to as a memory compiler tool. The library will provide this tool for generating memory library files of different sizes and at different process angles. These library files are still of the RTL type and can be implemented with other source files under the RTL directory to implement the front-end logic design. When the memory library file is generated, along with the generation of the time sequence report corresponding to each memory, whether the new memory meets the designed time sequence requirement or not can be confirmed by inquiring the data of the report.

Fig. 9 explains step S5 of fig. 3 as follows.

Step S5-1: memdict starts traversing from the first primary key (inst _ id). The process proceeds to step S5-2.

Step S5-2: and acquiring a new memory module port list new _ port _ list. The flow proceeds to step S5-3.

Step S5-3: and acquiring an original memory module port list old _ port _ list. The flow proceeds to step S5-4.

Step S5-4: the matching clock port, new _ port _ list [ clk ], corresponds to old _ port _ list [ clk ]. The flow proceeds to step S5-5.

Step S5-5: matching write enabled ports, new _ port _ list [ wren ] corresponds to old _ port _ list [ wren ]. The flow proceeds to step S5-6.

Step S5-6: the new _ port _ list [ D ] corresponds to old _ port _ list [ D ]. The flow proceeds to step S5-7.

Step S5-7: matching read enabled ports, new _ port _ list [ rden ] corresponds to old _ port _ list [ rden ]. The flow proceeds to step S5-8.

Step S5-8: the new _ port _ list [ Q ] corresponds to old _ port _ list [ Q ] for the matching read data port. The flow proceeds to step S5-9.

Step S5-9: the matching address port, new _ port _ list [ A ], corresponds to old _ port _ list [ A ]. The flow proceeds to step S5-10.

Step S5-10: the correspondence between new _ port _ list and old _ port _ list is stored in memdit [ inst _ id ] [ port _ map ]. The flow proceeds to step S5-11.

Step S5-11: is memdit traversed? If so, the process proceeds to step S5-13, otherwise, the process proceeds to step S5-12.

Step S5-12: the next inst _ id is selected. The process proceeds to step S5-2.

Step S5-13: and the memory port matching is finished.

In the above steps S5-2 and S5-3, the process of obtaining the memory module port list may be directly extracted from the memory instantiated structural body by using a regular expression. A memory instantiation structure, for an original memory, locating in a module statement block in an RTL source file defining the memory, and locating a file by using a memdit [ inst _ id ] [ old _ module _ name ]; for a new memory, the memory is located in a module statement block of a newly generated memory library file and is located by using a memdit [ inst _ id ] [ new _ module _ name ]. Here, the memory source file and the memory library file have no essential difference and are both verilog syntax descriptions.

Because the port occurrence sequence of the original memory and the new memory may be inconsistent in the instantiation structure, the port correspondence relationship needs to be reestablished. The method can be realized by adjusting the positions of the ports in the two port lists, namely the new _ port _ list and the old _ port _ list, and the ports are sequentially corresponded from front to back in the list data structure; additional dictionary data structures may also be used to store the mapping of ports. In this embodiment, the former is used to perform the correspondence of the port relationship, so that the memdit [ inst _ id ] [ port _ map ] only needs to directly store the adjusted lists new _ port _ list and old _ port _ list, and the port relationship actually completes the correspondence through the order of the elements in the lists.

Fig. 10 explains step S6 of fig. 3 as follows.

Step S6-1: memdict starts traversing from the first primary key (inst _ id). The flow proceeds to step S6-2.

Step S6-2: calculating the number of instantiations after the memory replacement according to the new memory and the original memory data port bit width new _ data _ width and data _ width

(division rounded up). The flow proceeds to step S6-3.

Step S6-3: a memory instantiation name inst _ name is acquired, and an initial instantiation index inst _ no is set to 0. The flow proceeds to step S6-4.

Step S6-4: a new instantiation name new _ inst _ name is constructed, new _ inst _ name is inst _ name + inst _ no (spliced by a string). The flow proceeds to step S6-5.

Step S6-5: and acquiring a memory port list new _ port _ list and old _ port _ list from the memory [ inst _ id ] [ port _ map ], and acquiring a connection relation port _ connect from the memory [ inst _ id ] [ port _ connect _ signal ]. The flow proceeds to step S6-6.

Step S6-6: is inst _ no equal to (inst _ times-1)? If so, the process proceeds to step S6-8, otherwise, the process proceeds to step S6-7.

Step S6-7: right _ index ═ new _ data _ width × inst _ no, left _ index ═ right _ index + new _ data _ width-1. The flow proceeds to step S6-10.

Step S6-8: right _ index is new _ data _ width × inst _ no, and left _ index is data _ width-1. The flow proceeds to step S6-9.

Step S6-9: "wire [ new _ data _ width × inst _ times-1: right _ index ] port _ connect [ old _ port _ list [ Q ] ] _; assign _ port _ connect [ old _ port _ list [ Q ] ] [ left _ index: right _ index ] -is appended to memdit [ inst _ id ] [ new _ rtl ]. The flow proceeds to step S6-10.

Step S6-10: "new _ module _ name new _ inst _ name (" appended to memdit [ inst _ id ] [ new _ rtl ]. proceed to step S6-11.

Step S6-11: ". new _ port _ list [ clk ] (port _ connect [ old _ port _ list [ clk ] ]),. new _ port _ list [ wren ] (port _ connect [ old _ port _ list [ wren ] ]),. new _ port _ list [ rden ] (port _ connect [ old _ port _ list [ rden ] ]),. new _ port _ list [ A ] (port _ connect [ old _ port _ list [ A ] ])," appended to media [ insert _ id ] [ new _ rtl ].

Step S6-12: is inst _ no equal to (inst _ times-1)? If yes, go to step S6-15, otherwise go to step S6-13.

Step S6-13: ". new _ port _ list [ D ] (port _ connect [ old _ port _ list [ D ] ] [ right _ index ]),. new _ port _ list [ Q ] (port _ connect [ old _ port _ list [ Q ] ] [ right _ index ])); "appended to memdit [ inst _ id ] [ new _ rtl ]. The flow proceeds to step S6-14.

Step S6-14: instantiation index increment: inst _ no ═ inst _ no + 1. The flow proceeds to step S6-4.

Step S6-15: calculating the number of 0 to be filled in the high order of the write data port D: the pads is new _ data _ width × inst _ times-data _ width. The flow proceeds to step S6-16.

Step S6-16: ". new _ port _ list [ D ] ({ { pads {1' b0} }, port _ connect [ old _ port _ list [ D ] ] [ left _ index: right _ index ] })," appended to media [ inst _ id ] [ new _ rtl ]. The flow proceeds to step S6-17.

Step S6-17: ". new _ port _ list [ Q ] (port _ connect [ old _ port _ list [ Q ] ])); "appended to memdit [ inst _ id ] [ new _ rtl ]. The flow proceeds to step S6-18.

Step S6-18: is memdit traversed? If so, the process proceeds to step S6-20, otherwise, the process proceeds to step S6-19.

Step S6-19: the next inst _ id is selected. The process proceeds to step S6-2.

Step S6-20: and the new _ rtl generation in the memdit is finished.

In the step S6-2, because the bit width of the data port of the new memory may be smaller than that of the original memory, multiple new memories need to be spliced by the data bits to realize the function of the original memory. After splicing, a situation that some data bits cannot be corresponded may occur on the upper data bits, and in this embodiment, the number of data ports D filled with 0 needs to be calculated by filling 0 in the upper bits, see step S6-15. After splicing, the total number of bits of Q may also be expanded, so that it is necessary to redefine the wire-type external signal connected to Q, the newly defined wire signal is implemented by adding an underline _ "to the name of the external signal at the original Q terminal, and the signal at the Q terminal needs to be intercepted and then connected to the original signal, in step S6-9. In addition, because the name of the instantiation needs to be redefined due to the concatenation of the memory, the instantiation name is distinguished by adding (concatenating) the instantiation index after the original instantiation name, see step S6-3 and step S6-14. When the instantiation index inst _ no reaches the instantiation time inst _ times-1 (see step S6-12), it indicates that the concatenation of the memory is completed, and the next instantiation structure can be processed.

In step S6-5, the port _ connect is preferably implemented by a dictionary-type data structure, so that the external signal (key value) corresponding to the connection can be directly retrieved through each port (key name) of the original port list old _ port _ list, which is convenient for connection in the instantiation structure of the new memory.

Fig. 11 explains step S7 of fig. 3 as follows.

Step S7-1: and entering an RTL directory, and opening a first RTL source file. The process proceeds to step S7-2.

Step S7-2: and traversing the memdit main key inst _ id, finding out the RTL file name which is the same as the name of the current RTL source file, and storing the RTL file name as a linked list inst _ id _ list. The flow proceeds to step S7-3.

Step S7-3: using memdit [ inst _ id ] [ instance _ range ] [ inst _ start _ no ] as a sorting key, sorting inst _ ids in the inst _ id _ list in a descending order, and sorting the inst _ id _ list into sorted _ inst _ id _ list. The flow proceeds to step S7-4.

Step S7-4: and storing the current RTL source file code into a linked list RTL _ list line by line. The flow proceeds to step S7-5.

Step S7-5: acquiring the top and bottom of the new memory instantiated code replacement position: top _ row ═ media [ inst _ id ] [ instance _ range ] [ inst _ start _ no ] bot _ row ═ media [ inst _ id ] [ instance _ range ] [ inst _ end _ no ]. The flow proceeds to step S7-6.

Step S7-6: and sequentially taking out the inst _ id from the sorted _ inst _ id _ list, and replacing a code between top _ row and bot _ row in the rtl _ list by using a new memory instantiated code memdit [ inst _ id ] [ new _ rtl ]. The flow proceeds to step S7-7.

Step S7-7: and writing the updated RTL _ list into a new RTL source file. The flow proceeds to step S7-8.

Step S7-8: is the RTL source file traversed? If so, the process proceeds to step S7-10, otherwise, the process proceeds to step S7-9.

Step S7-9: the next RTL source file is opened. The process proceeds to step S7-2.

Step S7-10: and finishing the reconstruction of the storage modules of all RTL source files.

In the step S7-2, since the memory instantiation index adopted in the embodiment already includes the RTL filename, all inst _ ids belonging to the RTL file can be filtered out through the RTL filename, that is, all code ranges to be replaced and specific instantiation codes new _ RTL in the RTL file can be found, so that it is not necessary to traverse the memdit for each RTL file.

In the step S7-3, the memory instantiated codes with large line number are replaced in the RTL file by using the initial line number of the instantiated structure for descending order, so that the replacement of the memory instantiated codes with small line number is not affected. If the sequence is not carried out, the line number of the instantiated code can be changed after each replacement, and the position of the next replacement needs to be recalculated, so that unnecessary calculation work is brought. This also reduces the possibility of code update errors.

Fig. 12 is a block diagram of a reconstruction system of a memory module according to an embodiment of the present invention, as shown in fig. 12, including:

an example parameter parsing unit 1210, configured to search all parameter parameters in all RTL source files, parse the searched parameter parameters, and store the parsed parameter parameters in a global parameter table; the parameter is a global parameter;

the hash table initialization unit 1220 is configured to search all RTL source files for names of original storage modules, find an instantiated structure of an original storage module based on the names of the original storage modules, extract information of the instantiated structure of the original storage module, store the extracted information in a custom hash table, and complete initialization of the hash table; the hash table is used for storing the information of the original storage module, the information of the new storage module and the matching relationship information between the original storage module and the new storage module;

an instantiated parameter updating unit 1230, configured to update the instantiated parameters of the original storage module in the hash table to decimal resolved parameters based on the global parameter table; the instantiation parameters comprise: the data end bit width, the storage depth and the address bit width;

the new storage module design unit 1240 is used for fixing two instantiated parameters, namely the storage depth and the address bit width, of the new storage module to corresponding preset values, designing a data port bit width value of the new storage module through an iterative method until the new storage module obtained by design meets the time sequence design requirement, and taking the data port bit width value at the moment as a data port bit width design value of the new storage module; keeping the name of the new storage module in a hash table;

a port relation determining unit 1250, configured to obtain port lists of the original storage module and the new storage module, respectively, establish a matching relation between ports of the original storage module and the new storage module, and store the matching relation in a hash table;

a new instantiation structure generation unit 1260, configured to determine instantiation times of the new storage module after replacing the original storage module with the new storage module according to the data port bit width value of the original storage module and the data port bit width design value of the new storage module, so as to generate an instantiation structure of the new storage module, and store the instantiation structure of the new storage module in the hash table;

the storage module reconfiguration unit 1270 is configured to replace the instantiated structure of the original storage module in the RTL source file with the instantiated structure of the new storage module in the hash table, output the updated RTL source file, and complete reconfiguration of the original storage module.

Specifically, the detailed function implementation of each unit in fig. 12 can refer to the description in the foregoing method embodiment, and is not described herein again.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A method for reconfiguring a memory module in a digital integrated circuit design, comprising the steps of:

determining the instantiation times of the new storage module after replacing the original storage module according to the data port bit width value of the original storage module and the data port bit width design value of the new storage module, generating the instantiation structure of the new storage module according to the instantiation times, and storing the instantiation structure of the new storage module into a hash table;

2. The reconstruction method according to claim 1, wherein the step of designing the data port bit width value of the new memory module by the iterative method until the new memory module obtained by the design meets the timing design requirement includes the following steps:

3. A reconstruction method according to claim 1 or 2, wherein the data structure of the customized hash table comprises:

4. The reconstruction method according to claim 3, wherein the determining the number of instantiations of the new memory module after replacing the original memory module according to the data port bit width value of the original memory module and the data port bit width design value of the new memory module to generate the instantiated structure of the new memory module specifically comprises the following steps:

5. The reconstruction method according to claim 4, wherein the parsing and storing the searched parameter into the global parameter table comprises the following steps:

6. The reconstruction method according to claim 5, wherein the updating the instantiated parameters of the original storage module in the hash table to the decimal resolved parameters based on the global parameter table comprises the following steps:

7. The reconstruction method according to claim 6, wherein the replacing the instantiation structure of the original storage module in the RTL source file with the instantiation structure of the new storage module in the hash table, and outputting the updated RTL source file specifically comprises the following steps:

filtering all new instantiated structure linked lists belonging to the RTL source file from the hash table by using the name of the RTL source file;

and sequentially taking out each instantiated structural body of the sorted linked list, and replacing codes between the instantiated starting line and the instantiated ending line of the original storage module in the RTL source file.

8. A system for reconfiguring a memory module in a digital integrated circuit design, comprising

the system comprises a Hash table initialization unit, a storage unit and a processing unit, wherein the Hash table initialization unit is used for searching the names of original storage modules in all RTL source files, finding the instantiation structure of the original storage modules based on the names of the original storage modules, extracting the information of the instantiation structure of the original storage modules, storing the extracted information into a self-defined Hash table and completing initialization of the Hash table; the hash table is used for storing the information of the original storage module, the information of the new storage module and the matching relationship information between the original storage module and the new storage module;

9. The reconstruction system according to claim 8, wherein the new memory module designing unit designs the data port bit width value of the new memory module by an iterative method until the new memory module obtained by the design meets the timing design requirement, and specifically includes the following steps:

10. The reconstruction system according to claim 8 or 9, wherein the new instantiation structure generating unit determines the number of instantiations of the new memory module after replacing the original memory module according to the data port bit width value of the original memory module and the data port bit width design value of the new memory module, so as to generate the instantiation structure of the new memory module, specifically comprising the following steps: dividing the data port bit width value of the original storage module by the data port bit width design value, and rounding up to obtain the number of instantiations; the instantiation name of the new storage module is formed by splicing the instantiation name and the instantiation index of the original storage module, 1 is added to the instantiation index of the new storage module once, until the instantiation index value is the instantiation frequency and is reduced by 1, and the generation of the new storage module instantiation structure is completed; the generated instantiation index of a new instantiation structure is returned to 0; signals of a clock port, a write enable port, a read enable port and an address port in the original storage module instantiation structure are directly connected to the new instantiation structure body without bit division; except for the last instantiation of the new storage module, signals of a write data port and a read data port need to be divided by using an instantiation index and then are connected to a new instantiation structure; when the new storage module is instantiated for the last time, for a write data port, in addition to signal division by using an instantiation index, high-order bit filling 0 operation is required to be carried out on the high-order bit according to the characteristic of bit width matching, and the number of 0 to be filled in the high-order bit is determined by multiplying the design value of the bit width of the data port by the number of instantiations and subtracting the bit width value of the data port of the original storage module; for the read data port, a signal which is matched with the bit width of the read data port of the new memory module needs to be additionally defined to be connected to the new instantiated structural body, and the signal is connected to the original read data signal after being shortened according to the bit width.