CN114448402A - High-end power control circuit based on digital logic and anti-interference method - Google Patents

High-end power control circuit based on digital logic and anti-interference method Download PDF

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Publication number
CN114448402A
CN114448402A CN202210092022.XA CN202210092022A CN114448402A CN 114448402 A CN114448402 A CN 114448402A CN 202210092022 A CN202210092022 A CN 202210092022A CN 114448402 A CN114448402 A CN 114448402A
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trigger module
output
digital trigger
digital
circuit
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Inventor
郭俊杰
田瑶
常昌远
徐申
叶佳玲
孙祎轩
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Suzhou Juren Semiconductor Co ltd
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Suzhou Juren Semiconductor Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Abstract

The invention discloses a high-end power control circuit based on digital logic and an anti-interference method. The high-side power control circuit comprises a digital trigger module, the output end of the digital trigger module is simultaneously connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the control end of the digital trigger module is connected with the output end of the output drive circuit. At the moment, the digital trigger module takes the output signal of the output driving circuit as a clock control signal, so that the digital trigger module is triggered in the time period when the output signal is in the rising edge, and the output end of the digital trigger module is always in the low level state. The anti-interference method is carried out on the basis of the high-end power control circuit, so that the drain electrode potential of the first LDMOS transistor is pulled high when the output signal is in a rising edge stage, and the noise pulse width is reduced. The high-end power control circuit has the advantages of simple structure and small chip size, and noise interference is effectively eliminated by the high-end power control circuit and the anti-interference method.

Description

High-end power control circuit based on digital logic and anti-interference method
Technical Field
The invention relates to the technical field of electronics and microelectronics, in particular to a high-end power control circuit based on digital logic and an anti-interference method.
Background
Power integrated circuits are an important product of the integration of electronic and microelectronic technologies. The power integrated circuit comprises a main chip, an interface circuit, a power control circuit, a protection circuit, a detection circuit, a high-voltage power device and the like, and can realize information acquisition, amplification, processing, loading and the like. And because the device has the advantages of strong reliability, small size and the like, the device is widely applied to the fields of spaceflight, new energy, smart home and the like.
The power control circuit is the core component of the power integrated circuit, and the high-end power control circuit is the core component of the power control circuit. The high-end power control circuit comprises a pulse generating circuit, a high-end level shifting circuit, a filter circuit, an RS trigger and an output driving circuit which are sequentially connected, and plays an important role in realizing final information output.
The high-end level shift circuit is mainly formed by connecting an LDMOS (laterally diffused metal oxide semiconductor) tube and a resistor in series, but is influenced by the self preparation process of the LDMOS tube, and a parasitic capacitor exists at the drain electrode of the LDMOS. When the floating reference of the circuit changes, noise interference is generated, the noise forms a path to the ground through the parasitic capacitance, and if the noise is too large, a large voltage drop is generated on a load resistor. At this time, the latter circuit may mistake the noise as a normal signal and transmit the signal downward, thereby causing the power integrated circuit to latch up, and even causing the entire power integrated circuit to burn out.
Disclosure of Invention
The invention aims to provide a high-end power control circuit based on digital logic, which has a simple structure and a small integral volume, can effectively eliminate noise interference and ensure the normal operation of the whole power integrated circuit.
The invention also provides an anti-interference method of the high-end power control circuit based on digital logic, which is carried out based on the high-end power control circuit, thereby effectively eliminating noise interference in the working process of the power integrated circuit.
In order to achieve the above purpose, the invention provides the following technical scheme:
a high-end power control circuit based on digital logic comprises a pulse generating circuit, a high-end level shift circuit, a filter circuit, an RS trigger and an output drive circuit which are matched with each other, wherein the high-end level shift circuit comprises a digital trigger module, and a first LDMOS (laterally diffused metal oxide semiconductor) tube, a first PMOS (P-channel metal oxide semiconductor) tube, a first voltage stabilizing diode, a first resistor, a second LDMOS tube, a second PMOS tube, a second voltage stabilizing diode and a second resistor which are matched with the digital trigger module;
the filter circuit, the RS trigger and the output drive circuit are sequentially connected in series, power ends of the filter circuit, the RS trigger and the output drive circuit are connected to a floating power supply at the same time, and grounding ends of the filter circuit, the RS trigger and the output drive circuit are connected to a floating reference at the same time;
the source electrode of the first LDMOS transistor is grounded, the grid electrode of the first LDMOS transistor is connected with the first output end of the pulse generation circuit, and the drain electrode of the first LDMOS transistor is simultaneously connected with the drain electrode of the first PMOS transistor, the first resistor, the anode of the first voltage stabilizing diode and the first input end of the digital trigger module and is connected to the first input end of the filter circuit; the source electrode of the first PMOS tube, the spare end of the first resistor and the cathode of the first voltage stabilizing diode are connected and connected to the floating power supply;
the source electrode of the second LDMOS transistor is grounded, the grid electrode of the second LDMOS transistor is connected with the second output end of the pulse generation circuit, the drain electrode of the second LDMOS transistor is simultaneously connected with the drain electrode of the second PMOS transistor, the second resistor, the anode of the second voltage regulator diode and the second input end of the digital trigger module and is connected to the second input end of the filter circuit, and the source electrode of the second PMOS transistor, the spare end of the second resistor and the cathode of the second voltage regulator diode are connected and connected to the floating power supply;
the output end of the digital trigger module is simultaneously connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the control end of the digital trigger module is connected with the output end of the output drive circuit; at this time, the digital trigger module takes the output signal of the output driving circuit as a clock control signal, so that the digital trigger module is triggered in a time period when the output signal is in a rising edge, and further the output end of the digital trigger module is always in a low level state.
And further, the digital trigger circuit comprises an even-level inverter, wherein the anode of the even-level inverter is connected with the output end of the output driving circuit, and the cathode of the even-level inverter is connected with the control end of the digital trigger module.
Furthermore, the digital trigger module comprises an exclusive or gate and a D trigger, and an output end of the exclusive or gate is connected with a D end of the D trigger; at this time, the first input end of the digital trigger module is the first input end of the xor gate, the second input end of the digital trigger module is the second input end of the xor gate, the output end of the digital trigger module is the Q end of the D trigger, and the control end of the digital trigger module is the CLK end of the D trigger.
Furthermore, the digital trigger module comprises an and gate, a D trigger and a phase inverter, wherein the output end of the and gate is connected with the D end of the D trigger, the positive electrode of the phase inverter is connected with the Q end of the D trigger, and the negative electrode of the phase inverter is connected with the gate of the second PMOS transistor; at this time, the first input end of the digital trigger module is the first input end of the and gate, the second input end of the digital trigger module is the second input end of the and gate, the output end of the digital trigger module is the Q end of the D flip-flop or the negative electrode of the phase inverter, and the control end of the digital trigger module is the CLK end of the D flip-flop.
An anti-jamming method for a high-side power control circuit based on digital logic, performed by the high-side power control circuit, comprising:
load sudden changes to make the floating reference potential transient, thereby generating a noise signal; the drain electrode of the first LDMOS transistor and the drain electrode of the second LDMOS transistor are at low level at the same time, and the first input end and the second input end of the digital trigger module are at low level at the same time;
the output signal of the output driving circuit enters a rising edge stage to trigger the digital trigger module, so that the output end of the digital trigger module keeps low level output;
the low level of the output end of the digital trigger module controls the first PMOS tube to be opened, so that the potential of the drain electrode of the first LDMOS tube is pulled high to reduce the pulse width of a noise signal, and a narrow pulse noise signal is formed;
the filter circuit filters the narrow pulse noise signal and reserves a working pulse signal.
Further, the method comprises the following steps:
when the rising edge stage of the output signal of the output driving circuit is cut off, the digital trigger module is in an un-triggered state, and the high-end power control circuit enters normal operation.
Furthermore, when the digital trigger module comprises an exclusive-or gate and a D flip-flop,
when the low level of the output end of the digital trigger module controls the first PMOS tube to be opened, the second PMOS tube is also opened, and the drain electrode potential of the second LDMOS tube is also pulled high at the same time.
Furthermore, when the digital trigger module comprises an AND gate, a D flip-flop and an inverter,
when the low level of the output end of the digital trigger module controls the first PMOS tube to be opened, the second PMOS tube is closed, and the drain electrode potential of the second LDMOS tube is still at the low level.
Has the advantages that:
according to the technical scheme, the invention provides the high-end power control circuit based on the digital logic. The noise signal is mainly generated by the following conditions: when other high-end power tubes of the other phases in the power integrated circuit are turned on, if the turn-off speed of the low-end power tube of the current phase is higher, the energy on the load inductor is not completely discharged. At this time, the current on the load inductor will freewheel through the freewheeling zener diode connected in parallel with the high-side power transistor, and the voltage of the floating reference will rise rapidly. Because the on-state speed of the freewheeling voltage-stabilizing diode is very high, the generated noise is also large, and the noise finally generates large displacement current through the parasitic capacitance of the drain electrode of the LDMOS transistor, and the displacement current can generate voltage drop on a load resistor, so that a rear-stage circuit mistakenly considers the displacement current as a normal working signal and influences the normal work of the whole power integrated circuit.
In order to solve the above problems, the present invention adds a digital trigger module to the high-side level shift circuit. The output end of the digital trigger module is simultaneously connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the control end of the digital trigger module is connected with the output end of the output drive circuit; at this time, the digital trigger module takes the output signal of the output driving circuit as a clock control signal. Therefore, when the circuit works normally, the digital trigger module cannot influence the normal working state of the whole circuit. And when a noise signal is generated, the digital trigger module is triggered in the time period when the output signal is at the rising edge, so that the output end of the digital trigger module is at a low level. The low level will pull up the potential of the drain of the first LDMOS transistor, so that the circuit is restored to a normal working state, thereby eliminating noise interference.
Therefore, the high-end power control circuit which takes the output signal fed back to the preceding stage circuit as the clock control signal is designed, the structure is simple, and the chip volume is small; the noise interference in the working process of the existing high-end power control circuit is more effectively eliminated.
The invention also provides an anti-interference method of the high-end power control circuit based on the digital logic. The anti-interference method is realized based on the high-end power control circuit, the drain electrode potential of the first LDMOS transistor is pulled high when the output signal is in the rising edge stage, so that the pulse width of noise is reduced, and the narrow pulse noise signal in the normal working signal can be well eliminated by the filter circuit. Therefore, the anti-interference method not only can effectively eliminate the noise interference in the working process of the high-end power control circuit, but also has the advantage of simpler control process.
It should be understood that all combinations of the foregoing concepts and additional concepts described in greater detail below can be considered as part of the inventive subject matter of this disclosure unless such concepts are mutually inconsistent.
The foregoing and other aspects, embodiments and features of the present teachings can be more fully understood from the following description taken in conjunction with the accompanying drawings. Additional aspects of the present invention, such as features and/or advantages of exemplary embodiments, will be apparent from the description which follows, or may be learned by practice of specific embodiments in accordance with the teachings of the present invention.
Drawings
The drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures may be represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. Embodiments of various aspects of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:
fig. 1 is a schematic diagram of an embodiment of a high-side power control circuit according to the present invention;
fig. 2 is a schematic diagram of another embodiment of a high-side power control circuit according to the present invention;
FIG. 3 is a waveform diagram illustrating the high-side power control circuit shown in FIGS. 1 and 2 during normal operation;
FIG. 4 is a waveform diagram illustrating the state of the high-side power control circuit shown in FIG. 1 in the presence of noise;
fig. 5 is a waveform diagram illustrating a state of the high-side power control circuit shown in fig. 2 when noise occurs.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.
The use of "first," "second," and similar terms in the description and claims of the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. Similarly, the singular forms "a," "an," or "the" do not denote a limitation of quantity, but rather denote the presence of at least one, unless the context clearly dictates otherwise. The terms "comprises," "comprising," or the like, mean that the elements or items listed before "comprises" or "comprising" encompass the features, integers, steps, operations, elements, and/or components listed after "comprising" or "comprising," and do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. "upper", "lower", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationships may also change accordingly.
The invention provides a high-side power control circuit based on digital logic, wherein a high-side level shift circuit in the high-side power control circuit comprises a digital trigger module; the output end of the digital trigger module is connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube at the same time, and the control end of the digital trigger module is connected with the output end of the output drive circuit. At this time, the digital trigger module takes the output signal of the output drive circuit as a clock control signal, so that the digital trigger module is triggered in a rising edge time period of the output signal, and the output end of the digital trigger module is always in a low level state. Therefore, the noise interference can be effectively eliminated while the advantages of simple circuit structure and smaller chip volume are achieved.
The invention also provides an anti-interference method of the high-end power control circuit based on the digital logic, which is carried out based on the high-end power control circuit, so that the drain electrode potential of the first LDMOS transistor is pulled high when the output signal is in a rising edge stage, the pulse width of noise is reduced, and the noise interference in the working process of the high-end power control circuit is effectively eliminated.
The digital logic based high-side power control circuit disclosed in the present invention will be further described in detail with reference to the embodiments shown in the drawings.
As shown in fig. 1-2, the high-side power control circuit includes a pulse generating circuit, a high-side level shifting circuit, a filter circuit, an RS flip-flop, and an output driver circuit, which are matched with each other. The pulse generating circuit is used for forming two paths of low-voltage narrow pulse working signals; the high-end level shift circuit is used for converting the two low-voltage narrow pulse working signals into two high-voltage narrow pulse working signals; the filter circuit is used for filtering the two paths of high-voltage narrow-pulse working signals to remove noise signals in the two paths of high-voltage narrow-pulse working signals; the RS trigger is used for restoring the high-voltage narrow-pulse working signal into a high-voltage wide-pulse working signal; the output driving circuit is used for improving the driving capability of the high-voltage wide-pulse working signal so as to control the high-end power device.
The high-end level shift circuit comprises a digital trigger module, a first LDMOS transistor LDOMS1, a first PMOS transistor MP1, a first voltage-stabilizing diode VD1, a first resistor R1, a second LDMOS transistor LDMOS2, a second PMOS transistor MP2, a second voltage-stabilizing diode VD2 and a second resistor R2, wherein the first LDMOS transistor LDOMS1, the first PMOS transistor MP1, the first voltage-stabilizing diode VD1, the first resistor R1 and the second LDMOS transistor LDMOS2 are matched with the digital trigger module.
The filter circuit, the RS trigger and the output drive circuit are sequentially connected in series, and power ends of the filter circuit, the RS trigger and the output drive circuit are connected to a floating power supply V simultaneouslyBTheir ground terminals are connected to the floating reference V at the same timeS。
The source electrode of the first LDMOS transistor LDOMS1 is grounded, the grid electrode of the first LDMOS transistor LDOMS1 is connected with the first output end of the pulse generation circuit, and the drain electrode of the first LDMOS transistor LDOMS is simultaneously connected with the drain electrode of the first PMOS transistor MP1, the first resistor R1, the anode of the first voltage-stabilizing diode VD1 and the first input end of the digital trigger module and is connected to the first input end of the filter circuit; the source electrode of the first PMOS tube MP1, the spare end of the first resistor R1 and the cathode of the first voltage-stabilizing diode VD1 are connected and connected to a floating power supplyVB。
The source electrode of the second LDMOS2 is grounded, the grid electrode of the second LDMOS2 is connected with the second output end of the pulse generation circuit, the drain electrode of the second LDMOS is connected with the drain electrode of the second PMOS tube MP2, the anode of the second resistor R2 and the anode of the second voltage-stabilizing diode VD2 and the second input end of the digital trigger module at the same time, and is connected with the second input end of the filter circuit, the source electrode of the second PMOS tube MP2, the spare end of the second resistor R2 and the cathode of the second voltage-stabilizing diode VD2 are connected and are connected to the floating power supply VB。
The output end of the digital trigger module is simultaneously connected with the grid electrode of the first PMOS tube MP1 and the grid electrode of the second PMOS tube MP2, and the control end of the digital trigger module is connected with the output end of the output drive circuit; at this time, the digital trigger module takes the output signal HO of the output driving circuit as a clock control signal, so that the digital trigger module is triggered when the output signal HO is in a rising edge time period, and further the output end of the digital trigger module is always in a low level state.
Studies have shown that noise signals are mainly generated by two situations: one is that the low-end power tube is in the off state, the high-end power tube is suddenly turned on, and the floating reference V isSThe potential of (2) rises rapidly, and noise is generated. However, the noise at this time is mainly related to the switching speed of the high-side power tube, and since the switching speed of the high-side power tube in the system is generally in the order of microseconds, the generated noise is not very serious when the bus voltage of the half-bridge system does not exceed 600V. Another situation is that when the high-side power tube of another phase (the load of the half-bridge system is mostly three-phase inductive load, such as a motor) is turned on, if the turn-off speed of the low-side power tube of the current phase is faster, the energy on the load inductance is not completely discharged. At this time, the current on the load inductor will freewheel through the freewheeling zener diode connected in parallel with the high-side power transistor, and at this time, the floating reference VSWill rise rapidly. Because the conduction speed of the freewheeling voltage-stabilizing diode is very high, the generated noise is also large, the noise in the actual power integrated circuit is mostly the same, and the noise finally passes through the drain electrode of the LDMOS transistorThe parasitic capacitance of the circuit generates a large displacement current, and the displacement current can generate voltage drop on the load resistor, so that the subsequent circuit mistakenly considers the displacement current as a normal working signal and influences the normal work of the whole power integrated circuit.
Therefore, in this embodiment, a digital trigger module is added to the high-side level shift circuit, and since the output terminal of the digital trigger module is connected to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 at the same time, the control terminal of the digital trigger module is connected to the output terminal of the output driver circuit; at this time, the digital trigger module takes the output signal of the output driving circuit as a clock control signal. Therefore, when the circuit works normally, the digital trigger module cannot influence the normal working state of the whole circuit. When noise comes, a path to the ground is formed by the drain-source parasitic capacitances of the first LDMOS transistor 1 and the second LDMOS transistor 2; at this time, the digital trigger module is triggered when the output signal HO is in the rising edge time period, so that the output end of the digital trigger module is in a low level, and the low level will pull up the drain electrode potential of the first LDMOS transistor LDMOS1, so that the circuit is restored to a normal operating state, thereby eliminating noise interference.
Therefore, the embodiment is a high-end power control circuit which takes the final output signal fed back to the preceding stage circuit as the clock control signal, and has the advantages of simple structure and small chip volume; noise interference in the working process of the existing high-end power control circuit is eliminated more effectively.
As a specific implementation manner, as shown in fig. 1, the digital trigger module includes an xor gate and a D flip-flop, and an output end of the xor gate is connected to a D end of the D flip-flop; at this time, the first input end of the digital trigger module is the first input end of the xor gate, the second input end of the digital trigger module is the second input end of the xor gate, the output end of the digital trigger module is the Q end of the D trigger, and the control end of the digital trigger module is the CLK end of the D trigger.
As another embodiment, as shown in fig. 2, the digital trigger module includes an and gate, a D flip-flop, and a phase inverter, where an output end of the and gate is connected to a D end of the D flip-flop, an anode of the phase inverter is connected to a Q end of the D flip-flop, and a cathode of the phase inverter is connected to a gate of the second PMOS transistor; at this time, the first input end of the digital trigger module is the first input end of the and gate, the second input end of the digital trigger module is the second input end of the and gate, the output end of the digital trigger module is the Q end of the D flip-flop or the negative electrode of the phase inverter, and the control end of the digital trigger module is the CLK end of the D flip-flop.
In order to make the signals of the first input end and the second input end of the digital trigger module have better delay matching with the output signal of the output driving circuit, the high-side power control circuit is provided with an even-numbered inverter. And the anode of the even-level inverter is connected with the output end of the output driving circuit, and the cathode of the even-level inverter is connected with the control end of the digital trigger module.
The anti-interference method of the high-side power control circuit based on digital logic disclosed in the present invention is further described in detail with reference to the embodiments shown in the drawings.
As shown in fig. 1-3, when the circuit is in a normal operating state, if the signal V is input to the gate of the first LDMOS transistor LDMOS1in1The potential of the drain electrode of the first LDMOS transistor LDMOS1, i.e. the potential of the point a, is pulled down from high to low, and the input signal enters the RS flip-flop through the filter circuit and serves as the RESET input of the RS flip-flop.
Then the first LDMOS1 is turned off, and a signal V is input to the gate of the second LDMOS2 after a period of timein2The potential of the drain electrode of the second LDMOS transistor LDMOS2, i.e., the potential of the B point, is pulled from the high level to the low level, the input signal enters the RS flip-flop through the filter circuit and is input as the SET terminal of the RS flip-flop, and then the second LDMOS transistor LDMOS2 is turned off.
The above input signal Vin1Input signal Vin2Are low-voltage narrow pulse signals. At this time, the RESET end and the SET end of the RS triggerThe two low-voltage narrow pulse signals are reduced into the required high-voltage wide pulse signal in a matched mode, the driving capability is improved through the output driving circuit, and finally a control signal HO (the control signal HO is the output driving circuit) of the high-end power device is formed.
As shown in FIG. 4 or FIG. 5, when the noise signal is generated, the effective effect is to pull down the A-point potential and the B-point potential to a low level, and the noise signal affecting the whole circuit occurs in the floating reference VSA phase of rapid rise. Therefore, the anti-interference method for the high-side power control circuit based on the above embodiment is as follows:
s102, loading sudden change to enable the floating reference VSPotential transients, thereby generating a noise signal; the drain of the first LDMOS transistor LDMOS1 and the drain of the second LDMOS transistor LDMOS2 are at a low level at the same time, and the first input end and the second input end of the digital trigger module are at a low level at the same time;
s104, when the output signal HO of the output driving circuit enters a rising edge stage, triggering the digital trigger module, so that the output end of the digital trigger module keeps outputting at a low level;
s106, the low level of the output end of the digital trigger module controls the first PMOS tube MP1 to be opened, so that the potential of the drain electrode of the first LDMOS1 is pulled high to reduce the pulse width of a noise signal, and a narrow pulse noise signal is formed;
and S108, filtering the narrow pulse noise signal by the filter circuit, and reserving a working pulse signal.
Because the narrow pulse noise signal can be easily processed by the subsequent filter circuit, the noise signal mixed in the working pulse signal can be effectively filtered.
In specific implementation, when the rising edge phase of the output signal HO of the output driver circuit is cut off, the digital trigger module is in an unfired state, and the high-side power control circuit enters the normal operation as shown in fig. 3. Therefore, the digital trigger module only plays a role in generating noise signals and cannot influence the normal operation of the whole circuit.
As can be seen from the comparison between fig. 4 and fig. 5, whether the drain voltage of the second LDMOS transistor LDMOS2 is high or low does not affect the control signal HO of the final effective high-side power device restored by the RS flip-flop.
Thus, as an alternative embodiment, when the digital trigger module comprises an exclusive or gate, a D flip-flop,
at this time, as shown in fig. 4, when the low level of the output terminal of the digital trigger module controls the first PMOS transistor MP1 to be turned on, the second PMOS transistor MP2 is turned on, and the drain potential of the second LDMOS transistor LDMOS2 is also pulled high at the same time.
As another alternative embodiment, when the digital trigger module includes an and gate, a D flip-flop and an inverter,
at this time, as shown in fig. 5, when the low level of the output terminal of the digital trigger module controls the first PMOS transistor MP1 to be turned on, the second PMOS transistor MP2 is turned off, and the drain potential of the second LDMOS transistor LDMOS2 is still at the low level.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention should be determined by the appended claims.

Claims (8)

1. A high-end power control circuit based on digital logic is characterized by comprising a pulse generating circuit, a high-end level shift circuit, a filter circuit, an RS trigger and an output drive circuit which are matched with each other, wherein the high-end level shift circuit comprises a digital trigger module, and a first LDMOS (laterally diffused metal oxide semiconductor) tube, a first PMOS (P-channel metal oxide semiconductor) tube, a first voltage-stabilizing diode, a first resistor, a second LDMOS tube, a second PMOS tube, a second voltage-stabilizing diode and a second resistor which are matched with the digital trigger module;
the filter circuit, the RS trigger and the output drive circuit are sequentially connected in series, power ends of the filter circuit, the RS trigger and the output drive circuit are connected to a floating power supply at the same time, and grounding ends of the filter circuit, the RS trigger and the output drive circuit are connected to a floating reference at the same time;
the source electrode of the first LDMOS transistor is grounded, the grid electrode of the first LDMOS transistor is connected with the first output end of the pulse generation circuit, and the drain electrode of the first LDMOS transistor is simultaneously connected with the drain electrode of the first PMOS transistor, the first resistor, the anode of the first voltage stabilizing diode and the first input end of the digital trigger module and is connected to the first input end of the filter circuit; the source electrode of the first PMOS tube, the spare end of the first resistor and the cathode of the first voltage stabilizing diode are connected and connected to the floating power supply;
the source electrode of the second LDMOS transistor is grounded, the grid electrode of the second LDMOS transistor is connected with the second output end of the pulse generation circuit, the drain electrode of the second LDMOS transistor is simultaneously connected with the drain electrode of the second PMOS transistor, the second resistor, the anode of the second voltage regulator diode and the second input end of the digital trigger module and is connected to the second input end of the filter circuit, and the source electrode of the second PMOS transistor, the spare end of the second resistor and the cathode of the second voltage regulator diode are connected and connected to the floating power supply;
the output end of the digital trigger module is simultaneously connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, and the control end of the digital trigger module is connected with the output end of the output drive circuit; at this time, the digital trigger module takes the output signal of the output driving circuit as a clock control signal, so that the digital trigger module is triggered in a time period when the output signal is in a rising edge, and further the output end of the digital trigger module is always in a low level state.
2. The digital logic based high-side power control circuit according to claim 1, comprising an even number of stages of inverters, wherein an anode of the even number of stages of inverters is connected to the output terminal of the output driver circuit, and a cathode of the even number of stages of inverters is connected to the control terminal of the digital trigger module.
3. The digital logic based high-side power control circuit according to claim 1, wherein the digital trigger module comprises an exclusive or gate and a D flip-flop, and an output terminal of the exclusive or gate is connected to a D terminal of the D flip-flop; at this time, the first input end of the digital trigger module is the first input end of the xor gate, the second input end of the digital trigger module is the second input end of the xor gate, the output end of the digital trigger module is the Q end of the D trigger, and the control end of the digital trigger module is the CLK end of the D trigger.
4. The high-side power control circuit of technical digital logic according to claim 1, wherein the digital trigger module comprises an and gate, a D flip-flop and an inverter, an output terminal of the and gate is connected to a D terminal of the D flip-flop, an anode of the inverter is connected to a Q terminal of the D flip-flop, and a cathode of the inverter is connected to a gate of the second PMOS transistor; at this time, the first input end of the digital trigger module is the first input end of the and gate, the second input end of the digital trigger module is the second input end of the and gate, the output end of the digital trigger module is the Q end of the D flip-flop or the negative electrode of the phase inverter, and the control end of the digital trigger module is the CLK end of the D flip-flop.
5. A method of immunity of a high-side power control circuit based on digital logic, performed by the high-side power control circuit of any of claims 1-4, comprising:
load sudden changes to make the floating reference potential transient, thereby generating a noise signal; the drain electrode of the first LDMOS transistor and the drain electrode of the second LDMOS transistor are at low level at the same time, and the first input end and the second input end of the digital trigger module are at low level at the same time;
the output signal of the output driving circuit enters a rising edge stage to trigger the digital trigger module, so that the output end of the digital trigger module keeps low level output;
the low level of the output end of the digital trigger module controls the first PMOS tube to be opened, so that the potential of the drain electrode of the first LDMOS tube is pulled high to reduce the pulse width of a noise signal, and a narrow pulse noise signal is formed;
the filter circuit filters the narrow pulse noise signal and reserves a working pulse signal.
6. The digital logic based high-side power control circuit immunity method of claim 5, comprising:
when the rising edge stage of the output signal of the output driving circuit is cut off, the digital trigger module is in an un-triggered state, and the high-end power control circuit enters normal operation.
7. The digital logic based high-side power control circuit immunity method of claim 5, wherein when said digital trigger module comprises an XOR gate, a D flip-flop,
when the low level of the output end of the digital trigger module controls the first PMOS tube to be opened, the second PMOS tube is also opened, and the drain electrode potential of the second LDMOS tube is also pulled high at the same time.
8. The digital logic based high-side power control circuit immunity method of claim 5, wherein when the digital trigger module comprises an AND gate, a D flip-flop and an inverter,
when the low level of the output end of the digital trigger module controls the first PMOS tube to be opened, the second PMOS tube is closed, and the drain electrode potential of the second LDMOS tube is still at the low level.
CN202210092022.XA 2022-01-26 2022-01-26 High-end power control circuit based on digital logic and anti-interference method Pending CN114448402A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114759780A (en) * 2022-06-15 2022-07-15 无锡硅动力微电子股份有限公司 Anti-interference method and device for integrated controller in switching power supply and integrated controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114759780A (en) * 2022-06-15 2022-07-15 无锡硅动力微电子股份有限公司 Anti-interference method and device for integrated controller in switching power supply and integrated controller

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