CN114448203A - Control circuit and corresponding method - Google Patents

Abstract

Embodiments of the present disclosure relate to control circuits and corresponding methods. A circuit receives an input signal having a first level and a second level. The logic circuit includes a finite state machine circuit, an edge detection circuit, and a timer circuit. The finite state machine circuit is configured to set an operating mode of the circuit. The edge detection circuit is configured to detect a transition between the first level and the second level. The timer circuit is configured to determine whether the first level or the second level is maintained for a period of time that begins from a transition detected by the edge detection circuit. The finite state machine circuit is configured to change the operating mode based on the timer circuit determining that the first level or the second level has been maintained for more than the period of time.

Description

Control circuit and corresponding method

Cross Reference to Related Applications

The disclosures in italian application No. 102020000026530, filed on 6.11.2020, which is hereby incorporated by reference in its entirety, are claimed for priority.

Technical Field

The present disclosure relates generally to control logic for electronic circuits, and in particular embodiments, to dynamically managing two different operating modes for a device and an external clock via a single pin.

Background

Some types of electronic devices may support two different modes of operation. Synchronization with a clock signal generated by an external master clock may be desirable for one or both of these modes.

For example, a switching DC-DC converter may function in a low consumption mode (e.g., burst switching) and a low noise mode (e.g., constant switching). The synchronization signal may be provided by an external clock signal applied to a pin in the device for the latter mode, which may identify the signal frequency.

In packages with a limited number of pins, any of the possible operating modes may be selected by a different "part number" defined for each mode, or a "pin shorting" function may be provided that sets the operating mode at device start-up so that the same pins may be used in steady state for other functions.

Furthermore, if the selected mode provides possible synchronization with an external clock (e.g., as may be the case for a low noise mode), the clock may be supplied via a dedicated pin.

This may lead to limitations in the possible application areas of the device, since dynamic switching from one mode to another (as may be desired) mode is not supported.

It is desirable to provide greater flexibility in these cases (where a single pin of the device is configured to facilitate dynamic (e.g., on-the-fly) transitions between different operating modes) and a scheme to manage the external synchronous clock via the same pin.

Disclosure of Invention

In accordance with one or more embodiments, a circuit and method are provided herein.

As discussed, the flexibility of those devices having different modes of operation that are suitable for selection from the outside can be at a disadvantage in applications where it is desirable to change the mode of operation while running. As mentioned, this problem is not properly addressed via pin shorting or by static selection between two different modes of operation assigning different part numbers to each of the two modes.

At least in principle, dynamic mode changes may be implemented by programming of internal registers, which would involve continuous accessibility of standard programming interfaces.

One or more embodiments may exploit a single pin of a device with a reduced area increase to facilitate possible dynamic management of two different operating modes, while also providing an external synchronous clock via the same pin.

In one or more embodiments, the use of a single pin provides the advantage of avoiding the use of multiple pins for devices configured to dynamically switch between two different modes of operation, where one of the two modes involves an external clock for synchronization. In this embodiment, no additional pins would be used for modes of operation that do not involve an external clock.

In one or more embodiments, the mode of operation may be determined by a temporal evaluation of the level present on, for example, an input pin (e.g., a single). This configuration may be used for mode selection as well as for applying an external clock.

In one or more embodiments, an external control level is associated with each mode, wherein the logic circuit is configured to check for a level change of the signal by detecting, for example, a falling edge associated with the level change. In these embodiments, a low level is associated with the first MODE of operation (MODE1) and a high level is associated with the second MODE of operation (MODE 2). For example, if the level signal is driven low at startup, then the device "knows" that the current configuration is in MODE1 and implements the relevant configuration in the device. The logic circuit may process information related to the evaluation duration if a level change occurs that may involve a configuration change. The (lower) time threshold may be chosen for each specific application. A change in configuration is verified if the signal on the (single) pin discussed previously remains constant at a certain level above the threshold for a duration of time.

The presence of a clock signal on the pin may be detected as a continuous level change.

One or more embodiments may include a Finite State Machine (FSM) circuit that handles changes between two operating modes and external clocks and enable and control signals. An edge detector may be provided to detect a rising or falling edge of the signal at the input pin corresponding to the level change. A level filter may be provided to evaluate the level change signal, for example to check if this is maintained for longer than a time threshold before modifying the operation mode or state.

Drawings

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1 and 2 are diagrams of operation mode transitions of an embodiment;

FIG. 3 is a block diagram of an embodiment;

FIG. 4 is a flowchart of the operation of an embodiment;

FIG. 5 is a diagram of the operation mode transition of the embodiment remaining valid;

FIG. 6 is a diagram of the operation mode transition of the embodiment remaining inactive;

FIG. 7 is a diagram of an embodiment of external clock verification; and

fig. 8 is a diagram of an embodiment with external clock removal.

Detailed Description

This disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments are merely illustrative of specific configurations and do not limit the scope of the claimed embodiments. Features from different embodiments may be combined to form further embodiments unless otherwise stated.

Variations or modifications described for one of the embodiments may also be used for other embodiments. Furthermore, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

In the following description, one or more specific details are set forth in order to provide a thorough understanding of the examples of embodiments described herein. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail so that certain aspects of the embodiments will not be difficult to understand.

Reference to "an embodiment" or "one embodiment" in the framework of the description of the invention is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may be presented in one or more points described herein do not necessarily refer to one or the same embodiment.

Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The headings/references used herein are provided for convenience only and thus do not define the scope of protection or the scope of the embodiments.

One or more embodiments may be applicable to, for example, circuits such as L7983 synchronous buck switching regulator devices, as currently available from fay semiconductor corporation.

This circuit may be seen as an example of a circuit that enables (at least) two different operating modes, namely a Low Consumption Mode (LCM) and a Low Noise Mode (LNM); the possibility of managing both modes, for example by means of a single pin, and the switching action with the low noise mode is synchronized with the external clock. Reference to this circuit is by way of example only and does not limit the embodiments.

One or more embodiments facilitate selection between different modes of operation through a single pin of a device (e.g., through dynamic management of transitions from one mode to another). In addition, one or more embodiments provide a logic circuit capable of checking whether an external synchronous clock signal is present on the pin.

As discussed, certain devices that fix the operating mode at startup (e.g., via pulling up to VCC or pulling down to GND on the select pin) do not consider the possibility of dynamically changing the operating mode as desired by various applications.

For example, in some devices, the configuration is fixed via trim bits, which may limit flexibility. Furthermore, if synchronization with an external clock is considered for one of the operating modes, the pins for providing the clock may be kept floating when the device is configured in a mode or application where synchronization is not desired.

One or more embodiments may involve a time evaluation mechanism for signal values at input pins of a device configuration, thereby providing greater flexibility in device usage.

Fig. 1 and 2 refer by way of example to possible transitions between two MODEs of operation, namely MODE1 and MODE 2. Fig. 1 is an example of a conversion from MODE1 to MODE 2. Fig. 2 is an example of a conversion from MODE2 to MODE 1. It will be further appreciated that one or more embodiments are very "transparent" to the nature of these two modes of operation.

The illustrated example refers to a pin 10 (not visible as a whole in fig. 1 and 2) in an electronic circuit. Pin 10 can be configured to receive a signal MODSEL _ CLKEXT for selecting between two MODEs of operation (i.e., MODE1 and MODE 2).

Throughout this specification, for simplicity and ease of understanding, pin 10 will also be referred to as the MODSEL _ CLKEXT pin.

In the illustrated example, this MODSEL _ CLKEXT pin may also be used to provide a device associated with a (e.g., external) synchronization clock CLKEXT, as desired for either (or both) of the two aforementioned modes of operation.

For example, the MODE of operation (MODE1 or MODE2) may be selected on the MODSEL _ CLKEXT pin by keeping the pin at a constant level (e.g., high or low, where each level is associated with one of the MODEs) for time Tmin. The time Tmin for maintaining the signal level may be set to vary (possibly by setting thereof) depending on the application for which the device is intended to be used.

For example, in FIG. 1, when MODE1 is enabled, the rising edge of the signal at the MODSEL _ CLKDEXT pin can be "filtered" within Tmin to detect a stable high level before the internal MODE signal is set to MODE 2.

Further, in FIG. 2, when MODE2 is enabled, the falling edge of the signal at the MODSEL _ CLKDEXT pin can be "filtered" within Tmin to detect a stable low level before the internal MODE signal is set to MODE 1.

Those skilled in the art will readily appreciate that the specific references to rising/falling edges and high/low levels are merely exemplary, as the same type of operation may be obtained, with the roles of rising/falling edges and/or high/low levels reversed.

In one or more embodiments, the time Tmin may be used to determine the current operating MODE (i.e., MODE1 or MODE2) and facilitate dynamic switching between the two MODEs when a change in operating MODE is desired.

One or more embodiments may relate to detection logic that continuously detects rising and falling edges of a signal at the MODSEL _ CLKEXT input pin with the ability to detect level changes and determine an operating mode based on the following mechanisms.

For example, if the high or low level of the signal at MODSEL _ CLKEXT remains stable for a minimum time T at least equal to Tmin at device start-up, then the device is configured to be in the corresponding mode of operation.

Furthermore, if a (falling or rising) edge of the signal is subsequently detected such that the level changes (e.g., from high to low or vice versa) and the new level is maintained for a time T at least equal to Tmin, then the logic interprets this level change as expected to produce a change in the operating mode of the device.

Furthermore, if a pulse train is detected at the pin (e.g. continuous level change or switching), a check of the possible presence of an external synchronization clock is made — affecting a spike in signal values or a continuous transition between operating modes.

For example, if an indication that the signal level at the MODSEL _ CLKEXT pin switches at a time period T shorter than time Tmin is detected as a steady level, the time between successive rising edges of the signal may be analyzed (e.g., based on information received from a circuit block that may filter the external clock).

Furthermore, if at least N rising edges of the signal are detected for a time period less than or equal to the lower threshold Tckmin, it is assumed that a CLKEXT clock signal is present at the pin with a frequency greater than or equal to 1/Tckmin.

The time Tckmin may be selected as the longest period considered by the external clock (i.e. its maximum value) -an indication of the lowest (i.e. smallest) frequency within the frequency range considered by the external clock. An overview of the selection mechanism discussed above is reproduced in table I below.

TABLE I-selection of operating mode based on signal level

Those skilled in the art will again appreciate that the specific references to low/high levels and MODE1/MODE2 are merely exemplary, as the roles of levels and MODEs to implement the same type of operation may be reversed.

In an embodiment, a circuit such as an integrated device is considered to have (at least) two different operating MODEs (e.g., MODE1 and MODE2) that can be selected depending on two different levels of a signal applied to an input pin (MODSEL _ CLKEXT), where the same pin can also provide an external clock for synchronization.

In this embodiment, an in-service change in the operating MODE of device switching, e.g., to MODE2 (see fig. 1) when MODE1 is enabled or to MODE1 (see fig. 2) when MODE2 is enabled, is facilitated from an external drive pin, e.g., via a microprocessor or other logic circuit.

For example, in the illustrated example, the operating mode may be enabled at device boot-up, considered the default mode, which may be selected in response to a low level signal ("0") at the MODSEL _ CLKEXT input pin.

The control logic processes the corresponding signal of value "0" and indicates the value MODE1 of the internal MODE signal.

The MODE2 can be selected in response to the high level present at the input pin MODSEL _ CLKEXT corresponding to the value "1" of the internal MODE signal.

Fig. 3 is a block diagram example of an embodiment circuit 100 according to the described embodiments of the invention including control logic and some support blocks.

As illustrated in FIG. 3, circuit 100 includes logic circuit 120 built around Finite State Machine (FSM) circuit 12 that is configured to manage the transitions between the two operating MODEs (i.e., MODE1, MODE2) and the selection of an external clock dependent upon signals from the various blocks and supporting circular blocks in the logic circuit.

For example, as illustrated in fig. 3, the circuit 12A may be configured to generate MODE signals (MODE1 or MODE2) in accordance with the signals old _ MODE, new _ MODE, and update _ MODE of the finite state machine circuit 12, as discussed below.

As similarly discussed below, the finite state machine circuit 12 may also be configured to generate signals CLK _ EXT _ GOOD and CLK _ EXT _ FILT related to selection of an external clock, as discussed below.

As illustrated in fig. 3, logic circuit 120 includes edge detection circuit 14, edge detection circuit 14 being sensitive to signal MODSEL _ CLKEXT at pin 10. The edge detection circuit 14 is configured to detect rising or falling edges of the input signal received at the pin, which correspond to level changes in the signal MODSEL _ CLKEXT and generate a corresponding signal mode _ CLKEXT _ edge applied to the finite state machine circuit 12.

As illustrated in fig. 3, the logic circuit 120 also includes a timer circuit 16. Timer circuit 16 may include a counter configured to evaluate (i.e., enabled by signal mode _ cnt _ en from finite state machine circuit 12) whether the level change of signal MODSEL _ CLKEXT at pin 10 is maintained for a minimum time (Tmin) before verifying the new mode of operation. This may involve generating an overflow signal to the active state machine circuitry 12 due to the count signal mode _ cnt (see also fig. 4 and 5) reaching an upper threshold (Thmin) that depends on the time Tmin previously discussed.

As illustrated in fig. 3, logic circuit 120 also receives information from check circuit 18 and counter circuit 20 to verify the presence of an external clock signal that is possibly applied to pin 10 as the MODSEL _ CLKEXT signal.

As illustrated in fig. 3, the check circuit 18 comprises a counter configured to evaluate whether the frequency of the incoming pulse train received at pin 10 corresponds to (i.e., coincides with) the lowest (i.e., minimum frequency) frequency allowed by the external clock by generating a respective signal (i.e., the designated TCLK _ GOOD in the figure) that is applied to the finite state machine circuit 12.

As illustrated in fig. 3, counter circuit 20 comprises another counter configured to count the N number of rising edges of an incoming pulse train received as MODSEL _ CLKEXT, which facilitates determining the presence of an external clock by generating a corresponding signal (i.e., designated NPulse _ OK in the drawing) that is applied to finite state machine circuit 12.

As illustrated in fig. 3, the circuit 100 also includes a clock circuit 22 (of any type known to those skilled in the art), which clock circuit 22 generates an internal clock signal CLK _ INT that is supplied to the control logic 120, as discussed below in connection with fig. 5 and 6.

Clock circuit 22 may be included in circuit 140 in fig. 3 even though illustrated as a separate element for ease of explanation.

As illustrated in fig. 3, the logic circuit 120 is configured to pass the signal pattern, CLK _ EXT _ GOOD, and CLK _ EXT to another circuit 140 in the circuit 100. These circuit stages may include, for example, one or more analog blocks and oscillators.

One or more embodiments are very "transparent" to the nature of circuitry 140, which also motivates embodiments to be very transparent to the nature of the MODEs (i.e., MODE1, MODE 2).

Fig. 4 is a flow diagram of an exemplary embodiment of possible operations of the control logic as previously discussed.

Step 1000 corresponds to the start (start-up mode).

At step 1002, the device is configured to operate in a default MODE selected from MODE1 and MODE2, which is dependent on the current value (e.g., low or high) of the signal MODSEL _ CLKEXT (i.e., MODE — MODSEL _ CLKEXT).

At step 1004, the occurrence of rising/falling edges in the signal MODSEL _ CLKEXT as indicated by the signal MODSEL _ CLKEXT from the edge detection circuit 14 is checked. If the check yields a negative result (no-no edge detected), then return to step 1002.

At step 1006, if the check at step 1004 produces a positive result (i.e., yes — edge detected), then the signal mode _ new is made equal to MODSEL _ CLKEXT.

At step 1008, the duration of the level transition caused by the edge is measured by setting mode _ CNT _ en to "1", incrementing the count CNT to CNT +1, and setting the mode to the current mode, i.e., mode _ curr.

At step 1010, the current (accumulated) count value is checked against an overflow for a threshold value corresponding to Tmin. At each increment, the value is compared to a threshold value and an overflow signal is generated in response to the count reaching a count value.

At step 1012, if the check at step 1010 yields a negative result (i.e., no — no longer the threshold duration is exceeded), then another check is performed as to whether modsel _ clkext _ edge from edge detection circuit 14 indicates a (further) edge. If the check at step 1012 yields a negative result (i.e., no another edge was not detected), then return is made to step 1008.

At step 1014, if the check at step 1010 is positive (i.e., if a count overflow occurs indicating that the level change of MODSEL _ CLKEXT continues to exceed Tmin), mode _ cnt _ en is "0" and update _ mode is mode _ new.

At step 1016, the operating mode is set to the new mode (caused by the change) mode — update _ mode.

At step 1018, when the counter has exceeded the threshold, in response to the result of the check at step 1012 being positive (i.e., yes-another edge detected), CNT is set to "0," indicating a spike in the input signal as expected.

At step 1020, it is checked whether CLK EXT GOOD from check circuit 18 indicates that the frequency of the received incoming pulse train coincides with the lowest (minimum) frequency allowed by the external clock. If the check at step 1020 is negative (i.e., a spike in the input signal is confirmed), then the process returns to step 1006.

At step 1022, in response to the check at step 1020 being positive (i.e., the frequency of the received incoming burst is consistent with the minimum frequency allowed by the external clock), then proceed to step 1016 as previously discussed.

At step 1024, regardless of the path to step 1016 (e.g., from step 1014 or step 1022) subsequently, another check is performed whether CLK EXT GOOD from check circuit 18 indicates that the frequency of the received incoming burst is consistent with the minimum frequency allowed by the external clock. If the check at step 1024 is positive, then go back to step 1016.

At step 1026, in response to the check at step 1024 being negative (i.e., no), another check is performed whether modsel _ clkext _ edge from the edge detection circuit 14 indicates an (another) edge. If the check at step 1026 is negative (i.e., no another edge is not detected), then the process returns to step 1016. If the check at step 1026 is positive (i.e., another edge is detected), then return is made to step 1006.

It should be noted that the check for CLK _ EXT _ GOOD at step 1016-step 1024 will be negative in response to a count overflow corresponding to a mode change and the current mode will be maintained until a new signal edge occurs.

Further, the check for CLK _ EXT _ GOOD in response to identifying that the external clock arrived at step 1016-1024 from step 1022 will be positive, and the pattern corresponding to the presence of the external clock will be maintained until the check becomes negative.

Furthermore, the signal CLK _ EXT _ GOOD generated by the finite-state-machine circuit 12 depends on the signals TCLK _ GOOD (e.g., the distance between two consecutive rising edges corresponding to the minimum expected frequency) and Npulse _ OK (e.g., a count of at least N >1 rising edges on the MODSEL _ CLKEXT pin) from the check circuit 18 and counter circuit 20, respectively, where these blocks are enabled on the rising edge of the signal at the MODSEL _ CLKEXT pin.

As previously discussed, the operations may be further illustrated by reference to fig. 5 and 6. These figures depict the common time scale t (abscissa scale), the possible timing behavior of the following signals (from top to bottom): an internal clock signal CLK _ INT from clock circuit 22 (fig. 3); signal MODSEL _ CLKEXT received at pin 10; the signal new _ mode from the finite state machine circuit 12; the signal mode _ clkext _ edge from the edge detection circuit 14; an enable signal mode _ cnt _ en provided by the finite state machine circuit 12 to the timer circuit 16; a level filtering signal mode _ cnt; by the timer circuit 16 in response to the signal mode _ cnt reaching the upper threshold th_minAn overflow signal (which varies as a function of the threshold time Tmin) provided to the finite state machine circuit 12; and a switched MODE signal (e.g., from MODE1 to MODE 2).

In short, when the signal on the MODSEL _ CLKEXT pin (i.e., pin 10) undergoes a level shift (e.g., from low to high in fig. 5), the edge detection circuit 14 detects the change (which is a signal edge) and generates a corresponding mode _ CLKEXT _ edge pulse.

This pulse is processed in the finite state machine circuit 12, which therefore performs various actions, as previously discussed in connection with the flow chart of fig. 4: the MODE _ cnt _ en signal is generated, the timer circuit 16 is enabled, the MODE signal is maintained at the current level (e.g., low) MODE1 until the new level is verified (e.g., high MODE2), and the change in the new level is stored via the internal signal new _ MODE (e.g., high MODE 2).

The timer circuit 16, enabled by the mode _ cnt _ en signal from the finite state machine circuit 12, increments the mode _ cnt counter at each cycle of the internal clock CLK _ INT until the threshold count value th is reached_minUntil now.

As discussed, this threshold may be defined as a minimum time value Tmin established pursuant to verification of the operating mode for the device.

When the mode _ cnt counter reaches a threshold (e.g., no further change in detected signal level), the timer circuit 16 generates an overflow signal (e.g., flag) that resets the count.

In response to detecting the overflow flag, the finite state machine circuit 12 updates the internal MODE signal to the logic value previously stored on "new _ MODE" (e.g., high — MODE2), which is evaluated as stable by the timer circuit 16 for time Tmin.

The device operating MODE is then updated to the new operating MODE (e.g., MODE 2).

Similarly, if a subsequent falling edge is detected on the input pin (i.e., MODSEL _ CLKEST at pin 10) and the signal level remains low for a time greater than Tmin after this edge, then the finite state machine circuit 12 will again change the MODE of operation (e.g., to MODE 1).

If the signal present on the input pin changes level again and then reaches the threshold th at the counter (signal mode _ cnt)_minPreviously back to the previous level, the logic circuit 120 will not change the value of the mode signal, treating the change as a spike in the input signal.

This possible mode of operation is illustrated in fig. 6.

As noted, FIG. 5 is an example of a MODE transition that causes a change from MODE1 to MODE2 in response to a rising edge in the signal MODSEL _ CLKEST, which results in an overflow signal being asserted.

By contrast, the right hand side of FIG. 6 is an example of an "inactive" MODE transition, where MODE1 is asserted (regardless of the falling edge in signal MODSEL CLKEST) to not reached corresponding to Th_minThe threshold value of (2) is set as a result of the count signal mode _ cnt.

If a pulse train occurs on the MODSEL _ CLKEST pin (i.e., pin 10), the logic circuit 120 can investigate whether this corresponds to an external clock or is caused by a continuous change in the operating mode.

This type of operation is illustrated in fig. 7 (external clock verification) and fig. 8 (external clock removal).

These figures again depict the common time scale t (abscissa scale), the possible time-sequential behavior of the following signals (from top to bottom): signal MODSEL _ CLKEXT received at pin 10; the signal CLK _ EXT _ GOOD from the finite-state-machine circuit 12; the signal CLK _ EXT _ FILT from the finite state machine circuit 12; and switching (e.g., from MODE1 to MODE2 in fig. 7, and from MODE2 to MODE1 in fig. 8).

As illustrated herein, counter circuit 20 detects each rising edge of the signal on the MODSEL _ CLKEXT pin (i.e., pin 10), and generates the Npulse _ OK signal in response to the N number of rising edges having been counted.

At the same time, filtering of the frequency of the clock signal received at the MODSEL _ CLKEXT pin (i.e., pin 10) is performed in check circuit 18. Check circuit 18 is enabled at each rising edge of the signal on the MODSEL _ CLKEXT pin and is configured to evaluate the distance between two consecutive rising edges and to undergo a reset when the distance between the edges exceeds the value of the minimum expected frequency of the (expected) external clock signal.

If the detected edges are separated by a time Tck shorter than Tckmin, then the check circuit 18 generates a TCLK _ GOOD signal. Thus, the logic circuit 120 will generate the internal signal CLK _ EXT _ GOOD to verify the presence of the external clock CLK _ EXT on pin 10(MODSEL _ CLKEXT). The clock will thus have a period defined by the switching time Tck of the pulse train.

The MODE signal will be appropriate for MODE2, which in the illustrated example provides for the provision/synchronization of an external clock.

For example, if MODE1 is enabled before receiving the burst, the MODE changes from MODE1 to MODE 2. On the other hand, if MODE2 was the enabled MODE prior to the burst, MODE2 would be verified. In both cases, the logic circuit 120 will pass the external clock to the circuit 140 (see FIG. 3) through the CLK _ EXT _ FILT output of the finite state machine circuit 12.

That is, as illustrated in fig. 7: if at least N rising edges are detected separated by a distance Tck (CLK _ EXT _ GOOD asserted) that is less than Tckmin, then the logic circuit 120 filters the value on pin MODSEL _ CLKEST (pin 10) to check for a valid external clock and validate the clock. Once verified, the clock is forwarded to circuit 140 internally in the finite state machine circuit 12 (CLK _ EXT _ FILT asserted) and the internal signal MODE is set to MODE2 or validated at MODE 2.

If conversely (see FIG. 8), the validation signal CLK _ EXT _ GOOD is reset during the time Tck when no rising edge is detected, and the logic circuit 120 causes a counter in the timer circuit 16 to check whether the signal level on the MODSEL _ CLKEXT pin remains stable at time T > Tmin.

If the signal on the MODSEL _ CLKEXT pin remains stable (e.g., high) up to the threshold set by Tmin, then the internal MODE signal remains at MODE 2. On the other hand, if steady low for Tmin, the internal signal will switch to MODE 1.

The logic circuit 120 thus continuously monitors the change in signal on the input pin (MODEL _ CLKEST-pin 10), thereby facilitating dynamic switching between the MODEs of operation provided by the device (MODE1 to MODE2, and vice versa) and management of possible external clocks.

That is, as illustrated in fig. 8: the logic circuit 120 continuously checks the reset signal CLK EXT _ GOOD if the distance between two consecutive rising edges is shorter (lower) than Tck and if the distance is longer (higher) than Tck. The logic circuit 120 begins counting T > Tmin to detect whether a stable level (high or low) is present on the input pin and changes the internal mode signal accordingly.

The example illustrated herein refers to the case where the external synchronous clock is considered for only one of the two MODEs, here the MODE indicated as MODE 2.

Those skilled in the art will additionally appreciate that the present invention will also apply mutatis mutandis to the more general case of an externally synchronized clock recognized by both MODE1 and MODE 2.

In this case, the user can set a first desired mode with a first action, keep the signal level stable at time T > Tmin, and then provide a synchronized clock as described.

As previously repeated, those skilled in the art will readily appreciate that the specific references to certain signal edges, respectively rising and falling edges, and certain signal levels, respectively high and low levels, are merely exemplary, as the same type of operation may be achieved, e.g., where the roles of rising/falling edges and/or high/low levels are reversed.

A circuit (e.g., 100) as exemplified herein may include a logic circuit (e.g., 120) coupled to an input node (e.g., 10) configured to receive an input signal (e.g., MODSEL _ CLKEXT) exhibiting a transition between a first level and a second level. The logic circuit may include a state machine (e.g., 12) coupled to the input node. The state machine is configured to set the circuit (e.g., 100, including the stage 140) to either one of a first MODE of operation (e.g., MODE1) and a second MODE of operation (e.g., MODE2) in response to an input signal (e.g., via a signal MODE) having a first level or a second level, respectively.

Further, edge detector blocks (e.g., 14) are coupled to the input nodes. The edge detector block is configured to detect transitions (e.g., rising and falling edges) between a first level and a second level in the input signal and to send a corresponding transition signal (e.g., mode _ clkext _ edge) to the state machine (12).

Further, a timer block (e.g., 16) is coupled (e.g., to be enabled via a signal mode _ cnt _ en) to the state machine and is configured to check whether the first level or the second level in the input signal is maintained beyond a threshold period (e.g., Tmin) from a transition detected by the edge detector block.

The state machine is configured to change the operating mode of the circuit from one of the first and second operating modes to the other operating mode in response to a check in the timer block indicating that the first level or the second level in the input signal has been maintained within a threshold period from the transition detected by the edge detector block.

The circuitry as exemplified herein may include processing circuitry (e.g., check circuitry 18 and counter circuitry 20) coupled to the input nodes and a state machine. The processing circuit is configured to apply a signal received at the input node as a verification clock signal to the circuit in response to the input signal exhibiting N number of transitions from one of the first level and the second level to the other and a frequency of transitions between the first level and the second level that exceeds a lower threshold.

One or more embodiments may therefore utilize edges that occur within Tmin and at a lower (e.g., minimum) limit on the frequency of the edge in order to assert that a real clock is applied to the pin.

If the pin level changes, where the frequency is below a threshold of the frequency of the external signal identified as a clock signal (which threshold frequency may be selected and set to vary depending on the intended application or use), the signal considered as a clock will be erroneous, since the signal will only correspond to the user in selecting one mode instead of another.

In one or more embodiments, to evaluate the presence of an external clock, the time TCKmin elapsed between two consecutive rising edges of the signal is checked to be less than the time Tmin during which the signal remains stable after a level change causing a mode change.

Furthermore, even in the presence of an "acceptable" frequency value, checking for the presence of N number of transitions from one of the first level and the second level to the other level may provide a safety limit that asserts the presence of a clock signal over a (e.g. minimum) desired number of clock cycles N via a masking action (where N ═ 1 represents a limiting condition of this masking action).

A circuit as exemplified herein may be configured to apply a signal received at the input node as a verify clock signal to a circuit for only one of a first MODE of operation and a second MODE of operation (e.g., only for MODE2 and not for MODE 1).

That is, the clock signal may (but need not) be passed to the circuitry for only one of the two MODEs, which in turn means that the clock signal identified at MODEL _ CLKEST does not imply a change between MODE1 and MODE 2.

In the circuit as illustrated, the state machine may thus be configured to apply the signal received at the input node as the verification clock signal to the circuit in conjunction with setting or maintaining the circuit in the only one of the first and second modes of operation.

That is, the state machine may be configured to change the operating mode of the circuit only if one of the two levels at MODSEL _ CLKEXT is maintained for more than a threshold period Tmin from the transition detected by the edge detection circuit 14.

For example, if the signal at MODSEL _ CLKEST remains high up to the threshold indicated by Tmin, then the internal MODE signal remains at MODE 2. If, conversely, the signal at MODSEL _ CLKEST is stable low within Tmin, then the internal MODE signal switches to MODE1, as illustrated in FIG. 8.

That is, the state machine may be configured to change the operating MODE of the circuit from one of the first and second operating MODEs to the other operating MODE (e.g., from MODE1 to MODE2) only in response to a check in the timer block (e.g., 16) indicating that a first level (e.g., low) in the input signal has been maintained for a threshold period of time from a transition detected by the edge detector block.

Conversely, the state machine may be configured to maintain the MODE of operation of the circuit at one of the first MODE of operation and the second MODE of operation (e.g., maintain MODE2) in response to a check in the timer block indicating that the second level (e.g., high) in the input signal has been maintained for the threshold period of time from the transition detected by the edge detector block.

As illustrated herein, a method of operating a circuit (e.g., 100) having an output node (e.g., 10) configured to receive an input signal (e.g., MODSEL _ CLKEXT) exhibiting a transition (e.g., rising/falling edge) between a first level and a second level may include setting the circuit to either of a first MODE of operation (e.g., MODE1) and a second MODE of operation (e.g., MODE2) in response to the input signal (e.g., via a signal MODE) having a first level or a second level, respectively.

The method may further include detecting a transition between the first level and the second level in the input signal (e.g., at the edge detection circuit 14), checking (e.g., at the timer circuit 16) whether the first level or the second level in the input signal is maintained beyond a threshold period (e.g., Tmin) from the detected transition (by the edge detection circuit 14).

The method may further include changing the mode of operation of the circuit from one of the first mode of operation and the second mode of operation to the other mode of operation in response to the first level or the second level in the input signal being maintained for more than a threshold period of time from a transition detected by the edge detector block.

A method as exemplified herein may include applying a signal received at an input node as a verification clock signal to a circuit in response to an input signal exhibiting N number of transitions from one of a first level and a second level to the other and a frequency of transitions between the first level and the second level that exceeds a lower threshold.

Although the specification has been described in detail, it should be understood that various changes, substitutions, and alterations can be made hereto without departing from the spirit and scope of the disclosure as defined by the appended claims. Like elements are represented by like reference numerals throughout the several views. Moreover, the scope of the present disclosure is not intended to be limited to the particular embodiments described herein, as one of ordinary skill in the art will readily appreciate from the present disclosure that processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Accordingly, the specification and drawings are to be regarded only as illustrative of the present disclosure as defined in the appended claims, and are intended to cover any and all modifications, variations, combinations, or equivalents falling within the scope of the present disclosure.

Claims (20)

1. A circuit, comprising:

an input node configured to receive an input signal having a first level value and a second level value; and

a logic circuit coupled to the input node and configured to receive the input signal, the logic circuit comprising:

a finite state machine circuit configured to configure an operation mode of the circuit to a first operation mode or a second operation mode based on the input signal being at the first level value or the second level value, respectively,

an edge detection circuit configured to detect transitions between the first level value and the second level value and to pass a corresponding transition signal to the finite state machine circuit based on the transitions, an

A timer circuit configured to determine whether the first level value or the second level value is maintained for more than a threshold period of time, the threshold period of time starting from a transition detected by the edge detection circuit, and wherein the finite state machine circuit is configured to change the operating mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained for more than the threshold period of time.

2. The circuit of claim 1, further comprising a processing circuit, wherein the finite state machine circuit is configured to correlate the input signal to a verification clock signal based on: determining, by the processing circuit, that the input signal includes a number N of transitions between the first level value and the second level value, and determining, by the processing circuit, that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

3. The circuit of claim 2, wherein the finite state machine circuit is configured to:

correlating the input signal to a verification clock signal, an

Setting the operating mode of the circuit to or maintaining the circuit at only one of the first or second operating modes.

4. The circuit of claim 2, wherein the circuit is configured to correlate the input signal as a verification clock signal for only one of the first or second modes of operation.

5. The circuit of claim 4, wherein the finite state machine circuit is configured to:

correlating the input signal to a verification clock signal, an

Setting or maintaining the operational mode at only one of the first operational mode or the second operational mode.

6. The circuit of claim 1, wherein the finite state machine circuit being configured to change the operating mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained for more than the threshold period of time comprises: changing the operating mode of the circuit based on the timer circuit determining that the first level value has been maintained for more than the threshold period of time; and

maintaining the operational mode of the circuit based on the timer circuit determining that the second level value has been maintained for more than the threshold period of time.

7. The circuit of claim 1, further comprising:

a counter circuit configured to determine that the input signal includes a number N of transitions between the first level value and the second level value; and

a checking circuit configured to determine that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

8. A method of operating a circuit, the method comprising:

configuring an input node to receive an input signal having a first level value and a second level value;

setting an operation mode of the circuit to a first operation mode or a second operation mode based on the input signal being at the first level value or the second level value, respectively;

detecting a transition between the first level value and the second level value;

determining whether the first level value or the second level value is maintained for more than a threshold period of time; and

changing the operating mode based on determining that the first level value or the second level value has been maintained for more than the threshold period of time.

9. The method of claim 8, further comprising: associating the input signal as a verification clock signal based on determining that the input signal includes a number N of transitions between the first level value and the second level value and determining that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

10. The method of claim 9, further comprising setting the operating mode to or maintaining the operating mode at only one of the first or second operating modes.

11. The method of claim 9, further comprising correlating the input signal as a verification clock signal for only one of the first or second modes of operation.

12. The method of claim 11, further comprising:

determining a time difference between two consecutive rising edges of the input signal; and

resetting the verification clock signal to be associated with the input signal based on determining that the time difference is greater than a threshold.

13. The method of claim 11, further comprising setting the operating mode to or maintaining the operating mode at only one of the first or second operating modes.

14. The method of claim 8, changing the mode of operation based on determining that the first level value or the second level value has been maintained beyond the threshold period of time comprises:

changing the operating mode based on determining that the first level value has been maintained for more than the threshold period of time; and

maintaining the operational mode based on determining that the second level value has been maintained for more than the threshold period of time.

15. A system, comprising:

a clock circuit configured to generate a signal having a first level value and a second level value; and

a circuit coupled to the clock circuit and configured to receive the signal at an input of the circuit, the circuit comprising logic circuitry configured to receive the signal, the logic circuitry comprising:

a finite state machine circuit configured to configure an operation mode of the circuit to a first operation mode or a second operation mode based on the signal being at the first level value or the second level value, respectively,

an edge detection circuit configured to detect transitions between the first level value and the second level value and to pass a corresponding transition signal to the finite state machine circuit based on the transitions, an

A timer circuit configured to determine whether the first level value or the second level value is maintained for more than a threshold period of time, the threshold period of time starting from a transition detected by the edge detection circuit, and wherein the finite state machine circuit is configured to change the operating mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained for more than the threshold period of time.

16. The system of claim 15, wherein the logic circuitry further comprises processing circuitry, wherein the finite state machine circuitry is configured to correlate the signal as a verification clock signal based on: determining, by the processing circuit, that the signal includes a number N of transitions between the first level value and the second level value, and determining, by the processing circuit, that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

17. The system of claim 16, wherein the finite state machine circuit is configured to:

correlating said signal as a verification clock signal, an

Setting the operating mode of the circuit to or maintaining the circuit at only one of the first or second operating modes.

18. The system of claim 16, wherein the circuitry is configured to correlate the signal as a verification clock signal for only one of the first or second modes of operation.

19. The system of claim 15, wherein the finite state machine circuit being configured to change the operating mode of the circuit based on the timer circuit determining that the first level value or the second level value has been maintained for more than the threshold period of time comprises: changing the operating mode of the circuit based on the timer circuit determining that the first level value has been maintained for more than the threshold period of time; and

maintaining the operational mode of the circuit based on the timer circuit determining that the second level value has been maintained for more than the threshold period of time.

20. The system of claim 15, wherein the logic circuit further comprises:

a counter circuit configured to determine that the signal includes a number N of transitions between the first level value and the second level value; and

a checking circuit configured to determine that a frequency of transitions between the first level value and the second level value is greater than a lower threshold.

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