CN114446913A

CN114446913A - Semiconductor packaging structure

Info

Publication number: CN114446913A
Application number: CN202111566304.0A
Authority: CN
Inventors: 洪齐元; 王贻源
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2021-12-20
Filing date: 2021-12-20
Publication date: 2022-05-06

Abstract

The present application provides a semiconductor package structure, the semiconductor package structure includes: an interposer; the semiconductor chip layer is positioned on the intermediate layer and comprises at least two semiconductor chips which are arranged side by side in a direction parallel to the surface of the intermediate layer; a hybrid bond structure between and connecting the semiconductor chip layer and the interposer; the hybrid bond structure is used to transmit signals between the semiconductor chip layer and the interposer.

Description

Semiconductor packaging structure

Technical Field

The application relates to the technical field of integrated circuit chips, in particular to a semiconductor packaging structure.

Background

The Package (Package) is a very critical part in the manufacture of integrated circuits, has an important influence on the performance and performance of the chip itself, and not only plays a role in placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance, but also plays a role in electrically connecting bonding points in the integrated circuit chip with the outside.

With the continuous development of emerging industries such as smart phones, high-performance computing, artificial intelligence, automatic driving, 5G networks, internet of things and the like, integrated circuits are also changing towards high performance, multiple functions and miniaturization. Thus, the integrated circuits are required to have higher and higher integration and more complex functions, and accordingly, the packaging density of the integrated circuits is required to be higher and higher. Therefore, the three-dimensional packaging technology is developed, so that a plurality of chips can be packaged together, interconnection among different chips is realized, the packaging volume and pins are reduced, and the power consumption is reduced. However, the stereo package still has many problems such as high cost, poor signal integrity, poor expansion flexibility, and poor stability.

Disclosure of Invention

In view of the above, an embodiment of the present application provides a semiconductor package structure, including:

an interposer;

the semiconductor chip layer is positioned on the intermediate layer and comprises at least two semiconductor chips which are arranged side by side in a direction parallel to the surface of the intermediate layer;

a hybrid bond structure between and connecting the semiconductor chip layer and the interposer; the hybrid bond structure is used to transmit signals between the semiconductor chip layer and the interposer.

In some embodiments, the semiconductor chip includes:

a first semiconductor chip and a second semiconductor chip;

the interposer includes: a first connection circuit; the first connection circuit is used for connecting the first semiconductor chip and the second semiconductor chip through the hybrid bonding structure.

In some embodiments, the first semiconductor chip includes: a system-on-chip; the second semiconductor chip includes: an on-chip memory.

In some embodiments, the on-chip memory includes at least one of:

high bandwidth memory, static random access memory, dynamic random access memory, magnetic random access memory, and flash memory.

In some embodiments, the hybrid bonding structure comprises:

a first hybrid bonding structure for connecting the first semiconductor chip and the interposer;

a second hybrid bonding structure for connecting the second semiconductor chip and the interposer;

the first and second hybrid bond structures are connected by a first connection circuit in the interposer.

In some embodiments, the first semiconductor chip includes: a first physical layer interface for connecting with the first hybrid bonded structure;

the second semiconductor chip includes: a second physical layer interface for connecting with the second hybrid bond structure.

In some embodiments, the semiconductor package structure further comprises:

the packaging substrate is positioned on one side of the interposer layer, which is far away from the semiconductor chip layer;

and the bump connecting structure is positioned between the packaging substrate and the interposer and used for connecting the interposer and the packaging substrate.

In some embodiments, the interposer further comprises: a second connection circuit extending through the interposer; the second connection circuit is used for connecting the bump connection structure and the hybrid bonding structure.

In some embodiments, an active device is also included within the interposer; the active device is used for controlling the first connecting circuit and/or the second connecting circuit.

In some embodiments, the semiconductor package structure further comprises:

the circuit board is positioned on one side of the packaging substrate, which is far away from the interposer, and is used for bearing the packaging substrate;

and the packaging solder balls are positioned between the circuit board and the packaging substrate and are used for connecting the circuit board and the packaging substrate.

In the semiconductor packaging structure provided by the embodiment of the application, the semiconductor chip layer and the intermediate layer are connected through the hybrid bonding structure, and hybrid bonding has the characteristics of high signal integrity, small space, good high-temperature stability and the like. Therefore, the number of transferable signals in unit area between the semiconductor chip layer and the interposer and the connection stability are improved, and the horizontal distance between the system-on-chip and the on-chip memory is reduced to the micrometer level, so that the space utilization rate and the packaging integration level are improved.

Drawings

Fig. 1 is a schematic view of a semiconductor package structure according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a first connection circuit in a semiconductor package structure according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a physical layer interface in a semiconductor package structure according to an embodiment of the present disclosure;

fig. 4 is a schematic view of a semiconductor package structure having a package substrate according to an embodiment of the present disclosure;

fig. 5 is a schematic diagram of a second connection circuit in a semiconductor package structure according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a semiconductor package structure having a circuit board according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of a semiconductor package structure having a microbump structure according to an embodiment of the present disclosure;

fig. 8 is a schematic view of another semiconductor package structure according to an embodiment of the present disclosure.

Detailed Description

To facilitate an understanding of the present application, exemplary embodiments disclosed herein will be described in more detail below with reference to the associated drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In some embodiments, some technical features that are well known in the art are not described in order to avoid confusion with the present application; that is, not all features of an actual embodiment may be described herein, and well-known functions and structures may not be described in detail.

In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Additionally, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily expressly described, again depending at least in part on the context.

Unless otherwise defined, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present application. The following detailed description of the preferred embodiments of the present application, however, will suggest that the present application may have other embodiments in addition to these detailed descriptions.

As shown in fig. 1, an embodiment of the present application provides a semiconductor package structure 100, including: an interposer 110; a semiconductor chip floor 120 on the interposer 110, the semiconductor chip floor 120 including at least two semiconductor chips, the two semiconductor chips being placed side by side in a direction parallel to a surface of the interposer 110; a Hybrid Bonding (Hybrid Bonding) structure 130 located between the semiconductor chip layer 120 and the interposer 110 and connecting the semiconductor chip layer 120 and the interposer 110; the hybrid bond structure 130 is used to transmit signals between the semiconductor chip layer 120 and the interposer 110.

It should be understood that in order to clearly show each layer structure in the drawings, the dimensional ratio of each layer structure may not be consistent with the actual structure.

In the present embodiment, the Interposer (Interposer)110 may be a non-organic material, such as a semiconductor material, a glass material, and/or a ceramic material. The semiconductor material may include elemental semiconductor materials such as silicon, germanium, selenium, or the like, or synthetic semiconductor materials such as gallium arsenide, indium gallium arsenide, or the like.

The semiconductor chip floor 120 is located on the interposer 110, and the semiconductor chip floor 120 includes at least two semiconductor chips. The semiconductor chips are placed side by side in a direction parallel to the surface of the interposer 110, i.e., the bottom surfaces of the semiconductor chips are located in the same plane on the interposer 110. Also, there may be a pitch between the semiconductor chips in a direction parallel to the surface of the interposer 110. In order to reduce the size of the package structure to achieve higher integration, the pitch of the semiconductor chips should be as small as possible.

The hybrid bond structure 130 is located between the semiconductor chip floor 120 and the interposer 110 and connects the semiconductor chip floor 120 and the interposer 110, and the hybrid bond structure 130 is also used to transmit signals between the semiconductor chip floor 120 and the interposer 110. Hybrid bonding structure 130 refers to a structure that achieves bonding by multiple different bonding means on the same surface. The hybrid bond structure 130 may be composed of a plurality of hybrid bonds, which refers to a single bump structure connecting the semiconductor chip layer 120 and the interposer 110 in the hybrid bond structure 130. The hybrid bonding structure 130 may include a plurality of bonding methods among insulator-insulator bonding, semiconductor-semiconductor bonding, and metal-metal bonding to achieve simultaneous bonding between metals and between media, thereby solving the wafer-level underfill problem and having high physical connection reliability.

In some embodiments, a Micro Bump (Micro Bump) structure is used to connect the semiconductor chip layer 120 and the interposer layer 110, so as to realize a 2.5D package structure with a plurality of different semiconductor chips horizontally arranged side by side. The microbumps may be pure metals (e.g., Au, Cu, Sn, In, etc.), eutectic or high melting point alloys (e.g., PbSn, AuSn, AgSn, SnCu, AgSnCu, etc.) materials. However, the 2.5D package using the micro bumps has the following problems: the packaging cost is high; the micro bumps connected to the interposer 110 are prone to crack at high temperature, and have poor stability; poor power and signal integrity; the number of micro bumps per unit area is limited, which is not favorable for the expansion of complex functions.

In the embodiment of the present application, the semiconductor chip layer 120 and the interposer 110 are connected by the hybrid bond structure 130. The hybrid bonding technology has the advantages of low cost, better thermal stability, almost no attenuation of transmission signals and better signal integrity. In addition, the Pitch (Pitch) of each hybrid bond is much smaller than that of the micro bump, the number of hybrid bonds in a unit area is larger, and the number of transmitted signals is larger, so that the distance between the semiconductor chips on the interposer 110 is reduced from millimeter level to micrometer level, the integration level is increased, and more complex function expansion can be realized.

In some embodiments, as shown in fig. 2, the semiconductor chip includes: a first semiconductor chip 121 and a second semiconductor chip 122; the interposer 110 includes: a first connection circuit 111; the first connection circuit 111 is used to connect the first semiconductor chip 121 and the second semiconductor chip 122 through the hybrid bonding structure 130.

Semiconductor chip floor 120 may include a plurality of identical and/or a plurality of different functional semiconductor chips to meet the requirements of higher integration, more functional packaging. The first semiconductor chip 121 and the second semiconductor chip 122 are placed side by side in a direction parallel to the surface of the interposer 110 and connected to the interposer 110 by the hybrid bonding structure 130. The first connection circuit 111 is located inside the interposer 110, the first semiconductor chip 121 and the second semiconductor chip 122 are connected to each other via the hybrid bonding structure 130 and the first connection circuit 111, and the first connection circuit 111 may enable mutual transmission of signals of the first semiconductor chip 121 and the second semiconductor chip 122 inside the interposer 110.

In some embodiments, the first semiconductor chip 121 includes: a System on Chip (SoC) Chip; the second semiconductor chip 122 includes: an on-chip memory.

The system on chip is formed by combining a plurality of integrated circuits with specific functions on one chip, and achieves the purposes of reducing the volume, reducing the power consumption, increasing the system functions and saving the cost by reducing each node with different functions. Memory granules in on-chip memory are stack integrated in the form of a Die (Die). Through the hybrid bonding structure 130, heterogeneous integration between the interposer 110 and the on-chip memory, i.e., Die on Wafer (Die on Wafer) bonding, can be achieved, so that the distance between the on-chip memory and the system-on-chip is reduced from millimeter level to micrometer level.

In some embodiments, the on-chip memory includes at least one of:

high Bandwidth Memory (HBM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Magnetic Random Access Memory (MRAM), and Flash Memory (Flash).

The on-chip memory may include a plurality of storage media to satisfy data read-write requirements of different specific functions of the system-on-chip.

In some embodiments, as shown in fig. 2, the hybrid bonding structure 130 includes: a first hybrid bonding structure 131 for connecting the first semiconductor chip 121 and the interposer 110; a second hybrid bonding structure 132 for connecting the second semiconductor chip 122 and the interposer 110; the first hybrid bond structures 131 and the second hybrid bond structures 132 are connected by first connection circuits 111 in the interposer 110.

The first hybrid bonding structure 131 is located between the first semiconductor chip 121 and the interposer 110, and the second hybrid bonding structure 132 is located between the second semiconductor chip 122 and the interposer 110. The first hybrid bonding structure 131 and the second hybrid bonding structure 132 are connected to the first connection circuit 111 in the interposer 110, so as to realize mutual signal transmission between the first semiconductor chip 121 and the second semiconductor chip 122. Alternatively, the first hybrid bonding structure 131 and the second hybrid bonding structure 132 may be formed using different processes to meet the bonding requirements between the semiconductor chips with different functions and the interposer 110.

In some embodiments, as shown in fig. 3, the first semiconductor chip 121 includes: a first physical layer interface 1211 for interfacing with the first hybrid bond structure 131; the second semiconductor chip 122 includes: a second physical layer interface 1221 for interfacing with the second hybrid bond structure 132.

A first physical layer interface 1211 is located in the first semiconductor chip 121 and connected to the first hybrid bond structure 131, and a second physical layer interface 1221 is located in the second semiconductor chip 122 and connected to the second hybrid bond structure 132. The individual semiconductor chips are interconnected by a physical layer interface (PHY), a hybrid bonding structure 130, and a first connection circuit 111 in the interposer 110. However, in an actual package structure, the distance between the first semiconductor chip 121 and the second semiconductor chip 122 is relatively long in the horizontal direction, which causes signals transmitted between the first semiconductor chip 121 and the second semiconductor chip 122 to be attenuated, and therefore, a physical layer interface is required to be used for signal driving, thereby ensuring efficient transmission of signals over a long distance. In addition, the physical layer interface can also be used for processing timing, interface interaction and the like.

In some embodiments, as shown in fig. 4, the semiconductor package structure further includes: a package substrate 140 on a side of the interposer 110 away from the semiconductor chip layer 120; a bump connecting structure 150 located between the package substrate 140 and the interposer 110 for connecting the interposer 110 and the package substrate 140.

The package substrate 140 is disposed under the interposer 110, and the package substrate 140 and the interposer 110 are connected by a bump connecting structure 150 therebetween. The Package substrate 140 may be a System In Package (SiP) substrate, and the Package substrate 140 may contain only passive devices therein for supporting the interposer 110 and the semiconductor chip layer 120 thereon and electrically interconnecting the components in the Package structure through the routing inside the Package substrate 140. Alternatively, the package substrate 140 may be an organic substrate, a ceramic substrate, a silicon substrate, or the like.

The bump connecting structure 150 may be a Controlled collapse Chip Connection bump (C4 Bumps), and specifically, a copper pillar bump (C4 Cu Bumps) may be used to connect the package substrate 140 and the interposer 110, which has better performance and lower package cost.

In some embodiments, as shown in fig. 5, the interposer 110 further includes: second connection circuits 112 extending through the interposer 110; the second connection circuit 112 is used for connecting the bump connection structure 150 and the hybrid bonding structure 130.

The second connection circuits 112 are disposed inside the interposer 110 and penetrate through the interposer 110, and have upper ends connected to the hybrid bonding structures 130 and lower ends connected to the bump connection structures 150, thereby connecting the first semiconductor chip 121 and/or the second semiconductor chip 122 to the package substrate 140.

In some embodiments, active devices are also included within the interposer 110; the active device is used for controlling the first connection circuit 111 and/or the second connection circuit 112.

Active devices may also be included in the interposer 110, i.e., the interposer 110 is an active interposer. Optionally, the active device may include: routers, repeaters, voltage regulators, etc. The active device may control routing connections, relay links, etc. of the first connection circuit 111 and/or the second connection circuit 112, thereby improving signal transmission bandwidth and efficiency. Optionally, the interposer 110 may further include some logic to implement an interface function, which is beneficial for communication between different chips in the semiconductor chip layer 120, and reduces the processing requirements of the semiconductor chips.

In some embodiments, as shown in fig. 6, the semiconductor package structure further includes: a Circuit Board (Circuit Board)160 located on a side of the package substrate 140 away from the interposer 110 for carrying the package substrate 140; and a Package solder ball (Package Balls)170 located between the circuit board 160 and the Package substrate 140, for connecting the circuit board 160 and the Package substrate 140.

The circuit board 160 is located below the package substrate 140 and is used for carrying the package substrate 140, the interposer 110 and the semiconductor chip layer 120. The Circuit Board 160 may be a Printed Circuit Board (PCB) with a Ball Grid Array (BGA) structure, and has the characteristics of a small package area, a large number of pins, high reliability, low cost, and the like.

The package solder balls 170 are used to connect the circuit board 160 and the package substrate 140, and the circuit board 160 and the package substrate 140 are connected together by melting and solidifying the package solder balls 170, and the package solder balls 170 may be a tin-lead eutectic alloy.

In some embodiments, as shown in fig. 7, a plurality of different chips and on-chip memories are connected to and interconnected in an interposer by micro-bump structures, while the chips are also connected through-silicon vias and controlled collapse chip connection bumps in the interposer into a package substrate. However, using the microbump structures to connect the interposer and the respective chips has the following disadvantages: the packaging cost is high; the micro-bump connected with the intermediate layer is easy to crack at high temperature and has poor thermal stability; the number of the micro bumps on the unit area is limited, which is not beneficial to the expansion of complex functions; signal and power integrity is poor.

In view of this, the present embodiment provides another alternative semiconductor package structure 200, as shown in fig. 8, including: an interposer 210; a system-on-chip die 220 on the interposer 210; an on-chip memory 230 on the interposer 210, side-by-side with the SoC chip 220 in a direction parallel to the surface of the interposer 210; a hybrid bonding structure 240 for connecting the soc chip 220 and the interposer 210, and connecting the on-chip memory 230 and the interposer 210; a package substrate 250 positioned below the interposer 210; a bump connecting structure 260 for connecting the package substrate 250 and the interposer 210; a circuit board 270 located under the package substrate 250; and package solder balls 280 for connecting the circuit board 270 and the package substrate 250.

Among other things, the interposer 210 includes: a first connection circuit 211 and a second connection circuit 212. The first connection circuit 211 is used to connect the system-on-chip 220 and the on-chip memory 230 through the hybrid bond structure 240. Second connecting circuits 212 extend through the interposer 210 for connecting the soc chip 220 to the package substrate 250.

The on-chip memory 230 includes at least one of the following storage media: high bandwidth memory, static random access memory, dynamic random access memory, magnetic random access memory, and flash memory. Thereby satisfying the data read/write requirements of the soc chip 220 with different functions.

The soc chip 220 includes a first physical layer interface 221; the on-chip memory 230 includes a second physical layer interface 231. The first physical layer interface 221 and the second physical layer interface 231 are used to drive signals transmitted between the soc chip 220 and the on-chip memory 230, so as to ensure efficient transmission of signals over long distances.

Compared with the micro bump structure, the hybrid bonding structure 240 has lower process cost, better thermal stability, almost no attenuation of transmission signals, and better signal integrity. In addition, the distance between the hybrid bonds is much smaller than that of the micro bumps, the number of the hybrid bonds in a unit area is larger, the number of transmitted signals is larger, the distance between the soc chip 220 and the on-chip memory 230 on the interposer 210 is reduced from millimeter level to micrometer level, the integration level is increased, and more complex function expansion can be realized.

The semiconductor package structure 200 provided by the embodiment of the application can be compatible with 2.5D package design, and provides a better choice and a cheaper choice. The inter-chip interconnection between the soc chip 220 and the on-chip memory 230 may extend the design scheme of 2.5D package, and a physical layer interface for signal driving is put into the soc chip 220, while the on-chip memory 230 may maintain the inherent interface protocol standard without any modification. From the perspective of chip design flow, the on-chip memory 230 is integrated in a bare-die manner, and only the interface protocol needs to be agreed in advance, while only the connection manner with the on-chip memory 230 and the package substrate 250 needs to be considered in the design process of the soc chip 220.

It should be noted that the features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily to obtain new method or apparatus embodiments without conflict.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor package structure, comprising:

an interposer;

2. The semiconductor package structure of claim 1, wherein the semiconductor chip comprises:

a first semiconductor chip and a second semiconductor chip;

3. The semiconductor package structure of claim 2, wherein the first semiconductor chip comprises: a system-on-chip; the second semiconductor chip includes: an on-chip memory.

4. The semiconductor package structure of claim 3, wherein the on-chip memory comprises at least one of:

5. The semiconductor package structure of claim 2, wherein the hybrid bond structure comprises:

the first hybrid bond structure and the second hybrid bond structure are connected by a first connection circuit in the interposer.

6. The semiconductor package structure of claim 5, wherein the first semiconductor chip comprises: a first physical layer interface for connecting with the first hybrid bonded structure;

7. The semiconductor package structure of claim 2, further comprising:

8. The semiconductor package structure of claim 7, wherein the interposer further comprises: a second connection circuit extending through the interposer; the second connection circuit is used for connecting the bump connection structure and the hybrid bonding structure.

9. The semiconductor package structure of claim 8, further comprising an active device within the interposer; the active device is used for controlling the first connecting circuit and/or the second connecting circuit.

10. The semiconductor package structure of claim 7, further comprising: