CN118073319A - Packaging structure and packaging method - Google Patents

Abstract

A packaging structure and a packaging method, the method includes: forming an adapter plate comprising a first surface and a second surface which are opposite; the adapter plate comprises a first area and a second area, wherein the first area is provided with a plurality of discrete conductive columns, the second area is provided with an interconnection chip, and the conductive columns and the side parts of the interconnection chip are filled with a first packaging layer; providing a chip set comprising one or more device chips, wherein the device chips comprise a first surface and a second surface which are opposite to each other, a second packaging layer is formed between adjacent device chips and on the side wall of the device chips, and a first rewiring structure electrically connected with the device chips is formed on the first surface; bonding the chipset and the adapter plate, wherein the first surface of the adapter plate is opposite to the first surface, micro-bumps are formed between the first rewiring structure and the conductive columns and between the first rewiring structure and the interconnection chip, and the micro-bumps are electrically connected with the conductive columns and the interconnection chip. The embodiment of the invention improves the interconnection density and interconnection performance between the adapter plate and the chipset.

Description

Packaging structure and packaging method

Technical Field

The embodiment of the invention relates to the technical field of semiconductor packaging, in particular to a packaging structure and a packaging method.

Background

Conventional chip fabrication techniques are being pushed toward their limits for the size of monolithic chips. However, applications desire the ability to implement large-scale integrated circuits using state-of-the-art technology, with challenges in achieving high-speed and low-volume interconnections between chips.

One current solution is to use a smaller integrated circuit of silicon Bridge (Si Bridge) chips embedded in a silicon substrate to enable chip-to-chip interconnection through the silicon Bridge chips to provide heterogeneous chip packaging.

But the interconnection density and interconnection performance between the interposer and the chipset remain to be improved.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a packaging structure and a packaging method, and improves the interconnection density and interconnection performance between an adapter plate and a chipset.

In order to solve the above-mentioned problems, an embodiment of the present invention provides a package structure, including: the adapter plate comprises a first surface and a second surface which are opposite; the adapter plate comprises a first area and a second area positioned between the first area, wherein the first area is formed with a plurality of discrete conductive columns, the second area is formed with an interconnection chip, and the conductive columns and the side parts of the interconnection chip are filled with a first packaging layer; the interconnection chip and the conductive column are exposed out of the first surface; the chip set comprises one or more device chips, the device chips are distributed along the direction parallel to the device chips, the device chips comprise a first surface and a second surface which are opposite to each other, a second packaging layer is formed between the adjacent device chips and on the side wall of the device chips, a first rewiring structure is formed on the first surface, and the first rewiring structure is electrically connected with the device chips; the first surface of the chipset is bonded on the first surface of the adapter plate; and the micro-bump is positioned between the first rewiring structure and the conductive column and between the micro-bump and the interconnection chip, and is electrically connected with the conductive column and the interconnection chip.

Optionally, the first surface is a front surface of the chip, and the second surface is a back surface of the chip.

Optionally, the package structure further includes: and a second rewiring structure positioned between the first packaging layer and the micro-bump, between the conductive post and the micro-bump, and between the interconnection chip and the micro-bump.

Optionally, the package structure further includes: and the third rewiring structure is positioned on the second surface of the adapter plate and is electrically connected with the conductive post.

Optionally, the package structure further includes: and the substrate is bonded on the second surface of the adapter plate and is electrically connected with the third rewiring structure.

Optionally, the package structure further includes: and the conductive bump is positioned between the third rewiring structure and the substrate and electrically connects the third rewiring structure and the substrate.

Optionally, the package structure further includes: and the sealing layer is filled between the first surface of the adapter plate and the chipset, and is filled in gaps among the micro bumps and seals the micro bumps.

Optionally, an interconnection pad is formed on the interconnection chip; the interconnection pad is exposed on the first surface of the adapter plate; the microbumps are electrically connected with the interconnection pads of the interconnection chip.

Optionally, the first rewiring structure comprises one or more rewiring layers.

Correspondingly, the embodiment of the invention also provides a packaging method, which comprises the following steps: forming an adapter plate comprising a first surface and a second surface which are opposite; the adapter plate comprises a first area and a second area positioned between the first area, wherein the first area is formed with a plurality of discrete conductive columns, the second area is formed with an interconnection chip, and the conductive columns and the side parts of the interconnection chip are filled with a first packaging layer; the interconnection chip and the conductive column are exposed out of the first surface; providing a chip set comprising one or more device chips, wherein the device chips are distributed along a direction parallel to the device chips, the device chips comprise a first surface and a second surface which are opposite to each other, a second packaging layer is formed between adjacent device chips and on the side wall of the device chips, a first rewiring structure is formed on the first surface, and the first rewiring structure is electrically connected with the device chips; bonding the chipset and the adapter plate, wherein the first surface of the adapter plate is opposite to the first surface, micro-bumps are formed between the first rewiring structure and the conductive columns and between the first rewiring structure and the interconnection chip, and the micro-bumps are electrically connected with the conductive columns and the interconnection chip.

Optionally, the step of forming the interposer includes: providing a first carrier plate, wherein the first carrier plate comprises a first area and a second area positioned between the first areas; forming discrete conductive pillars on a first carrier plate of the first region; attaching an interconnection chip on the first carrier plate in the second area; after forming the conductive column and attaching the interconnection chip, forming a first packaging layer filled in the side part of the conductive column and the side part of the interconnection chip on the first carrier, wherein the conductive column and the interconnection chip are exposed out of the first packaging layer; after bonding the chipset and the interposer, the packaging method further includes: and removing the first carrier plate.

Optionally, after forming the first encapsulation layer, the encapsulation method further includes: forming a second rewiring structure on the first packaging layer, wherein the second rewiring structure is electrically connected with the conductive column and the device chip; in the step of bonding between the chipset and the interposer, the microbumps are contacted with a second rewiring structure.

Optionally, after the first carrier is provided and before the conductive pillars are formed and the interconnection chip is bonded, the step of forming the interposer further includes: forming a third rewiring structure on the first carrier plate; in the step of forming the conductive pillars, the conductive pillars are formed on and electrically connected with the third rewiring structure; in the step of attaching the interconnect chip, the interconnect chip is attached to the third rewiring structure.

Optionally, the packaging method further includes: after the first carrier plate is removed, the second surface of the adapter plate is bonded on the substrate, and the third rewiring structure is arranged opposite to and electrically connected with the substrate.

Optionally, the packaging method further includes: after the first carrier plate is removed and before the second surface of the adapter plate is bonded on the substrate, forming a conductive bump on the third rewiring structure; in the step of bonding the chipset and the interposer to the substrate, the conductive bumps are bonded to and electrically connected with the substrate.

Optionally, the step of bonding between the chipset and the interposer includes: forming a plurality of microbumps on the first rewiring structure; bonding the micro-bump with the first surface of the adapter plate.

Optionally, in the step of providing the chipset, forming a microbump; the step of providing a chipset comprises: providing a second carrier plate; providing one or more device chips, wherein the device chips comprise a first surface and a second surface which are opposite to each other, and the second surface of the one or more device chips is attached to a second carrier plate; forming a second packaging layer on a second carrier plate at the side part of the device chip, wherein the first surface of the second packaging layer is exposed; forming a first rewiring structure on the second packaging layer, wherein the first rewiring structure is electrically connected with the first surface; forming a plurality of microbumps on the first rewiring structure; and removing the second carrier plate.

Optionally, the step of forming the second encapsulation layer includes: forming a packaging material layer covering the side part of the device chip and the first surface on the second carrier plate; and removing the packaging material layer higher than the first surface to expose the first surface, wherein the rest packaging material layer is used as a second packaging layer.

Optionally, the packaging method further includes: after bonding the chip set and the interposer, a sealing layer is filled between the first face of the interposer and the chip set, the sealing layer filling gaps between the micro bumps and sealing the micro bumps.

Optionally, an interconnection pad is formed on the interconnection chip; the interconnection pad is exposed on the first surface of the adapter plate; in the step of bonding between the chipset and the interposer, the micro bumps are electrically connected to the interconnect pads of the interconnect chip.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

According to the packaging structure provided by the embodiment of the invention, the second surface, the space between adjacent device chips and the side wall of the device chip are provided with the second packaging layer, the first surface is provided with the first rewiring structure, the first surface of the chip set is bonded on the first surface of the adapter plate, and the micro-bumps are arranged between the first rewiring structure and the conductive columns and between the first rewiring structure and the interconnection chip.

In the packaging method provided by the embodiment of the invention, the interposer and the chipset are respectively formed, then the chipset and the interposer are bonded, the first surface of the interposer is opposite to the first surface, and the microbumps are electrically connected with the conductive columns and the interconnection chips.

Drawings

Fig. 1 to 5 are schematic structural diagrams corresponding to each step in a packaging method;

FIG. 6 is a schematic diagram of an embodiment of a package structure according to the present invention;

Fig. 7 to 12 are schematic structural diagrams corresponding to each step in an embodiment of the packaging method of the present invention.

Detailed Description

As known from the background art, the performance of the current package structure needs to be improved. The reason why the performance of the packaging structure needs to be improved is analyzed by combining a packaging method. Fig. 1 to 5 are schematic structural diagrams corresponding to each step in a packaging method.

Referring to fig. 1, a carrier 10 is provided, including first regions (not labeled) and second regions (not labeled) located between the first regions; forming discrete conductive pillars 11 on the carrier plate 10 in the first region; an interconnect chip 12 is attached to the carrier 10 in the second region.

Referring to fig. 2, after forming the conductive pillars 11 and attaching the interconnect chip 12, first encapsulation layers 13 filled in the sides of the conductive pillars 11 and the interconnect chip 12 are formed on the carrier 10, and the first encapsulation layers 13 expose the conductive pillars 11 and the interconnect chip 12.

Referring to fig. 3, a re-wiring structure 14 is formed on the first encapsulation layer 13, and the re-wiring structure 14 is electrically connected with the conductive pillars 11 and the interconnect chip 12.

Referring to fig. 4, a plurality of micro bumps 15 are formed on the rewiring structure 14.

Referring to fig. 5, a plurality of device chips 16 are bonded on the microbumps 15; a second encapsulation layer 17 is formed over the rewiring structure 14 covering the device chip 16.

In the above packaging method, after the conductive pillars are formed and the device chips are attached, a first packaging layer is formed, and then a rewiring structure is formed on the first packaging layer, where the pitch of the rewiring structure cannot meet the requirements of improving the interconnection density and the interconnection performance.

The number of the conductive posts is a plurality of, and the conductive posts are of a cylindrical structure, after the conductive posts are formed and the device chip is attached, a first packaging layer is formed, the top surface of the first packaging layer, the conductive posts and the device chip are low in consistency and flatness, and the process requirement of forming a rewiring structure with small space and high density on the first packaging layer is difficult to meet.

In order to solve the technical problems, the embodiment of the invention provides a packaging structure, a second surface, a second packaging layer, a first rewiring structure, a first surface of a chip set, a micro bump, a first rewiring structure, a second rewiring structure, a first conductive post and an interconnection chip, wherein the second packaging layer is formed on the second surface, between adjacent device chips and on the side wall of the device chips, the first rewiring structure is formed on the first surface, the first surface of the chip set is bonded on the first surface of an adapter plate, and the micro bump is arranged between the first rewiring structure and the conductive post and between the first rewiring structure and the interconnection chip.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Referring to fig. 6, a schematic structural diagram of an embodiment of the package structure of the present invention is shown.

As shown in fig. 6, in the present embodiment, the package structure includes: an interposer 110 including opposite first and second faces 101, 102; the interposer 110 includes a first region (not shown) formed with a plurality of discrete conductive pillars 120 and a second region (not shown) between the first region formed with interconnect chips 130, the conductive pillars 120 and the interconnect chips 130 side-filled with a first encapsulation layer 140; interconnect die 130 and conductive pillars 120 are exposed at first face 101; a chipset 20 including one or more device chips 200, the plurality of device chips 200 being distributed in a direction parallel to the device chips 200, the device chips 200 including first and second surfaces 201 and 202 opposite to each other, second package layers 210 being formed between adjacent device chips 200 and on sidewalls of the device chips 200, first rewiring structures 220 being formed on the first surface 201, the first rewiring structures 220 being electrically connected to the device chips 200; the first surface 201 of the chipset 20 is bonded to the first face 101 of the interposer 110; the micro bump 230 is located between the first rewiring structure 220 and the conductive pillar 120 and between the micro bump and the interconnect chip 130, and the micro bump 230 is electrically connected with the conductive pillar 120 and with the interconnect chip 130.

An Interposer 110 is used to make electrical connection between the chipset 20 and external circuitry.

Specifically, the interposer 110 has smaller line width and space, and supports heterogeneous integration, so that connection between different device chips is realized through the interposer 110, which is beneficial to reducing power consumption and increasing bandwidth.

The first side 101 of the interposer 110 is used to enable bonding with the chipset 20.

In this embodiment, the second surface 102 is used to achieve bonding with the substrate.

The first region is used to form conductive pillars 120 and the second region is used to form interconnect die 130.

The conductive posts 120 are used to make electrical connection between the chipset 20 and external circuitry.

In this embodiment, the material of the conductive pillars 120 is copper, i.e., the conductive pillars 120 are copper pillars. In other embodiments, the material of the conductive posts may also be other metallic materials.

Interconnect die 130 is used as a device-to-chip Bridge (Bridge) for interconnecting device dies and device dies, thereby providing a heterogeneous device-to-chip package.

Specifically, one or more layers of interconnect lines are formed in the interconnect chip 130.

As an example, interconnect pads 135 are formed on interconnect chip 130; the interconnect pad 135 is exposed at the first side 101 of the interposer 110.

Interconnect pads 135 are used to electrically bring out interconnect chip 130 to make electrical connection between interconnect chip 130 and external circuitry or other interconnect structures.

As one example, interconnect pad 135 is a bond pad. As one example, the material of interconnect pad 135 is metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium.

The first encapsulation layer 140 is used to implement the encapsulation of the conductive pillars 120 and the interconnect chips 130, and also to provide support for bonding the chip set 20 on the interposer 110.

The first encapsulation layer 140 exposes the conductive pillars 120 and the interconnect chips 130 in order to enable electrical connection between one or more device chips 200 in the chipset and the conductive pillars 120 and the interconnect chips 130.

As an embodiment, the material of the first encapsulation layer 140 is a Molding (Molding) material, for example: an epoxy resin. The epoxy resin has the advantages of low shrinkage, good cohesiveness, good corrosion resistance, excellent electrical property, low cost and the like. In other embodiments, other suitable packaging materials may be used for the first packaging layer.

In this embodiment, the package structure further includes: the third rewiring structure 150 is located on the second face 102 of the interposer, and the third rewiring structure 150 is electrically connected to the conductive stud 130.

The third rewiring structure 150 is used to make electrical connections between the second side 102 of the interposer 110 and external circuitry or other interconnect structures.

In particular, the third rewiring structure 150 may include one or more rewiring layers.

Specifically, the material of the third rewiring structure 150 is a conductive material. More specifically, the material of the third rewiring structure 150 is metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium.

In a specific implementation, the package structure further includes: a substrate (not shown) is bonded to the second side 102 of the interposer 110, and is electrically connected to the third rewiring structure 150.

Bonding between the third rewiring structure 150 and the substrate is achieved, and packaging integration and electrical integration between the packaging structure group and the substrate are achieved.

The third rewiring structure 150 is electrically connected to the substrate, thereby electrically connecting the conductive pillars 120 to the substrate, and correspondingly electrically connecting the chipset 20 to the substrate.

In this embodiment, the substrate is a PCB (Printed Circuit Board ).

In this embodiment, the package structure further includes: conductive bumps (not shown) are located between the third re-wiring structure 150 and the substrate, the conductive bumps electrically connecting the third re-wiring structure 150 and the substrate.

The conductive bumps are used to make electrical connection between the third rewiring structure 150 and the substrate.

In this embodiment, the conductive bump is a solder ball. As an example, the material of the solder balls includes tin.

Specifically, the solder ball is C4 (Controlled Collapse Chip Connection), has excellent electrical and thermal properties, and the I/O number can be high at the same solder ball pitch without being limited by the size of the third rewiring structure 150, and is also suitable for mass production, and greatly reduces the size and weight.

Specifically, in the present embodiment, the conductive bump and the substrate are soldered together.

In this embodiment, the package structure further includes: a second sealing layer (not shown) is located between the third re-wiring structure 150 and the substrate, and also fills in the gaps between adjacent conductive bumps. The second sealing layer is used for sealing the conductive bumps.

As an example, the second sealing layer is an Underfill (Underfill).

The chipset 20 is configured to bond with the interposer 110, thereby forming a corresponding package structure to implement a corresponding function.

In particular implementations, chipset 20 includes one or more device chips 200 and the types of the plurality of device chips 200 may be the same or different. Heterogeneous integration may be achieved when the types of device chips 200 are different.

As an example, the chipset 20 includes a first device chip 21 and a second device chip 22, and the first device chip 21 and the second device chip 22 are different types to implement different functions.

As an example, the first device chip 21 is a high-bandwidth memory storage (HBM) chip, which is advantageous in meeting the requirement for a higher information transfer speed by employing the HBM chip.

As an example, the second device chip 22 is a logic chip for performing logic control on the first device chip 21. Specifically, as an embodiment, the second device chip 22 may be a CPU chip, a GPU chip, or a SoC chip.

In this embodiment, the first surface 201 is a front surface of the chip, and the second surface 202 is a back surface of the chip.

In this embodiment, the front side of the chip is the side facing the device in the chip, and the back side of the chip is the side facing away from the device in the chip.

The second packaging layer 210 is used for packaging and integrating one or more device chips 200 in the chipset 20, and the second packaging layer 210 can also play roles of insulation, sealing and moisture resistance, so as to be beneficial to improving the reliability of the packaging structure.

As an embodiment, the material of the second packaging layer 210 is a Molding (Molding) material, for example: an epoxy resin. The epoxy resin has the advantages of low shrinkage, good cohesiveness, good corrosion resistance, excellent electrical property, low cost and the like. In other embodiments, the second encapsulation layer may be made of other suitable encapsulation materials.

The first rewiring structure 220 is used to make electrical connections between the chipset 20 and the interposer 110.

In this embodiment, the first rewiring structure 220 is directly disposed on the first surface 201, so that the first rewiring structure 220 with smaller pitch can be obtained, thereby improving the density of the first rewiring structure 220, which is correspondingly beneficial to improving the interconnection density and interconnection performance between the interposer 110 and the chipset 20.

Specifically, the first rewiring structure 220 is disposed on the second package layer 210 and the first surface 201, and compared with the scheme of disposing the rewiring structure on the conductive pillars, the first package layer and the interconnection chip, the second package layer 210 and the first surface 201 have higher top surface uniformity and top surface flatness, so that the patterning process for forming the first rewiring structure 220 is facilitated, the first rewiring structure 220 with smaller pitch and high density is facilitated to be formed, and the interconnection density and interconnection performance between the chipset 20 and the interposer 110 are improved.

In addition, the first rewiring structure 220 can also provide a process platform and a foundation for forming the micro bumps 230, so that the first rewiring structure 220 has high density and small space, and the micro bumps 230 with higher density are easy to obtain, and the communication speed between the chipset 20 and the interposer 110 is further improved.

In particular, the first rewiring structure 220 may include one or more rewiring layers.

Specifically, the material of the first rewiring structure 220 is a conductive material. More specifically, the material of the first rewiring structure 220 is metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium.

The micro bumps 230 are used to make electrical connection between the first rewiring structure 220 and the interposer 110, and also to increase the interconnection density between the chipset 20 and the interposer 110.

In this embodiment, the material of the micro bump 230 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the micro bump 230 is tin.

As an example, interconnect pads 135 are formed on interconnect chip 130; the interconnection pad 135 is exposed on the first surface of the interposer 110; the micro bumps 230 are electrically connected to the interconnect pads 135 of the interconnect die 130.

In a specific implementation, the package structure may further include: a second rewiring structure (not shown) is located between the first encapsulation layer 140 and the micro bump 230, between the conductive pillar 120 and the micro bump 230, and between the interconnect chip 130 and the micro bump 230.

The second rewiring structure is used to redistribute the interconnections between the chipset 20 and the interposer 110.

In particular, the second rewiring structure may comprise one or more rewiring layers.

Specifically, the material of the second rewiring structure is a conductive material. More specifically, the material of the second rewiring structure is metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium.

In this embodiment, the package structure further includes: the first sealing layer 240 is filled between the first face 101 of the interposer 110 and the chipset 20, and the first sealing layer 240 fills the gaps between the micro bumps 230 and seals the micro bumps 230. The first sealing layer 240 is used to seal the micro bump 230.

As one example, the first sealing layer 240 is an Underfill (Underfill).

The package structure of the embodiment may be formed by the package method provided by the present invention, or may be formed by other methods.

Correspondingly, the invention further provides a packaging method. Fig. 7 to 12 are schematic structural diagrams corresponding to each step in an embodiment of the packaging method of the present invention.

The following describes the packaging method of the present embodiment in detail with reference to the accompanying drawings.

Referring to fig. 7-9, an interposer 110 is formed, including opposing first and second faces 101, 102; the interposer 110 includes a first region (not shown) formed with a plurality of discrete conductive pillars 120 and a second region (not shown) between the first region formed with interconnect chips 130, the conductive pillars 120 and the interconnect chips 130 side-filled with a first encapsulation layer 140; interconnect die 130 and conductive pillars 120 are exposed at first face 101.

An Interposer 110 is used to make electrical connection between the chipset 20 and external circuitry.

Specifically, the interposer 110 has smaller line width and space, and supports heterogeneous integration, so that connection between different device chips is realized through the interposer 110, which is beneficial to reducing power consumption and increasing bandwidth.

The first side 101 of the interposer 110 is used to enable bonding with the chipset 20.

In this embodiment, the second surface 102 is used to achieve bonding with the substrate.

The first region is used to form conductive pillars and the second region is used to form an interconnect die.

The conductive posts 120 are used to make electrical connection between the chipset 20 and external circuitry.

In this embodiment, the material of the conductive pillars 120 is copper, i.e., the conductive pillars 120 are copper pillars. In other embodiments, the material of the conductive posts may also be other metallic materials.

Interconnect die 130 is used as a device-to-chip Bridge (Bridge) for interconnecting device dies and device dies, thereby providing a heterogeneous device-to-chip package.

Specifically, one or more layers of interconnect lines are formed in the interconnect chip 130.

As an example, interconnect pads 135 are formed on interconnect chip 130; the interconnect pad 135 is exposed at the first side 101 of the interposer 110.

Interconnect pads 135 are used to electrically bring out interconnect chip 130 to make electrical connection between interconnect chip 130 and external circuitry or other interconnect structures.

As one example, interconnect pad 135 is a bond pad. As one example, the material of interconnect pad 135 is metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium.

The first encapsulation layer 140 is used to implement the encapsulation of the conductive pillars 120 and the interconnect chips 130, and also to provide support for bonding the chip set 20 on the interposer 110.

The first encapsulation layer 140 exposes the conductive pillars 120 and the interconnect chips 130 in order to enable electrical connection between one or more device chips 200 in the chipset and the conductive pillars 120 and the interconnect chips 130.

As an embodiment, the material of the first encapsulation layer 140 is a Molding (Molding) material, for example: an epoxy resin. The epoxy resin has the advantages of low shrinkage, good cohesiveness, good corrosion resistance, excellent electrical property, low cost and the like. In other embodiments, other suitable packaging materials may be used for the first packaging layer.

As one example, the step of forming the interposer 110 includes:

As shown in fig. 7, a first carrier plate 111 is provided, the first carrier plate 111 including a first region and a second region located between the first regions; forming discrete conductive pillars 120 on the first carrier plate 111 of the first region; the interconnection chip 130 is attached to the first carrier 111 in the second region.

In an implementation, the interconnect chip 130 may be attached to the first carrier plate 111 after the conductive pillars 120 are formed, so as to prevent the process steps for forming the conductive pillars 120 from affecting the interconnect chip 130.

In other embodiments, the process sequence of forming the conductive pillars and attaching the interconnect die may be flexibly adjusted based on actual process requirements.

As shown in fig. 7, after the first carrier plate is provided and before the conductive pillars are formed and the interconnection chips are bonded, the step of forming the interposer 110 further includes: a third rewiring structure 150 is formed on the first carrier board 111.

Accordingly, in the step of forming the conductive pillars 120, the conductive pillars 120 are formed on the third re-wiring structure 150 and electrically connected with the third re-wiring structure 150; in the step of attaching the interconnect chip 130, the interconnect chip 130 is attached to the third rewiring structure 150.

The third rewiring structure 150 is used to make electrical connections between the second side 102 of the interposer 110 and external circuitry or other interconnect structures.

In particular, the third rewiring structure 150 may include one or more rewiring layers.

Specifically, the material of the third rewiring structure 150 is a conductive material. More specifically, the material of the third rewiring structure 150 is metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium.

As shown in fig. 8 to 9, after the conductive pillars 120 are formed and the interconnection chip 130 is attached, the first encapsulation layer 140 filled in the sides of the conductive pillars 120 and the interconnection chip 130 is formed on the first carrier 111, and the conductive pillars 120 and the interconnection chip 130 are exposed by the first encapsulation layer 140.

As an example, the step of forming the first encapsulation layer 140 includes: as shown in fig. 8, a first encapsulation material layer 145 covering the conductive pillars 120 and the interconnect chip 130 is formed on the first carrier 111; as shown in fig. 9, the first encapsulation material layer 145 higher than the conductive pillars 120 and the interconnect chip 130 is removed, exposing the conductive pillars 120 and the interconnect chip 130, and the remaining first encapsulation material layer 145 is used as the first encapsulation layer 140.

As an example, the first encapsulation material layer 145 is subjected to a polishing (polishing) process to remove the first encapsulation material layer 145 higher than the conductive pillars 120 and the interconnect chip 130.

In other embodiments, after forming the first encapsulation layer, the encapsulation method further comprises: a second rewiring structure is formed on the first encapsulation layer, and the second rewiring structure is electrically connected with the conductive post and the device chip.

Referring to fig. 10, a chip set 20 is provided, including one or more device chips 200, the plurality of device chips 200 being distributed in a direction parallel to the device chips 200, the device chips 200 including first and second surfaces 201 and 202 opposite to each other, a second encapsulation layer 210 being formed between adjacent device chips 200 and on a sidewall of the device chips 200, a first rewiring structure 220 being formed on the first surface 201, and an electrical connection between the first rewiring structure 220 and the device chips 200.

The chipset 20 is configured to bond with the interposer 110, thereby forming a corresponding package structure to implement a corresponding function.

In particular implementations, chipset 20 includes one or more device chips 200 and the types of the plurality of device chips 200 may be the same or different. Heterogeneous integration may be achieved when the types of device chips 200 are different.

As an example, the chipset 20 includes a first device chip 21 and a second device chip 22, and the first device chip 21 and the second device chip 22 are different types to implement different functions.

As an example, the first device chip 21 is a high-bandwidth memory storage (HBM) chip, which is advantageous in meeting the requirement for a higher information transfer speed by employing the HBM chip.

As an example, the second device chip 22 is a logic chip for performing logic control on the first device chip 21. Specifically, as an embodiment, the second device chip 22 may be a CPU chip, a GPU chip, or a SoC chip.

In this embodiment, the first surface 201 is a front surface of the chip, and the second surface 202 is a back surface of the chip.

In this embodiment, the front side of the chip is the side facing the device in the chip, and the back side of the chip is the side facing away from the device in the chip.

The second packaging layer 210 is used for packaging and integrating one or more device chips 200 in the chipset 20, and the second packaging layer 210 can also play roles of insulation, sealing and moisture resistance, so as to be beneficial to improving the reliability of the packaging structure.

As an embodiment, the material of the second packaging layer 210 is a Molding (Molding) material, for example: an epoxy resin. The epoxy resin has the advantages of low shrinkage, good cohesiveness, good corrosion resistance, excellent electrical property, low cost and the like. In other embodiments, the second encapsulation layer may be made of other suitable encapsulation materials.

The first rewiring structure 220 is used to make electrical connections between the chipset 20 and the interposer 110.

In this embodiment, the first rewiring structure 220 is directly disposed on the first surface 201, so that the first rewiring structure 220 with smaller pitch can be obtained, thereby improving the density of the first rewiring structure 220, which is correspondingly beneficial to improving the interconnection density and interconnection performance between the interposer 110 and the chipset 20.

Specifically, the first rewiring structure 220 is disposed on the second package layer 210 and the first surface 201, and compared with the scheme of disposing the rewiring structure on the conductive pillars, the first package layer and the interconnection chip, the second package layer 210 and the first surface 201 have higher top surface uniformity and top surface flatness, so that the patterning process for forming the first rewiring structure 220 is facilitated, the first rewiring structure 220 with smaller pitch and high density is facilitated to be formed, and the interconnection density and interconnection performance between the chipset 20 and the interposer 110 are improved.

In addition, the first rewiring structure 220 can also provide a process platform and a foundation for forming the micro bumps 230, so that the first rewiring structure 220 has high density and small space, and the micro bumps 230 with higher density are easy to obtain, and the communication speed between the chipset 20 and the interposer 110 is further improved.

In particular, the first rewiring structure 220 may include one or more rewiring layers.

Specifically, the material of the first rewiring structure 220 is a conductive material. More specifically, the material of the first rewiring structure 220 is metal, including: any one or more of copper, titanium, aluminum, gold, nickel, iron, tin, silver, zinc, or chromium.

As an example, the step of providing the chipset 20 includes: providing a second carrier plate (not shown); providing one or more device chips 200, the device chips 200 comprising a first surface 201 and a second surface 202 opposite to each other; attaching the second surface 202 of the one or more device chips 200 to the second carrier; forming a second encapsulation layer 210 on the second carrier plate at the side of the device chip 200, wherein the first surface 201 is exposed by the second encapsulation layer 210; forming a first rewiring structure 220 on the second encapsulation layer 210, the first rewiring structure 220 being electrically connected to the first surface 201; forming a plurality of micro bumps 230 on the first rewiring structure 220; and removing the second carrier plate.

The second carrier plate is used to provide a bearing and support for the chip set 20.

As an example, the step of forming the second encapsulation layer 210 includes: forming a second encapsulation material layer covering the side of the device chip 200 and the first surface 201 on the second carrier plate; the second encapsulation material layer above the first surface 201 is removed, exposing the first surface 201, and the remaining second encapsulation material layer is used as the second encapsulation layer 210.

In the present embodiment, in the step of providing the chipset 20, a plurality of micro bumps 230 are formed on the first rewiring structure 220, and the micro bumps 230 are used to achieve electrical connection between the first rewiring structure 220 and the interposer 110, and also to increase the interconnection density between the chipset 20 and the interposer 110.

In this embodiment, the material of the micro bump 230 includes one or more of tin, copper, aluminum, tungsten, cobalt, nickel, titanium, tantalum, titanium nitride, and tantalum nitride. As an example, the material of the micro bump 230 is tin.

Referring to fig. 11, bonding is performed between the chipset 20 and the interposer 110, the first face 101 of the interposer 110 is disposed opposite to the first face 201, micro bumps 230 are formed between the first rewiring structure 220 and the conductive pillars 120, and between the micro bumps 230 and the interconnection chip 130.

In this embodiment, the interposer 110 and the chipset 20 are formed separately, then the chipset 20 and the interposer 110 are bonded, the first surface 101 of the interposer 110 is opposite to the first surface 201, and the microbump 150 is electrically connected to the conductive pillar 120 and the interconnect chip 130, and compared with the method that after the interposer is formed, the rewiring structure is formed on the first surface of the interposer, then the device chip is bonded on the rewiring structure and the second package layer is formed, the rewiring structure electrically connected to the conductive pillar and the interconnect chip is not required to be formed on the first package layer, the first rewiring structure 220 can be formed on the first surface 201, and the microbump 230 is formed on the first rewiring structure 220, and the first rewiring structure 220 with smaller pitch can be obtained by forming the first rewiring structure 220 on the first surface 201, so that the density of the first rewiring structure 220 is improved, and the interconnection density and the interconnection performance between the interposer 110 and the chipset 20 are improved correspondingly.

In this embodiment, the step of bonding the chipset 20 and the interposer 110 includes: forming a plurality of micro bumps on the first rewiring structure 220; the microbumps are bonded to the first face 101 of the interposer 110.

In the present embodiment, the first rewiring structure 220 is formed with high density and small pitch, and the micro-bumps with smaller pitch and higher density are advantageously obtained by forming the plurality of micro-bumps 230 on the first rewiring structure 220.

More specifically, in the present embodiment, in the step of providing the chipset 20, a plurality of micro bumps 230 are formed on the first rewiring structure 220.

In this embodiment, in the step of bonding between the chipset 20 and the interposer 110, the micro bump 150 is in contact with the second rewiring structure.

In this embodiment, interconnect pads 135 are formed on interconnect die 130; the interconnection pad is exposed on the first face 101 of the interposer 110; in the step of bonding between the chipset and the interposer, the micro bumps are electrically connected to the interconnect pads of the interconnect chip 130.

It should be noted that, in this embodiment, the packaging method further includes: after bonding between the chip set 20 and the interposer 110, a first sealing layer 240 is filled between the first face 101 of the interposer 110 and the chip set 20, the first sealing layer 240 fills the gaps between the micro bumps 230 and seals the micro bumps 230. The first sealing layer 240 is used to seal the micro bump 230.

As one example, the first sealing layer 240 is an Underfill (Underfill).

It should be noted that, in this embodiment, after the chipset 20 and the interposer 110 are bonded, the packaging method further includes: the first carrier 111 is removed. The first carrier plate 111 is removed in order to achieve an electrical connection between the second side 102 of the interposer and an external circuit or other structure.

In a specific implementation, the packaging method further includes: after the first carrier 111 is removed, the second surface 102 of the interposer 110 is bonded to a substrate (not shown), and the third rewiring structure 150 is disposed opposite to and electrically connected to the substrate.

Bonding between the third rewiring structure 150 and the substrate is achieved, and packaging integration and electrical integration between the packaging structure group and the substrate are achieved.

The third rewiring structure 150 is electrically connected to the substrate, thereby electrically connecting the conductive pillars 120 to the substrate, and correspondingly electrically connecting the chipset 20 to the substrate.

In this embodiment, the substrate is a PCB (Printed Circuit Board ).

After removing the first carrier 111 and before bonding the second face 102 of the interposer 110 to the substrate, forming conductive bumps on the third rewiring structure 150; in the step of bonding the chipset and the interposer to the substrate, the conductive bumps are bonded to and electrically connected with the substrate.

The conductive bumps are used to make electrical connection between the third rewiring structure 150 and the substrate.

In this embodiment, the conductive bump is a solder ball. As an example, the material of the solder balls includes tin.

Specifically, the solder ball is C4 (Controlled Collapse Chip Connection), has excellent electrical and thermal properties, and the I/O number can be high at the same solder ball pitch without being limited by the size of the third rewiring structure 150, and is also suitable for mass production, and greatly reduces the size and weight.

Specifically, in the present embodiment, the conductive bump and the substrate are soldered together.

In this embodiment, the packaging method further includes: a second sealing layer (not shown) is filled between the third re-wiring structure 150 and the substrate, and the second sealing layer is also filled in the gaps between adjacent conductive bumps. The second sealing layer is used for sealing the conductive bumps.

As an example, the second sealing layer is an Underfill (Underfill).

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A package structure, comprising:

The adapter plate comprises a first surface and a second surface which are opposite; the interposer includes a first region formed with a plurality of discrete conductive pillars and a second region between the first region formed with an interconnection chip, the conductive pillars and the interconnection chip side being filled with a first encapsulation layer; the interconnection chip and the conductive posts are exposed out of the first surface;

A chip set including one or more device chips, the device chips being distributed in a direction parallel to the device chips, the device chips including first and second surfaces opposite to each other, second package layers being formed between adjacent device chips and on sidewalls of the device chips, a first rewiring structure being formed on the first surface, the first rewiring structure being electrically connected to the device chips; the first surface of the chipset is bonded on the first surface of the adapter plate;

and the micro-bump is positioned between the first rewiring structure and the conductive column and between the micro-bump and the interconnection chip, and is electrically connected with the conductive column and the interconnection chip.

2. The package structure of claim 1, wherein the first surface is a front side of a chip and the second surface is a back side of the chip.

3. The package structure of claim 1, wherein the package structure further comprises: and a second rewiring structure positioned between the first packaging layer and the micro-bump, between the conductive post and the micro-bump, and between the interconnection chip and the micro-bump.

4. The package structure of claim 1, wherein the package structure further comprises: and the third rewiring structure is positioned on the second surface of the adapter plate and is electrically connected with the conductive post.

5. The package structure of claim 4, wherein the package structure further comprises: and the substrate is bonded on the second surface of the adapter plate and is electrically connected with the third rewiring structure.

6. The package structure of claim 5, wherein the package structure further comprises: and the conductive bump is positioned between the third rewiring structure and the substrate and electrically connects the third rewiring structure and the substrate.

7. The package structure of claim 1, wherein the package structure further comprises: and the sealing layer is filled between the first surface of the adapter plate and the chipset, fills gaps among the micro bumps and seals the micro bumps.

8. The package structure of claim 1, wherein the interconnect die has interconnect pads formed thereon; the interconnection pad is exposed on the first surface of the adapter plate; the micro-bumps are electrically connected with the interconnection pads of the interconnection chip.

9. The package structure of claim 1, wherein the first rewiring structure comprises one or more rewiring layers.

10. A method of packaging, comprising:

forming an adapter plate comprising a first surface and a second surface which are opposite; the interposer includes a first region and a second region between the first region, the first region is formed with a plurality of discrete conductive pillars, the second region is formed with an interconnection chip, and the conductive pillars and the interconnection chip side are filled with a first encapsulation layer; the interconnection chip and the conductive posts are exposed out of the first surface;

Providing a chip set comprising one or more device chips, wherein the device chips are distributed along a direction parallel to the device chips, the device chips comprise a first surface and a second surface which are opposite to each other, a second packaging layer is formed between the adjacent device chips and on the side wall of the device chips, a first rewiring structure is formed on the first surface, and the first rewiring structure is electrically connected with the device chips;

Bonding the chipset and the adapter plate, wherein the first surface of the adapter plate is opposite to the first surface, micro-bumps are formed between the first rewiring structure and the conductive columns and between the first rewiring structure and the interconnection chip, and the micro-bumps are electrically connected with the conductive columns and the interconnection chip.

11. The packaging method of claim 10, wherein the step of forming the interposer includes: providing a first carrier plate, wherein the first carrier plate comprises a first area and a second area positioned between the first areas; forming discrete conductive pillars on a first carrier plate of the first region; attaching an interconnection chip on the first carrier plate of the second area;

After forming the conductive columns and attaching the interconnection chips, forming first packaging layers filled in the side parts of the conductive columns and the side parts of the interconnection chips on the first carrier, wherein the first packaging layers expose the conductive columns and the interconnection chips;

After bonding the chipset and the interposer, the packaging method further includes: and removing the first carrier plate.

12. The packaging method of claim 11, wherein after forming the first packaging layer, the packaging method further comprises: forming a second rewiring structure on the first packaging layer, wherein the second rewiring structure is electrically connected with the conductive column and the device chip;

in the step of bonding between the chipset and the interposer, the micro bump is contacted with a second rewiring structure.

13. The packaging method of claim 11, wherein after providing the first carrier and before forming the conductive pillars and attaching the interconnect die, the step of forming the interposer further comprises: forming a third rewiring structure on the first carrier plate; in the step of forming the conductive pillars, the conductive pillars are formed on and electrically connected with the third rewiring structure; in the step of attaching the interconnect chip, the interconnect chip is attached to the third rewiring structure.

14. The packaging method of claim 13, wherein the packaging method further comprises: after the first carrier plate is removed, the second surface of the adapter plate is bonded on the substrate, and the third rewiring structure is arranged opposite to and electrically connected with the substrate.

15. The packaging method of claim 14, wherein the packaging method further comprises: after the first carrier plate is removed and before the second surface of the adapter plate is bonded on the substrate, forming a conductive bump on the third rewiring structure; in the step of bonding the chipset and the interposer to the substrate, the conductive bumps are bonded to and electrically connected with the substrate.

16. The packaging method of claim 10, wherein the step of bonding between the chipset and the interposer includes: forming a plurality of microbumps on the first rewiring structure; bonding the micro-bump with the first surface of the adapter plate.

17. The packaging method of claim 16, wherein in the step of providing a chipset, the micro bumps are formed; the step of providing a chipset comprises: providing a second carrier plate; providing one or more device chips, wherein the device chips comprise a first surface and a second surface which are opposite to each other, and attaching the second surface of the one or more device chips to the second carrier plate; forming a second packaging layer on a second carrier plate at the side part of the device chip, wherein the first surface of the second packaging layer is exposed; forming a first rewiring structure on the second packaging layer, wherein the first rewiring structure is electrically connected with the first surface; forming a plurality of microbumps on the first rewiring structure; and removing the second carrier plate.

18. The packaging method of claim 17, wherein the step of forming a second packaging layer comprises: forming a packaging material layer covering the side part of the device chip and the first surface on the second carrier plate; and removing the packaging material layer higher than the first surface, exposing the first surface, and using the rest packaging material layer as the second packaging layer.

19. The packaging method of claim 10, wherein the packaging method further comprises: after bonding between the chip set and the interposer, a sealing layer is filled between the first face of the interposer and the chip set, the sealing layer filling gaps between the microbumps and sealing the microbumps.

20. The packaging method of claim 10, wherein the interconnect die has interconnect pads formed thereon; the interconnection pad is exposed on the first surface of the adapter plate; in the step of bonding between the chip set and the interposer, the micro bumps are electrically connected to the interconnect pads of the interconnect chip.