CN219267651U

CN219267651U - System integration 2.5D structure

Info

Publication number: CN219267651U
Application number: CN202223536766.0U
Authority: CN
Inventors: 陈彦亨; 林正忠
Original assignee: Shenghejing Micro Semiconductor Jiangyin Co Ltd
Current assignee: SJ Semiconductor Jiangyin Corp
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2023-06-27
Anticipated expiration: 2032-12-29

Abstract

The utility model provides a system integrated 2.5D structure, wherein a system integrated chip is a system stacked 3D packaging structure, and system chips or wafers of different generations are integrated into one packaging chip, so that the functional density is greatly improved, and the size of a chip is optimized; the system integrated chip is used for integrating the system into a 2.5D structure, so that the same packaging size can realize the cooperative work of more functional systems, a plurality of packaging structures are not required to be prepared respectively, the production process cost is saved, the chip performance is improved, the economic benefit is improved, and the system integrated chip has strong integration, high flexibility and wide compatibility; the system integrated chip is bonded with the second metal pad through the first metal pad, so that the passing path of electric connection is reduced, parasitic capacitance in the packaging structure is reduced, and the signal transmission efficiency is improved; the number of metal pads in a unit area can be increased by hybrid bonding, so that the data throughput and the integration level are improved; the first metal pad and the second metal pad are different in size, so that the problem of chip mounting precision is solved, and the production efficiency is improved.

Description

System integration 2.5D structure

Technical Field

The utility model relates to the field of semiconductor packaging, in particular to a system integration 2.5D structure.

Background

With the advancement of technology, since end users want smaller, faster, more energy-saving and higher performance devices, miniaturization and multifunctionality of electronic terminal products have become a trend of industry development, and how to integrate and package a plurality of different kinds of high-density chips together to form a system or subsystem with powerful functions and small volume and power consumption has become a challenge in advanced packaging field of semiconductor chips.

The system-in-package technology is used as an emerging heterogeneous integration technology and becomes a packaging form of more and more chips, and integrates various functional chips and components into a package body, so that a basically complete function is realized, and the system-in-package technology has the advantages of short development period, more functions, lower power consumption, better performance, smaller volume and the like. Along with the increasingly higher requirements on packaging components and functions, the application provides the ultra-high integration system level package, which can integrate SOCs of different generations in a packaging structure, realize the cooperative work of a multifunctional system, improve the functional density, and has the advantages of high compatibility, high integration level, high flexibility and the like.

Disclosure of Invention

In view of the above drawbacks of the prior art, the present utility model is directed to a system-in-2.5D architecture, which is used for solving the problems of limited functions, low integration level, difficult compatibility of chips of different generations, and the like in the prior art.

To achieve the above and other related objects, the present utility model provides a system integrated 2.5D structure, which has the following advantages: the system integrated chip is a system stacked 3D packaging structure, system chips or wafers of different generations are integrated in the same packaging chip in a hybrid bonding mode, and low-generation system chips are stacked on high-generation system chips according to the different size characteristics of the system chips or wafers of different generations, so that more functions can be realized in the packaging structure of the same size, the functional density of the packaging structure is greatly improved, and the size of a wafer is optimized; the system integrated chip is applied to a 2.5D packaging structure to form a system integrated 2.5D structure, and various electronic chips and components such as an HBM/DDR/flash memory/transistor/filter/passive device integrated chip are integrated, so that the same packaging size can realize the cooperative work of more functional systems, a plurality of packaging structures do not need to be prepared respectively, the connection of the packaging structures does not need to be additionally performed, the production process cost is saved, the chip performance of the system integrated 2.5D structure is improved, the economic benefit of the system integrated 2.5D structure is improved, and the system integrated chip has the advantages of strong integration, high flexibility, wide compatibility and the like.

When a first signal interface of a first chip in the system integrated chip is electrically connected with a corresponding interface of a system wafer, the first metal pad and the second metal pad are aligned to directly electrically connect, so that the passing path of the electrical connection is reduced, the parasitic capacitance in the packaging structure is reduced, and the signal transmission efficiency is improved; the space between the first metal pads and the space between the second metal pads can be expanded to be smaller than 5 mu m, so that the number of the metal pads can be increased in a unit area, the number of data channels is increased, the data throughput is improved, and the integration level is improved; the first metal pad and the second metal pad do not need the same size and width, so that the problem of mounting precision of the hybrid bonding chip can be solved, and the production efficiency is improved.

Drawings

Fig. 1a to fig. 4 are schematic structural diagrams corresponding to each process step in the process for preparing a system-on-chip according to an embodiment of the present utility model.

Fig. 5 to fig. 7 are schematic structural diagrams corresponding to each process step in the system integrated 2.5D structure preparation method according to the embodiment of the present utility model.

Description of the reference numerals

1. First wafer

11. First chip

2. System wafer

3. A first dielectric layer

4. First metal pad

5. A second dielectric layer

6. Second metal pad

7. Metal column

8. Plastic seal layer

9. Rewiring layer

91. Wiring dielectric layer

92. Wiring metal layer

10. External connection interface

100. System integrated chip

110. Interposer substrate

120 TSV conductive column

131. First wiring dielectric layer

132. First wiring metal layer

140. Second chip

150. First plastic sealing layer

151. Underfill

161. Second wiring dielectric layer

162. Second wiring metal layer

170. First external connection interface

Detailed Description

Other advantages and effects of the present utility model will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present utility model with reference to specific examples. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model.

As described in detail in the embodiments of the present utility model, the cross-sectional view of the device structure is not partially enlarged to a general scale for convenience of explanation, and the schematic drawings are only examples, which should not limit the scope of the present utility model. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present utility model by way of illustration, and only the components related to the present utility model are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complex.

As shown in fig. 1a to fig. 7, the present utility model provides a method for preparing a system-integrated 2.5D structure, and the structure and beneficial effects of the system-integrated 2.5D structure are described in detail by using the method for preparing a system-integrated 2.5D structure, where the method comprises the following steps.

As shown in fig. 1a to 1c, a first wafer 1 is provided, a first dielectric layer 3 and a first metal pad 4 located in the first dielectric layer 3 are formed on the first wafer 1, the first metal pad 4 is electrically connected with the first wafer 1, and a first chip 11 is formed by encapsulation dicing.

Specifically, as shown in fig. 1a, a first wafer 1 is provided, where the first wafer 1 is a manufactured wafer having a complete internal structure and an external signal interface, such as various memory wafers capable of implementing a memory function, such as a programmable logic device wafer capable of implementing a programming function, such as a system wafer for integrated information processing, and the above examples are non-limiting examples, and are specifically selected according to practical requirements. In this embodiment, the first wafer 1 is a low-generation system wafer, and is a small-size system wafer. A first dielectric layer 3 is deposited on the first wafer 1, where the first dielectric layer 3 is used as an intermetallic dielectric layer and includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride or other low-K inorganic dielectric layers, the first dielectric layer 3 also includes an organic dielectric layer formed by polymers such as benzocyclobutene BCB and polyimide PI, and the first dielectric layer 3 may also be a combination dielectric layer of an inorganic dielectric layer and an organic dielectric layer, which is specifically set according to actual requirements, and is not excessively limited herein. The first dielectric layer 3 is patterned to define metal pad contact holes, and the metal pad contacts Kong Xianlou the first signal interface of the first wafer 1. And depositing a barrier layer and a metal cushion layer in the metal cushion contact hole, wherein the material for forming the metal cushion layer is preferably copper, and can also be nickel, tin and other suitable metals or metal alloys. After the metal pad contact hole is filled, a metal layer with a certain thickness is deposited on the first dielectric layer 3, and then the surface metal layer is removed by a planarization process such as chemical mechanical polishing, etc., as shown in fig. 1b, to obtain a flat first dielectric layer 3 and a first metal pad 4 in the first dielectric layer 3. The first dielectric layer 3 and the first metal pad 4 can rearrange the first signal interface on the front surface of the first wafer 1, so that the first signal interface is electrically connected to the first metal pad 4, wherein the arrangement of the first metal pad 4 is different from the arrangement of the first signal interface. The first wafer 1 is subjected to plastic packaging, and then diced to form individual first chips 11.

As shown in fig. 2a to 2b, a system wafer 2 is provided, a second dielectric layer 5 and a second metal pad 6 located in the second dielectric layer 5 are formed on the system wafer 2, and the second metal pad 6 is electrically connected to the system wafer 2.

Specifically, as shown in fig. 2a, a system wafer 2 is provided, where the system wafer 2 is a high-generation system wafer, and is a large-size system wafer. The surface of the system wafer 2 is provided with a second signal interface. As shown in fig. 2b, a second dielectric layer 5 and a second metal pad 6 located in the second dielectric layer 5 are formed on the surface of the system wafer 2. The second dielectric layer 5 and the second metal pad 6 can rearrange the second signal interface on the front surface of the system wafer 2, so that the second signal interface is electrically connected to the second metal pad 6, wherein the arrangement of the second metal pad 6 is different from the arrangement of the second signal interface. The method for forming the second dielectric layer 5 and the second metal pad 6 can be referred to the method for forming the first dielectric layer 3 and the first metal pad 4, and will not be described herein.

As shown in fig. 3, a metal pillar 7 is formed on the second metal pad 6, the first chip 11 is bonded to the system wafer 2 by hybrid bonding, a plastic layer 8 is formed, and the plastic layer 8 encapsulates the first chip 11, the metal pillar 7 and the second dielectric layer 5 and exposes the surface of the metal pillar 7.

Specifically, in this embodiment, metal pillars 7 are formed on the second metal pads 6 on both sides, and the metal pillars 7 are electrically connected to the second signal interface of the system wafer 2 through the second metal pads 6 to provide power transmission and signal transmission; this allows more space on the system wafer 2 to be freed up for integration of the first chip 11, improving integration and optimizing die size. However, the location of the metal posts 7 is not limited thereto, and the metal posts 7 may be located on the second metal pad 6 on one side, or may be located in other suitable locations such as the middle of the second metal pad 6, according to actual layout requirements.

The metal pillars 7 include, but are not limited to, copper pillars, titanium pillars, and the forming methods include, but are not limited to, PVD, CVD, sputtering, electroplating, and electroless plating. In an embodiment, a PVD process may be first used to form a metal copper layer, then a photoresist is formed on the metal copper layer, the photoresist is patterned and etched, and finally the metal pillars 7 are formed on the second metal pads 6 on both sides, and the photoresist is removed.

And bonding the first chip 11 to the system wafer 2 by a hybrid bonding mode of correspondingly bonding the first metal pad 4 and the second metal pad 6 and correspondingly bonding the first dielectric layer 3 and the second dielectric layer 5.

Specifically, hybrid bonding (Hybrid bonding) combines metal-metal bonding and medium-medium bonding, and the first signal interface of the first chip 11 is directly and electrically connected to the corresponding interface of the system wafer 2 through the bonding between the first metal pad 4 and the second metal pad 6, so that the path of electrical connection can be reduced, the parasitic capacitance in the package structure can be reduced, and the signal transmission efficiency between the first chip 11 and the system wafer 2 can be improved; and when the vertical metal interconnection is obtained, the physical and mechanical properties between the stacked chips are enhanced by adopting the auxiliary effect of medium adhesion, so that the comprehensive performance of the stacked chips is improved. In detail, the hybrid bonding technology is different from the conventional bump bonding technology in that the hybrid bonding technology has no protruding bumps and the surface of the dielectric layer is very smooth. Attaching two chips together at room temperature, raising the temperature and annealing them, copper expanding and firmly bonding together, thereby forming an electrical connection with high current carrying capacity and low interconnect length, reducing power consumption per interconnect channel, achieving low time delay; besides bonding metal together, the dielectric layers are bonded together, gaps are not formed between the dielectric layers, filling glue is not needed, and the heat dissipation performance and the bonding strength are better. In this embodiment, the number of the first chips 11 is shown as 2, but the number of the first chips 11 may be 1, 3 or more than 3 according to the requirements of the actual functional system. Through the hybrid bonding of the first chip 11 and the system wafer 2, the system chips or wafers of different generations are integrated in the same packaging chip, the size characteristics of the chips of different generations, such as large size of the chips of the higher generation and small size of the chips of the lower generation, are effectively utilized, the system chips of different generations are stacked, the system chips of the lower generation are stacked on the system chips of the higher generation, more functions can be obtained by realizing the same packaging size, the functional density of the packaging structure is greatly improved, the size of the chip is optimized, the flexibility is high, and the compatibility is wide.

The plastic layer 8 material includes, but is not limited to, epoxy-based resins, liquid thermosetting epoxy resins, plastic molding compounds, and the method of forming the plastic layer 8 includes compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable methods. After forming the molding layer 8, planarization treatment, including but not limited to grinding, is performed so that the surface of the metal posts 7 is flush with the surface of the molding layer 8.

As an example, the first metal pad 4 is not the same size as the second metal pad 6.

Specifically, as shown in fig. 4, in this embodiment, the first metal pad 4 and the second metal pad 6 are completely aligned when bonded, and have the same size. However, the dimensions of the first metal pad 4 and the second metal pad 6 do not need to be the same dimension width, but the first metal pad 4 may be large and the second metal pad 6 may be small, according to actual production requirements; the opposite can also be the second metal pad 6 size is big, the first metal pad 4 size is little, so can overcome the chip mounting precision problem when mixing the bonding, reduce the bonding degree of difficulty, improve production efficiency.

As an example, the first metal pads 4 have a pitch of less than 5 μm and the second metal pads 6 have a pitch of less than 5 μm.

Specifically, in this embodiment, the distance between the first metal pads 4 and the distance between the second metal pads 6 break through by 10 μm, and can be reduced to less than 5 μm, so that the number of metal pads can be increased in a unit area, and the number of data channels can be further increased, thereby improving data throughput, functional density and integration level. In one embodiment, the first metal pads 4 are spaced apart by 3 μm, and the second metal pads 6 are spaced apart by 3 μm. In another embodiment, the first metal pads 4 are spaced apart by 1 μm, and the second metal pads 6 are spaced apart by 1 μm.

As shown in fig. 4, a re-wiring layer 9 is formed on the surface of the plastic sealing layer 8, the re-wiring layer 9 includes a wiring dielectric layer 91 and a wiring metal layer 92 that is located in the wiring dielectric layer 91 and is electrically connected to the metal pillar 7, and an external interface 10 is formed on the surface of the wiring metal layer 92 away from the metal pillar 7, so as to form the system-in-chip 100.

Specifically, a wiring dielectric layer 91 is formed on the surface of the plastic sealing layer 8, and the material of the wiring dielectric layer 91 includes one of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass and fluorine-containing glass. Patterning the wiring dielectric layer 91 to expose the metal posts 7, forming a wiring metal layer 92 in the wiring dielectric layer 91, wherein the wiring metal layer 92 is electrically connected with the metal posts 7. The material of the wiring metal layer 92 includes one or a combination of copper, aluminum, titanium, and nickel, the method of forming the wiring metal layer 92 includes, but is not limited to, PVD, CVD, sputtering, electroplating, and electroless plating, and the wiring metal layer 92 includes a single layer or a multi-layer structure. In the present utility model, all wiring metal layers include a single-layer or multi-layer structure unless otherwise specified.

An external interface 10 is formed on the surface of the wiring metal layer 92 away from the metal pillar 7, and the external interface 10 includes solder balls and pads. In this embodiment, the external interface is a solder ball, and the material of the solder ball includes but is not limited to copper, nickel, and tin.

The metal posts 7 are used to directly communicate with the top of the rewiring layer 9 to power the system wafer 2 and to conduct electrical signal transmission. The metal pillars 7 are larger in size, lower in resistance, and provide more stable power transfer and lower time delay than conventional through silicon vias.

After the external connection interface 10 is formed, in order to further reduce the height of the package structure, polishing or other methods may be used to thin the substrate thickness of the system wafer 2 and planarize the substrate, and then package the system integrated chip 100. The system-in-chip 100 is applied to a 2.5D package structure to form a system-in-2.5D structure. As a non-limiting example, a method for preparing the system-on-chip 100 applied to the 2.5D package structure is described below, and other methods may be used according to actual production requirements, which is not limited herein.

As shown in fig. 5, an interposer substrate 110 is provided, and TSV conductive pillars 120 penetrating through the interposer substrate 110 are formed in the interposer substrate 110, wherein the interposer substrate 110 has a first surface and a second surface disposed opposite to each other.

Specifically, the interposer substrate 110 includes a glass substrate, a semiconductor substrate, a polymer substrate, a ceramic substrate, etc., and is used for supporting and isolating the chip on the first surface and the external signal interface on the second surface. In this embodiment, the interposer substrate 110 is a silicon substrate. A TSV hole penetrating the interposer substrate 110 is formed in the interposer substrate 110 by laser drilling, mechanical drilling, deep reactive ion etching, photo-assisted electrochemical etching, or the like. The TSV holes are filled with a conductive material, such as one or a combination of copper, aluminum, gold, silver, nickel, titanium, tantalum, etc., to form TSV conductive pillars 120, and the filling method includes, but is not limited to, electroplating, electroless plating, and one or a combination of layers Ta, taN, ti, tiN may be deposited as a diffusion barrier or adhesion layer in order to prevent the conductive material from diffusing into the interposer substrate 110.

As shown in fig. 6, a first re-wiring layer is formed on the first surface, the first re-wiring layer includes a first wiring dielectric layer 131 and a first wiring metal layer 132 disposed in the first wiring dielectric layer 131 and electrically connected to the TSV conductive post 120, a second chip 140 and the system integrated chip 100 are provided, and the second chip 140 and the system integrated chip 100 are flip-chip mounted on the first wiring metal layer 132 at intervals.

Specifically, a first wiring dielectric layer 131 is deposited on the first surface, the first wiring dielectric layer 131 is patterned, and the TSV conductive post 120 is exposed. A barrier layer and a first wiring metal layer 132 are deposited on the patterned first wiring dielectric layer 131, the first wiring metal layer 132 is electrically connected to the TSV conductive post 120, and the electrical signal interface of the TSV conductive post 120 is electrically connected to the first wiring metal layer 132 via the first re-wiring layer.

The second chip 140 includes various chips and devices such as HBM (high bandwidth memory), DDR (double rate synchronous dynamic random access memory), flash memory, transistors, filters, etc., and the second chip 140 further includes passive device integrated chips such as capacitors, resistors, inductors, etc. In the present embodiment, the number of the second chips 140 and the system-in-integrated chips 100 is 1, but according to practical needs, the number of the second chips 140 and the system-in-integrated chips 100 may be greater than or equal to 2, such as 3, 4, 5, etc., which is not limited herein.

As an example, after the flip-chip process, the method further includes a step of filling an underfill in a gap between the second chip 140 and the first wiring dielectric layer 131 and a gap between the system-in-chip 100 and the first wiring dielectric layer 131.

Specifically, after the flip-chip process, the gap between the second chip 140 and the first wiring dielectric layer 131 and the gap between the system integrated chip 100 and the first wiring dielectric layer 131 may be filled with the underfill 151, so as to increase the anti-dropping performance and the bonding strength of the package structure, and improve the package quality. The underfill 151 comprises a relatively small particle filler material such as epoxy, and the filling method includes, but is not limited to, one or more of capillary filling, form filling, dispensing, and spin coating.

As an example, a first plastic sealing layer 150 is further provided, where the first plastic sealing layer 150 encapsulates the second chip 140, the system integrated chip 100, and the first wiring dielectric layer 131. After the first plastic sealing layer 150 is formed, the surface of the first plastic sealing layer 150 may be thinned and planarized according to actual needs, which is not limited herein.

As shown in fig. 7, a second re-wiring layer is formed on the second surface, the second re-wiring layer includes a second wiring dielectric layer 161 and a second wiring metal layer 162 located in the second wiring dielectric layer 161 and electrically connected to the TSV conductive post 120, and a first external interface 170 is formed on a surface of the second wiring metal layer 162 away from the TSV conductive post 120.

Likewise, the second wiring metal layer 162 is electrically connected to the TSV conductive post 120, and an electrical signal interface of the TSV conductive post 120 is electrically connected to the second wiring metal layer 162 via the second re-wiring layer. The first external interface 170 includes solder balls and pads, and in this embodiment, the first external interface 170 is a solder ball.

To sum up, as shown in fig. 7, the system integration 2.5D structure includes:

the interposer 110 includes a first surface and a second surface disposed opposite to each other;

a TSV conductive post 120 penetrating through the interposer substrate 110;

a first re-wiring layer on the first surface, including a first wiring dielectric layer 131 and a first wiring metal layer 132 in the first wiring dielectric layer 131 electrically connected to the TSV conductive post 120;

the system-in-chip 100 is flip-chip mounted on the surface of the first wiring metal layer 132, and is a system-on-3D package structure at least comprising a system wafer 2 and a first chip 11 mixed-bonded on the system wafer 2;

the second chip 140 is flip-chip mounted on the surface of the first wiring metal layer 132 and is spaced apart from the system-in-package chip 100;

a second re-wiring layer located on the second surface, including a second wiring dielectric layer 161 and a second wiring metal layer 162 located in the second wiring dielectric layer 161 and electrically connected to the TSV conductive post 120;

a first external interface 170 located on a surface of the second wiring metal layer 162 away from the TSV conductive post 120;

as an example, the first chip 11 is a system chip and is different from the system wafer 2.

As an example, as shown in fig. 4, the system-on-chip 100 includes:

a system wafer 2;

a second dielectric layer 5 and a second metal pad 6 formed on the system wafer 2, the second metal pad 6 being located in the second dielectric layer 5 and electrically connected to the system wafer 2;

a metal pillar 7 formed on the second metal pad 6 and electrically connected to the second metal pad 6;

a first chip 11;

a first dielectric layer 3 and a first metal pad 4 formed on the first chip 11, wherein the first metal pad 4 is located in the first dielectric layer 3 and is electrically connected with the first chip 11, the first dielectric layer 3 and the second dielectric layer 5 are correspondingly bonded, and the first metal pad 4 and the second metal pad 6 are correspondingly bonded;

a plastic layer 8, wherein the plastic layer 8 encapsulates the first chip 11, the metal pillars 7 and the second dielectric layer 5, and exposes the surfaces of the metal pillars 7;

a re-wiring layer 9 formed on the surface of the molding layer 8, wherein the re-wiring layer 9 includes a wiring dielectric layer 91 and a wiring metal layer 92 which is located in the wiring dielectric layer 91 and is electrically connected with the metal post 7;

and an external connection interface 10 formed on the surface of the wiring metal layer 92 away from the metal pillar 7.

As an example, the metal posts 7 are located on the second metal pads 6 at the sides.

As an example, the front surface of the first wafer 1 has a first signal interface, the first signal interface is electrically connected to the first metal pad 4, and the arrangement of the first metal pad 4 is different from that of the first signal interface; the front surface of the system wafer 2 is provided with a second signal interface, the second signal interface is electrically connected with the second metal pad 6, and the arrangement of the second metal pad 6 is different from that of the second signal interface.

As an example, the gap between the second chip 140 and the first wiring dielectric layer 131 is filled with an underfill 151, the gap between the system-in-package chip 100 and the first wiring dielectric layer 131 is filled with an underfill 151,

as an example, a first plastic sealing layer 150 is provided, and the first plastic sealing layer 150 encapsulates the second chip 140, the system integrated chip 100, and the first wiring dielectric layer 131.

As an example, the substrate of the system wafer 2 is subjected to thinning and planarization processes.

In summary, the utility model provides a system integrated 2.5D structure, which has the following beneficial effects: the system integrated chip is a system stacked 3D packaging structure, system chips or wafers of different generations are integrated in the same packaging chip in a hybrid bonding mode, and low-generation system chips are stacked on high-generation system chips according to the different size characteristics of the system chips or wafers of different generations, so that more functions can be realized in the packaging structure of the same size, the functional density of the packaging structure is greatly improved, and the size of a wafer is optimized; the system integrated chip is applied to a 2.5D packaging structure to form a system integrated 2.5D structure, and various electronic chips and components such as an HBM/DDR/flash memory/transistor/filter/passive device integrated chip are integrated, so that the same packaging size can realize the cooperative work of more functional systems, a plurality of packaging structures do not need to be prepared respectively, the connection of the packaging structures does not need to be additionally performed, the production process cost is saved, the chip performance of the system integrated 2.5D structure is improved, the economic benefit of the system integrated 2.5D structure is improved, and the system integrated chip has the advantages of strong integration, high flexibility, wide compatibility and the like.

The above embodiments are merely illustrative of the principles of the present utility model and its effectiveness, and are not intended to limit the utility model. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the utility model. Accordingly, it is intended that all equivalent modifications and variations of the utility model be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A system-integrated 2.5D architecture, the system-integrated 2.5D architecture comprising at least:

the intermediate substrate comprises a first surface and a second surface which are oppositely arranged;

TSV conductive posts penetrating through the interposer substrate;

a first re-wiring layer on the first surface, including a first wiring dielectric layer and a first wiring metal layer in the first wiring dielectric layer electrically connected to the TSV conductive post;

the system integrated chip is flipped on the surface of the first wiring metal layer and is a system stacked 3D packaging structure at least comprising a system wafer and a first chip which is mixed and bonded on the system wafer;

the second chip is inversely arranged on the surface of the first wiring metal layer and is arranged at intervals with the system integrated chip;

the second re-wiring layer is positioned on the second surface and comprises a second wiring dielectric layer and a second wiring metal layer which is positioned in the second wiring dielectric layer and is electrically connected with the TSV conductive column;

the first external connection interface is positioned on the surface, far away from the TSV conductive column, of the second wiring metal layer.

2. The system-integrated 2.5D architecture of claim 1, wherein: the first chip is a system chip and belongs to different generations with the system wafer.

3. The system-integrated 2.5D architecture of claim 1, wherein the system-integrated chip comprises:

a system wafer;

the second dielectric layer and the second metal pad are formed on the system wafer, and the second metal pad is positioned in the second dielectric layer and is electrically connected with the system wafer;

a metal pillar formed on the second metal pad and electrically connected to the second metal pad;

a first chip;

the first dielectric layer and the first metal pad are formed on the first chip, the first metal pad is located in the first dielectric layer and is electrically connected with the first chip, the first dielectric layer and the second dielectric layer are correspondingly bonded, and the first metal pad and the second metal pad are correspondingly bonded;

the plastic layer is used for coating the first chip, the metal column and the second dielectric layer and exposing the surface of the metal column;

the rewiring layer is formed on the surface of the plastic sealing layer and comprises a wiring dielectric layer and a wiring metal layer which is positioned in the wiring dielectric layer and is electrically connected with the metal column;

and the external connection interface is formed on the surface of the wiring metal layer far away from the metal column.

4. A system-integrated 2.5D architecture according to claim 3, characterized in that: the first metal pads have a pitch of less than 5 μm and the second metal pads have a pitch of less than 5 μm.

5. A system-integrated 2.5D architecture according to claim 3, characterized in that: the first metal pad is sized differently than the second metal pad.

6. A system-integrated 2.5D architecture according to claim 3, characterized in that: the metal posts are located on the second metal pads at the side edges.

7. A system-integrated 2.5D architecture according to claim 3, characterized in that: the front surface of the first wafer is provided with a first signal interface, the first signal interface is electrically connected with the first metal pad, and the arrangement of the first metal pad is different from that of the first signal interface; the front surface of the system wafer is provided with a second signal interface, the second signal interface is electrically connected with the second metal pad, and the arrangement of the second metal pad is different from that of the second signal interface.

8. The system-integrated 2.5D architecture of claim 1, wherein: and the gap between the second chip and the first wiring medium layer is filled with underfill, and the gap between the system integrated chip and the first wiring medium layer is filled with underfill.

9. The system-integrated 2.5D architecture of claim 1, wherein: the first plastic sealing layer is arranged and coats the second chip, the system integrated chip and the first wiring medium layer.

10. The system-integrated 2.5D architecture of claim 1, wherein: the substrate of the system wafer is thinned and planarized.