CN114446904A - Wafer packaging structure and method based on nanoscale radiator - Google Patents
Wafer packaging structure and method based on nanoscale radiator Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 32
- 230000017525 heat dissipation Effects 0.000 claims abstract description 113
- 239000000463 material Substances 0.000 claims abstract description 38
- 238000001259 photo etching Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000000231 atomic layer deposition Methods 0.000 claims description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
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- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052719 titanium Inorganic materials 0.000 claims description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
The invention provides a wafer packaging structure and a method based on a nanoscale radiator. The wafer packaging method comprises the following steps: providing a wafer to be packaged, wherein the wafer comprises a front surface and a back surface which are opposite, and a chip is formed on the front surface; carrying out photoetching on the back surface of the wafer to form a plurality of heat dissipation fins arranged at intervals on the back surface of the wafer, wherein the heat dissipation fins are spaced by the grooves, and the thickness of each heat dissipation fin is less than or equal to 100 nm; and sequentially depositing a thermal interface material layer and a heat dissipation layer on the surface of the heat dissipation fin and the surface of the groove to form the nanoscale heat radiator, wherein the sum of the thicknesses of the thermal interface material layer and the heat dissipation layer is less than 1/2 of the width of the groove. The invention creatively forms a novel structure radiator on the back of the chip, can form a nanometer-sized radiator through the process flow and the structure design, can obtain larger radiating surface area, greatly improves the radiating performance of the device, improves the reliability of the device, can ensure that the size of the packaged structure is not increased, and ensures the advantage of small size of WLCSP.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to back-end packaging, and particularly relates to a wafer packaging structure and a wafer packaging method based on a nanoscale radiator.
Background
Wafer Level Chip System Packaging (WLCSP) is becoming increasingly popular in portable electronic devices due to its better electrical parameters, smaller size and lower manufacturing cost. For example, for power converting Integrated Circuits (ICs) of the same chip size, WLCSP can achieve higher efficiency than Quad Flat No-leads Package (QFN) packages, for example. Because the WLCSP heat-generating component (silicon chip) itself constitutes the package, the silicon material does not have good thermal conductivity; furthermore, the WLCSP chip has a small heat dissipation area, and thus it is impossible to obtain a good heat dissipation performance at the package level. With the miniaturization of the chip size and the improvement of the integration degree, the increase of the heat productivity not only reduces the circuit operation efficiency, but also can cause the thermal runaway of the electronic circuit, and lead to the shortening of the service life of the chip and even the damage of the circuit elements. Therefore, it is critical to provide a heat sink in the integrated circuit as a heat source. However, it becomes a great challenge to dissipate the power dissipation heat in a small area and keep the temperature of the integrated circuit low.
Furthermore, WLCSP packages have higher junction-to-ambient thermal resistance (R) due to small size and packaging material limitationsθJA). R of QFN for the same ICθJAAbout 32.6 deg.C/W, while WLCSP can be as high as 55.8 deg.C/W. Other packaging arrangements, e.g. flip chip ball grid array (FCLBGA)) The package, although the heat dissipation performance can be improved by externally mounting a heat sink. However, the size of the conventional heat sink is large (all in mm or above), which increases the package size of the device and loses the competitive advantage of the small size of the WLCSP.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a wafer package structure based on a nanoscale heat spreader and a method thereof, which are used to solve the problems that the package structure in the prior art has high junction-to-environment thermal resistance, resulting in poor heat dissipation performance of the device, and the package size is increased due to improvement of heat dissipation by installing an external heat spreader.
In order to achieve the above and other related objects, the present invention provides a wafer packaging method based on a nanoscale heat sink, the wafer packaging method comprising:
providing a wafer to be packaged, wherein the wafer comprises a front surface and a back surface which are opposite, and a chip is formed on the front surface;
photoetching the back surface of the wafer to directly form a plurality of heat dissipation fins arranged at intervals on the back surface of the wafer, wherein the heat dissipation fins are spaced by grooves, and the transverse dimension of each heat dissipation fin is less than or equal to 100 nm;
and sequentially forming a thermal interface material layer and a heat dissipation layer on the surface of the heat dissipation fin and the surface of the groove to form the nanoscale heat radiator, wherein the sum of the thicknesses of the thermal interface material layer and the heat dissipation layer is less than 1/2 of the width of the groove.
Optionally, the wafer packaging method further includes a step of thinning the back side of the wafer before etching.
More optionally, the method for thinning the back side of the wafer includes a chemical mechanical polishing method, and the method for forming the thermal interface material layer and the heat dissipation layer includes an atomic layer deposition method.
Optionally, the step of performing photolithography and etching on the back surface of the wafer to form the heat dissipation fin includes:
coating the back of the wafer to form a photoresist layer;
exposing and developing the photoresist layer to define a pattern of the heat dissipation fin in the photoresist layer;
and carrying out plasma etching on the back surface of the wafer according to the photoresist layer so as to form the heat dissipation fin on the back surface of the wafer.
Optionally, the thickness of the photoresist layer is 2 μm, and the patterning process includes baking the photoresist layer after the photoresist layer is formed, and then performing exposure and soft baking, and finally performing development and hard baking.
Optionally, the heat dissipation fin has a lateral dimension greater than 50nm, a height of 2 μm, and a width of the groove of 150nm to 250 nm.
More optionally, the heat dissipation layer includes a metal heat dissipation layer, and a method of forming the thermal interface material layer and the metal heat dissipation layer is an atomic layer deposition method.
Optionally, the thermal interface material layer comprises several of a tantalum layer, a tantalum nitride layer, a titanium layer and a titanium nitride layer, and the metal heat dissipation layer comprises a copper layer and/or an aluminum layer.
Optionally, the thickness of the thermal interface material layer is 10nm to 30nm, and the thickness of the heat dissipation layer is 20nm to 40 nm.
The invention also provides a wafer packaging structure based on the nanoscale heat radiator, which comprises a wafer, wherein the wafer is provided with a front surface and a back surface which are opposite, a chip is formed on the front surface, the back surface is provided with the heat radiator, the heat radiator comprises a plurality of heat radiating fins, a thermal interface material layer and a heat radiating layer, the heat radiating fins are spaced through grooves, the thermal interface material layer and the heat radiating layer are positioned on the surfaces of the heat radiating fins and the surfaces of the grooves, and the heat radiating fins and the wafer are integrally connected.
As described above, the wafer packaging structure and method based on the nanoscale heat sink of the present invention have the following advantages: the invention creatively forms a novel structure radiator structure on the back surface of the chip, namely in-situ (in-situ), can form a nanometer-sized radiator through the process flow and the structure design, and the nanometer-sized radiator can obtain larger radiating surface area, thereby greatly improving the radiating performance of the device, improving the reliability of the device, ensuring that the size of the packaged structure is not increased and ensuring the small-size advantage of the WLCSP.
Drawings
FIG. 1 is a schematic diagram illustrating a wafer to be packaged according to the nanoscale heat sink-based wafer packaging method of the present invention.
FIG. 2 is a schematic diagram illustrating a wafer with a thinned back surface according to the present invention.
FIG. 3 is a schematic diagram illustrating a backside etching of a wafer according to the present invention.
Fig. 4 is a schematic diagram illustrating the formation of heat dissipation fins on the back surface of a wafer according to the present invention.
Fig. 5 is a schematic diagram illustrating a thermal interface material layer and a heat dissipation layer formed on the surface of a heat dissipation fin according to the present invention.
Fig. 6 is an enlarged view of the region a of fig. 4.
Description of the element reference numerals
11 wafer
12 heat radiation fin
13 groove
14 Heat dissipation layer
15 Photoresist layer
16 light shield
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated. In order to keep the drawings as concise as possible, not all features of a single figure may be labeled in their entirety.
Please refer to fig. 1 to 6.
The invention provides a wafer packaging method based on a nanoscale radiator, which comprises the following steps:
providing a wafer 11 to be packaged, wherein the wafer 11 comprises a front surface and a back surface which are opposite, a plurality of chips are usually formed on the front surface, and the plurality of wafers are arranged in an array on the front surface of the wafer; if the initial thickness of the provided wafer 11 is relatively large, for example, as shown in fig. 1, before the next etching process is performed, after the wafer 11 is provided, the back side of the wafer 11 usually needs to be thinned, for example, by using a chemical mechanical polishing method (CMP), the thinned thickness is determined according to the initial thickness of the wafer 11 and a depth to be etched, but it is preferable to ensure that the distance between the back side of the thinned wafer 11 and the chip is still more than 2 μm (note: the thickness of the chip after the current thinning is generally at least 100 μm), so as to avoid adverse effects on the chip on the front side in the subsequent etching process; the surface of the wafer can be flattened through chemical mechanical polishing, and pollutants such as a natural oxide layer on the surface of the wafer 11 can be effectively removed, so that the subsequent etching uniformity can be improved; the structure of the thinned wafer 11 is shown in fig. 2; if the initial thickness of the wafer 11 is relatively thin, the next etching process can be directly performed without thinning;
performing photolithography and etching on the back surface of the wafer 11, so as to directly form a plurality of heat dissipation fins 12 arranged at intervals on the back surface of the wafer 11, wherein the heat dissipation fins 12 are spaced apart from each other by a groove 13, and the transverse dimension of the heat dissipation fin 12 is less than or equal to 100nm, that is, the width of the heat dissipation fin 12 is in nanometer level; the number of the heat dissipation fins 12 may be set as needed, for example, according to the surface area of the chip, and it is usually necessary to ensure that a single chip corresponds to multiple heat dissipation fins 12, so that after the subsequent cutting process is completed, multiple heat dissipation fins 12 are ensured on the back surface of each chip, for example, if the chip size is 3mm × 3mm, the number of heat dissipation fins is 3000 μm/0.3 μm (0.3 μm is the pitch of the heat dissipation fins) ═ 10000 ea; in a further example, the photolithographic etching process may include the steps of: coating the back side of the wafer 11 by using a spin coating process to form a photoresist layer 15, wherein the thickness of the photoresist layer 15 is preferably 1 μm to 3 μm, for example, 2 μm; performing patterning processing including exposure and development on the photoresist layer 15, for example, baking the photoresist layer 15 after forming the photoresist layer 15 to remove the solvent, bubbles and other defects in the photoresist layer 15, so as to improve the adhesion between the photoresist layer 15 and the wafer 11, wherein the baking temperature is, for example, 80 ℃ to 120 ℃, and then performing exposure under the action of the photomask 16The manufacturing cost of the photomask; soft baking is carried out after exposure to enable the exposed structure to be stable, the soft baking temperature is 110-130 ℃, for example, and finally, developing and hard baking are carried out, and finally, the pattern of the heat dissipation fin 12 is defined in the photoresist layer 15; then, performing plasma etching on the back surface of the wafer 11 according to the photoresist layer 15 to form the heat dissipation fin 12 on the back surface of the wafer 11, where the process may be as shown in fig. 3, and in a case where the wafer 11 is made of a silicon material, the wafer may be based on HBr + NF3+O2Performing dry etching on the silicon by using the plasma, wherein the etching CD is close to the photoetching CD, after etching, the pattern in the photoresist layer 15 is transferred to the back side of the wafer 11, and then stripping and cleaning are performed to remove the residual photoresist layer 15 and etching byproducts, so as to obtain the structure shown in FIG. 4;
after the heat dissipation fin 12 is formed, a thermal interface material layer (not shown in the drawings) and a heat dissipation layer 14 are sequentially formed on the surface of the heat dissipation fin 12 and the surface of the groove 13 to form the nanoscale heat sink, the nanoscale heat sink comprises heat dissipation fins 12, a thermal interface material layer and a heat dissipation layer 14, wherein the sum of the thicknesses of the thermal interface material layer and the heat dissipation layer 14 is less than the width of the groove 13, and preferably 1/2, less than the width of the trench, to avoid premature trench sealing during deposition, i.e. to ensure that the formed heat sink layer 14 does not completely fill the trench 13 but still leaves a gap in the trench 13, the gap can be used as a heat dissipation channel to ensure good convection of heat dissipation air and improve heat dissipation uniformity, and the thermal interface material layer and the heat dissipation layer 14 on the surface of the heat dissipation fin 12 and the thermal interface material layer and the heat dissipation layer 14 on the surface of the groove 13 are generally continuous (i.e., connected to each other); the resulting structure after this step is shown in fig. 5.
The invention creatively forms the radiator structure on the back of the chip, namely in-situ (in-situ), and through the process and the structural design, the formed radiator can be in the nanometer size, the size of the packaged structure can be ensured not to be increased, and through the improved structural design, the nanometer-sized radiator can obtain larger surface area, and the heat radiation performance of the device can be greatly improved through the larger surface area. Taking FIG. 6 as an example, assume that of a single chipThe size is 3mm by 3mm, and the chip area is 9mm210000 heat dissipation fins 12 are formed on the back surface of a single chip, the transverse dimension (CD) of each heat dissipation fin is set to be 100nm, the height of each heat dissipation fin is set to be 2000nm (namely 2 micrometers), and the surface area of the heat sink on the back surface of the single chip is (100+200+2000 x 2)/(100+200) x 9mm2＝129mm2. Compared with the surface of the traditional WLCSP, the surface area of the nanometer radiator is improved by 14.3 times and is in a nanometer level. Since heat transfer performance is proportional to surface area. The formula is as follows:
heat flow Q ═ h × a × Δ Tm,
wherein h is the heat transfer coefficient, Δ Tm is the effective average temperature difference, A is the surface area where heat transfer occurs,
therefore, the method can greatly increase the heat dissipation area, thereby greatly improving the heat dissipation performance of the device.
In a preferred example, the method for forming the thermal interface material layer and the heat dissipation layer 14 is an Atomic Layer Deposition (ALD) method, the ALD method has a good step coverage rate, accurate control of deposition thickness can be achieved, and the formed material layer is dense, and can effectively avoid dropping off from the heat dissipation fin; of course, in other examples, electroplating or other methods may be used, but the use of atomic layer deposition is more helpful to form a uniform thermal interface material layer and the heat dissipation layer 14, so as to ensure the heat dissipation uniformity of the device. In a preferred example, the Thermal Interface Material (TIM) layer includes, but is not limited to, several of a tantalum layer, a tantalum nitride layer, a titanium layer, and a titanium nitride layer, and the TIM layer can serve as an adhesion/barrier layer of a metal heat dissipation layer, which helps to improve interface adhesion and interface thermal resistance, so that heat generated during the operation of the chip can be rapidly transferred to the metal heat dissipation layer for heat dissipation; the metal heat sink layer includes, but is not limited to, a copper layer and/or an aluminum layer, preferably a copper layer, since copper has a thermal conductivity of about twice that of aluminum and pure copper has a thermal conductivity of 400W/(m.K).
It should be particularly noted that although the heat dissipation fin is defined as "fin" in the present specification, the heat dissipation fin 12 may have a sheet-like structure, a column-like structure, for example, a rectangular column, or a trapezoidal column structure with an upper dimension smaller than a lower dimension (in this case, the corresponding groove 13 is a structure with an upper opening larger than a lower opening), depending on the setting of the width of the heat dissipation fin, the inventors have found through a lot of experiments that, in a preferred example, the lateral dimension d2 of the heat dissipation fin 12 needs to be larger than 50nm and smaller than or equal to 100nm (i.e., the lateral dimension in fig. 6 is not too large or too small, if too small, the requirement for photolithography is high, the limitation of the critical dimension is imposed, and if too small, the heat dissipation fin 12 formed on the back surface of a single fin is too few, and the heat dissipation effect is not good), and more preferably 100nm, the height h1 is preferably 1.5 μm to 2.5 μm, for example, 1.5 μm, 2.5 μm or an arbitrary value in a range (too large or too small is not preferable, too large is not favorable for forming the heat dissipation layer 14, and too small is not favorable for a good heat dissipation effect), more preferably about 2 μm, the width d1 of the groove 13 is preferably 150nm to 250nm (if the groove is an irregular groove, the width refers to the width at the maximum), more preferably 200nm, and the pitch (pitch) between the fins 12 is the sum of the width of a single fin 12 and the width of a single groove 13, for example, 100nm +200nm is 300 nm.
The sum of the thicknesses of the thermal interface material layer and the heat dissipation layer can be set as required, but in a preferred example, the thickness of the thermal interface material layer is 10nm-30nm, and more preferably 20nm, and the thermal interface material layer in the thickness range can not only play a good role in interface adhesion, but also avoid influence on heat dissipation due to too large thickness of the thermal interface material layer; the thickness of the metal heat dissipation layer 14 is 20nm-40nm, preferably 30nm, and the total thickness of the thermal interface material layer and the heat dissipation metal layer is preferably no greater than 1/2 of the width of the trench 13, so as to ensure that the trench 13 is not completely filled with the heat dissipation layer 14, and sufficient space is available for convection heat dissipation.
After the fabrication of the heat spreader is completed, dicing is usually required to separate the chips, so that the package structure with the in-situ heat spreader can be produced in batch, without the need of mounting the external heat spreaders on the chip surface one by one after the dicing in the conventional manner.
The invention also provides a wafer packaging structure based on the nanoscale radiator, and the wafer packaging structure can be prepared based on the wafer packaging method of any scheme, so that the contents can be fully cited. As shown in fig. 5, the wafer package structure includes a wafer 11, where the wafer 11 has a front surface and a back surface opposite to each other, the front surface has chips formed thereon, and the number of the chips is usually thousands or tens of thousands, the back surface has a heat spreader formed thereon, the heat spreader includes a plurality of heat dissipation fins 12 (usually more than 1 ten thousand), a thermal interface material layer, and a heat dissipation layer 14, the heat dissipation fins 12 are spaced apart from each other by grooves 13, the thermal interface material layer and the heat dissipation layer 14 are located on the surfaces of the heat dissipation fins 12 and the grooves 13, and the heat dissipation fins 12 and the wafer 11 are integrally connected, that is, the material of the heat dissipation fins 12 is a part of the wafer 11, and the wafer 11 is etched to form the heat dissipation fins 12 and the chips, which are also integrally connected. The heat dissipation layer 14 may be, for example, a heat dissipation metal layer, and the thickness, material, and the like of each material layer may refer to the foregoing, which is not described herein for brevity.
The invention not only contributes to the miniaturization of the device, but also can obviously increase the heat dissipation area and improve the heat dissipation performance of the device through the improved structural design.
In summary, the present invention provides a wafer packaging method and structure based on a nanoscale heat sink. The wafer packaging method comprises the following steps: providing a wafer to be packaged, wherein the wafer comprises a front surface and a back surface which are opposite, and a chip is formed on the front surface; photoetching the back surface of the wafer to directly form a plurality of heat dissipation fins arranged at intervals on the back surface of the wafer, wherein the heat dissipation fins are spaced by grooves, and the transverse dimension of each heat dissipation fin is less than or equal to 100 nm; and forming a heat dissipation layer on the surface of the heat dissipation fin and the surface of the groove to form the nanoscale heat sink, wherein the sum of the thicknesses of the thermal interface material layer and the heat dissipation layer is less than 1/2 of the width of the groove. The invention creatively forms a novel structure radiator structure on the back surface of the chip, namely in-situ (in-situ), can form a nanometer-sized radiator through the process flow and the structure design, and the nanometer-sized radiator can obtain larger radiating surface area, greatly improve the radiating performance of the device, improve the reliability of the device, ensure that the size of the packaged structure is not increased, and ensure the small-size advantage of the WLCSP. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A wafer packaging method based on a nanoscale radiator is characterized by comprising the following steps:
providing a wafer to be packaged, wherein the wafer comprises a front surface and a back surface which are opposite, and a chip is formed on the front surface;
carrying out photoetching on the back surface of the wafer so as to directly form a plurality of heat dissipation fins arranged at intervals on the back surface of the wafer, wherein the heat dissipation fins are spaced by the grooves, and the transverse dimension of the heat dissipation fins is less than or equal to 100 nm;
and sequentially forming a thermal interface material layer and a heat dissipation layer on the surface of the heat dissipation fin and the surface of the groove to form the nanoscale heat radiator, wherein the sum of the thicknesses of the thermal interface material layer and the heat dissipation layer is less than 1/2 of the width of the groove.
2. The wafer packaging method according to claim 1, further comprising the step of thinning the back side of the wafer before etching.
3. The wafer packaging method according to claim 2, wherein the method for thinning the back surface of the wafer comprises a chemical mechanical polishing method.
4. The wafer packaging method according to claim 1, wherein the step of performing the photolithography etching on the back surface of the wafer to form the heat dissipation fin comprises:
coating the back of the wafer to form a photoresist layer;
exposing and developing the photoresist layer to define a pattern of the heat dissipation fin in the photoresist layer;
and carrying out plasma etching on the back surface of the wafer according to the photoresist layer so as to form the heat dissipation fin on the back surface of the wafer.
5. The wafer packaging method according to claim 4, wherein the photoresist layer has a thickness of 2 μm, and the exposing and developing comprises the steps of baking the photoresist layer after the photoresist layer is formed, then exposing and soft baking, and finally developing and hard baking.
6. The wafer packaging method according to claim 1, wherein the lateral dimension of the heat dissipation fin is greater than 50nm, the height is 2 μm, and the width of the slot is 150nm to 250 nm.
7. The wafer packaging method according to claim 1, wherein the heat dissipation layer comprises a metal heat dissipation layer, and the method for forming the thermal interface material layer and the metal heat dissipation layer is an atomic layer deposition method.
8. The wafer packaging method as claimed in claim 7, wherein the thermal interface material layer comprises several of a tantalum layer, a tantalum nitride layer, a titanium layer and a titanium nitride layer, and the metal heat dissipation layer comprises a copper layer and/or an aluminum layer.
9. The wafer packaging method according to claim 8, wherein the thermal interface material layer has a thickness of 10nm to 30nm, and the heat dissipation layer has a thickness of 20nm to 40 nm.
10. The wafer packaging structure is characterized in that the wafer packaging structure comprises a wafer, the wafer is provided with a front surface and a back surface which are opposite to each other, a chip is formed on the front surface, a radiator is formed on the back surface, the radiator comprises a plurality of radiating fins, a thermal interface material layer and a radiating layer, the radiating fins are spaced through grooves, the thermal interface material layer and the radiating layer are located on the surfaces of the radiating fins and the surfaces of the grooves, and the radiating fins and the wafer are integrally connected.
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