CN114446820A - Substrate processing system and substrate processing method - Google Patents

Substrate processing system and substrate processing method Download PDF

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Publication number
CN114446820A
CN114446820A CN202111254312.1A CN202111254312A CN114446820A CN 114446820 A CN114446820 A CN 114446820A CN 202111254312 A CN202111254312 A CN 202111254312A CN 114446820 A CN114446820 A CN 114446820A
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Prior art keywords
processing
processing unit
substrate
unit
abnormality
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Chinese (zh)
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绫部刚
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67745—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber characterized by movements or sequence of movements of transfer devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67173—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers in-line arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67207—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67703—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations between different workstations
    • H01L21/67718—Changing orientation of the substrate, e.g. from a horizontal position to a vertical position
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67739—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations into and out of processing chamber
    • H01L21/67742—Mechanical parts of transfer devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Robotics (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Cleaning Or Drying Semiconductors (AREA)

Abstract

The invention provides a technology capable of reducing the number of discarded substrates even if an abnormality occurs in a processing unit. A substrate processing system according to one embodiment of the present invention includes: a plurality of processing units capable of performing the same kind of processing on the substrate; a transport device for transporting the substrate to the plurality of processing units; and a control unit for controlling the plurality of processing units and the conveying device. The control unit also has a relief processing unit, a conveyance processing unit, and a re-relief processing unit. The relief processing unit performs relief processing on the retained substrate being processed in the abnormality processing unit in which the abnormality has occurred, in the abnormality processing unit. The transport processing unit transports the retained substrate from the abnormal processing unit to another processing unit based on a transport pattern set in advance when the retained substrate cannot be subjected to relief processing in the abnormal processing unit. The re-relief processing unit performs a re-relief process on the retained substrate conveyed to another processing unit.

Description

Substrate processing system and substrate processing method
Technical Field
Embodiments of the present invention relate to a substrate processing system and a substrate processing method.
Background
Conventionally, in a substrate processing apparatus for processing a substrate such as a semiconductor wafer (hereinafter, also referred to as a wafer), a technique for improving the yield of the processed substrate has been known (see patent document 1).
Documents of the prior art
Patent document
Patent document 1: japanese laid-open patent publication No. 2009-148734-
Disclosure of Invention
Technical problem to be solved by the invention
The invention provides a technology capable of reducing the number of discarded substrates even if an abnormality occurs in a processing unit.
Means for solving the problems
A substrate processing system according to an aspect of the present invention includes: a plurality of processing units capable of performing the same kind of processing on the substrate; a transport device for transporting the substrate to the plurality of processing units; and a control unit for controlling the plurality of processing units and the conveying device. The control unit also has a relief processing unit, a conveyance processing unit, and a rescure processing unit. The relief processing unit performs relief processing on the retained substrate being processed in the abnormality processing unit in which the abnormality has occurred, in the abnormality processing unit. The transport processing unit transports the retained substrate from the abnormal processing unit to another processing unit based on a transport pattern set in advance when the retained substrate cannot be subjected to relief processing in the abnormal processing unit. The re-relief processing unit re-performs a relief process on the retained substrate conveyed to another processing unit.
Effects of the invention
According to the present invention, even when an abnormality occurs in the processing unit, the number of discarded substrates can be reduced.
Drawings
Fig. 1 is a schematic diagram showing a schematic configuration of a substrate processing system according to an embodiment.
Fig. 2 is a schematic diagram showing a specific configuration example of the processing unit according to the embodiment.
Fig. 3 is a schematic diagram showing a specific configuration example of the inspection apparatus according to the embodiment.
Fig. 4 is a schematic diagram showing a specific configuration example of the cleaning apparatus according to the embodiment.
Fig. 5 is a schematic diagram showing a specific configuration example of the cleaning apparatus according to the embodiment.
Fig. 6 is a block diagram showing a specific configuration example of the control device of the embodiment.
Fig. 7 is a diagram showing an example of the conveyance pattern storage unit according to the embodiment.
Fig. 8 is a diagram for explaining mode 1 of the conveyance mode of the embodiment.
Fig. 9 is a diagram for explaining mode 2 of the conveyance mode of the embodiment.
Fig. 10 is a diagram for explaining mode 3 of the conveyance mode of the embodiment.
Fig. 11 is a diagram showing an example of the inspection information storage unit according to the embodiment.
Fig. 12 is a diagram showing an example of a recipe information storage unit according to the embodiment.
Fig. 13 is a diagram showing an example of the conveyance information storage unit according to the embodiment.
Fig. 14 is a flowchart showing a flow of substrate processing performed in the substrate processing system of the embodiment.
Detailed Description
Hereinafter, embodiments of the substrate processing system and the substrate processing method disclosed in the present application will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below. Note that the drawings are schematic drawings, and the relationship between the sizes of the elements, the proportions of the elements, and the like may be different from those in reality. Further, the drawings may include portions having different dimensional relationships and ratios from each other.
Conventionally, in a substrate processing apparatus for processing a substrate such as a semiconductor wafer (hereinafter, also referred to as a wafer), a technique for improving the yield of the processed substrate has been known.
However, in the conventional technology, when an abnormality occurs in a processing unit, it is difficult to relief a processed substrate in the processing unit (hereinafter, also referred to as "abnormality processing unit") in which the abnormality has occurred.
In particular, when another abnormality occurs when a substrate processed in the abnormality processing unit is subjected to relief processing in the same unit, it is difficult to relieve the substrate, and therefore the substrate has to be discarded.
Therefore, a technique for reducing the number of substrates to be discarded even when an abnormality occurs in the processing unit, which overcomes the above-described problems, has been desired.
< overview of substrate processing System >
First, a schematic configuration of a substrate processing system 1 according to an embodiment will be described with reference to fig. 1. Fig. 1 is a diagram showing a schematic configuration of a substrate processing system 1 according to an embodiment. Hereinafter, in order to clarify the positional relationship, an X axis, a Y axis, and a Z axis orthogonal to each other are specified, and the positive Z axis direction is taken as the vertically upward direction.
As shown in fig. 1, a substrate processing system 1 includes an in-out station 2 and a processing station 3. The carry-in and carry-out station 2 is disposed adjacent to the processing station 3.
The carry-in and carry-out station 2 includes a carrier placing portion 11 and a conveying portion 12. The inspection device 15 is disposed in the conveying unit 12. A plurality of carriers C for horizontally accommodating a plurality of substrates, in the embodiment, semiconductor wafers W (hereinafter, referred to as wafers W), are placed on the carrier placement unit 11.
The transport unit 12 is disposed adjacent to the carrier placement unit 11, and includes a substrate transport device 13 and a transfer unit 14. The substrate transport apparatus 13 includes a wafer holding mechanism that holds the wafer W. The substrate transfer device 13 is movable in the horizontal direction and the vertical direction and rotatable about the vertical axis, and transfers the wafer W among the carrier C, the interface 14, and the inspection device 15 using the wafer holding mechanism.
The inspection device 15 inspects the processing state of the processed wafer W. In the present invention, the inspection apparatus 15 is provided as an in-line inspection apparatus capable of inspecting wafers W processed in the plurality of processing units 17 before being sent out to the carrier C. Details of the inspection device 15 will be described later.
The processing station 3 is disposed adjacent to the conveying section 12. The processing station 3 includes a conveying section 16, a plurality of (10 in the figure) processing units 17, and a cleaning device 19. The plurality of processing units 17 and the cleaning device 19 are arranged in a row on both sides of the conveyance unit 16.
The conveying section 16 is internally provided with a substrate conveying device 18. The substrate transport apparatus 18 is an example of a transport apparatus. The substrate transport apparatus 18 includes a wafer holding mechanism that holds the wafer W. The substrate transfer device 18 is movable in the horizontal direction and the vertical direction and rotatable about the vertical axis, and transfers the wafer W between the delivery portion 14 and the processing unit 17 using the wafer holding mechanism.
The processing unit 17 performs a predetermined substrate processing on the wafer W conveyed by the substrate conveyor 18. The plurality of processing units 17 disposed in the processing station 3 can perform all the same kind of substrate processing. Details of the processing unit 17 will be described later.
The cleaning device 19 cleans the substrate transport device 18. Details of the cleaning device 19 will be described later.
In addition, the substrate processing system 1 includes a control device 4. The control device 4 is, for example, a computer, and includes a control unit 5 and a storage unit 6. The storage unit 6 stores programs for controlling various processes executed in the substrate processing system 1. The control section 5 reads out and executes the program stored in the storage section 6 to control the operation of the substrate processing system 1. Details of the control device 4 will be described later.
The program may be recorded in a computer-readable storage medium, and may be installed from the storage medium to the storage unit 6 of the control device 4. Examples of the computer-readable storage medium include a Hard Disk (HD), a Flexible Disk (FD), an optical disk (CD), a magneto-optical disk (MO), and a memory card.
The storage unit 6 is not limited to the one provided in the control device 4 of the substrate processing system 1, and may be provided in a storage device provided in a different location from the substrate processing system 1 and connected to the control device 4 of the substrate processing system 1 via a network.
In the substrate processing system 1 configured as described above, first, the substrate transport apparatus 13 of the carry-in/out station 2 takes out the wafer W from the carrier C placed on the carrier placement unit 11, and places the taken-out wafer W on the delivery unit 14. The wafer W placed on the delivery portion 14 is taken out of the delivery portion 14 by the substrate transfer device 18 of the processing station 3 and is carried into the processing unit 17.
The wafer W loaded into the processing unit 17 is processed by the processing unit 17, and then is unloaded from the processing unit 17 by the substrate transfer device 18 and placed on the delivery part 14. Then, the processed wafer W placed on the transfer unit 14 is carried into the inspection apparatus 15 by the substrate transport apparatus 13.
The processed wafer W carried into the inspection apparatus 15 is inspected by the inspection apparatus 15, and then carried out of the inspection apparatus 15 by the substrate transfer apparatus 13 and returned to the carrier C of the carrier placement unit 11.
< Structure of processing Unit >
Next, the structure of the processing unit 17 according to the embodiment will be described with reference to fig. 2. Fig. 2 is a schematic diagram showing a specific configuration example of the processing unit 17 according to the embodiment. As shown in fig. 2, the processing unit 17 includes a chamber 20, a substrate processing section 30, a liquid supply section 40, and a recovery cup 50.
The chamber 20 houses the substrate processing unit 30, the liquid supply unit 40, and the recovery cup 50. At the top of the chamber 20, an FFU (Fan Filter Unit) 21 is disposed. FFU21 forms a down flow (downflow) within chamber 20.
The substrate processing section 30 includes a holding section 31, a column section 32, and a driving section 33, and performs liquid processing on the mounted wafer W. The holding portion 31 horizontally supports the wafer W. The support column portion 32 is a member extending in the vertical direction, and has a base end portion rotatably supported by the driving portion 33 and a distal end portion horizontally supporting the holding portion 31. The driving unit 33 rotates the column portion 32 about the vertical axis.
The substrate processing section 30 rotates the column section 32 using the driving section 33, and rotates the holding section 31 supported by the column section 32, thereby rotating the wafer W held by the holding section 31.
A holding member 31a for holding the wafer W from the side surface is disposed on the upper surface of the holding portion 31 of the substrate processing section 30. The wafer W is horizontally held by the holding member 31a in a state slightly separated from the upper surface of the holding portion 31. The wafer W is held by the holding portion 31 in a state where the surface to be subjected to the substrate processing is directed upward.
The liquid supply unit 40 supplies a process fluid to the wafer W. The liquid supply unit 40 includes nozzles 41a to 41d, an arm 42 horizontally supporting the nozzles 41a to 41d, and a rotation/elevation mechanism 43 for rotating and elevating the arm 42.
The nozzle 41a is connected to an etching solution supply source 46a via a valve 44a and a flow regulator 45 a. The etching liquid is used for etching, for example. The nozzle 41b is connected to a DIW supply source 46b via a valve 44b and a flow regulator 45 b. DIW (deionised Water) is used, for example, for rinsing processes.
The nozzle 41c is connected to a cleaning liquid supply source 46c via a valve 44c and a flow regulator 45 c. The cleaning liquid is, for example, SC1 (mixed liquid of ammonia water and aqueous hydrogen peroxide) and is used for the cleaning process. The nozzle 41d is connected to an IPA supply source 46d via a valve 44d and a flow regulator 45 d. IPA (IsoPropyl Alcohol: isopropanol) is used, for example, for the drying treatment.
The nozzle 41a discharges the etching liquid supplied from the etching liquid supply source 46 a. The nozzle 41b discharges the DIW supplied from the DIW supply source 46 b. The nozzle 41c discharges the cleaning liquid supplied from the cleaning liquid supply source 46 c. The nozzle 41d releases the IPA supplied from the IPA supply source 46 d.
In the processing unit 17 of the embodiment, the nozzles 41a to 41d are disposed above (on the front surface side) the wafer W, but the nozzles 41a to 41d may be disposed below (on the back surface side) the wafer W.
The recovery cup 50 is disposed so as to surround the holding portion 31, and collects the processing liquid scattered from the wafer W by the rotation of the holding portion 31. A drain port 51 is disposed at the bottom of the collection cup 50, and the processing liquid collected in the collection cup 50 is discharged from the drain port 51 to the outside of the processing unit 17. Further, an exhaust port 52 for exhausting the gas supplied from FFU21 to the outside of the processing unit 17 is disposed at the bottom of the recovery cup 50.
< Structure of inspection apparatus >
Next, the structure of the inspection apparatus 15 according to the embodiment will be described with reference to fig. 3. Fig. 3 is a schematic diagram showing a specific configuration example of the inspection apparatus 15 according to the embodiment. As shown in fig. 3, the inspection apparatus 15 includes a housing 61, a rotary stage 62, an illumination section 63, a camera 64, and a data processing section 65.
The housing 61 has an opening 61a for carrying in and out the wafer W, and houses therein the rotary stage 62, the illumination section 63, and the camera 64. The rotary stage 62 horizontally supports the wafer W and adjusts the orientation of the supported wafer W. The illumination unit 63 illuminates the surface of the wafer W supported by the rotary stage 62.
The camera 64 photographs the front surface of the wafer W supported by the rotary stage 62. The camera 64 has, for example, a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor.
The data processing unit 65 processes the image of the wafer W obtained by the camera 64, and performs various inspections of the wafer W based on the processed image of the wafer W.
The inspection apparatus 15 according to the embodiment can perform, for example, particle number detection for detecting the number of particles adhering to the wafer W, pattern collapse detection for detecting collapse of a pattern formed on the wafer W, and the like.
The inspection apparatus 15 according to the embodiment can also perform a splash-back detection for detecting a splash-back (splashback) in which the solvent of the resist solution ejected from the surface of the wafer W is again attached to the wafer W, a coating unevenness detection for detecting a coating unevenness of the resist solution, and the like.
The inspection that can be performed by the inspection apparatus 15 according to the embodiment is not limited to the above-described example, and various inspections for checking the processing state of the processed wafer W in the processing unit 17 can be performed.
In the example of fig. 3, the camera 64 is shown to capture an image of the front surface of the wafer W for inspection, but the camera 64 is not limited to capture an image of the front surface of the wafer W for inspection by the camera 64, and may capture an image of the back surface and the edge of the wafer W for inspection.
< Structure of washing apparatus >
Next, the structure of the cleaning apparatus 19 according to the embodiment will be described with reference to fig. 4 and 5. Fig. 4 and 5 are schematic diagrams showing a specific configuration example of the cleaning device 19 according to the embodiment.
Fig. 4 is a sectional view of the cleaning device 19 viewed from the side, and fig. 5 is a sectional view of the cleaning device 19 viewed from above. In addition, in both fig. 4 and 5, the substrate transport apparatus 18 as a cleaning target is shown.
As shown in fig. 4 and 5, the substrate transport apparatus 18 includes a transport arm 110 that holds and transports the outer peripheral portion of the wafer W (see fig. 1). As shown in fig. 5, the transport arm 110 includes a frame portion 111 and an arm portion 112.
The frame 111 is formed in an 3/4 annular shape, for example, to support the outer peripheral portion of the wafer W. The arm portion 112 is integrally formed with the frame portion 111, and supports the frame portion 111.
In the frame portion 111, for example, a plurality of holding portions 113 that directly support the outer peripheral portion of the wafer W are arranged at 3 locations. The plurality of holding portions 113 are arranged at equal intervals on the inner circumference of the frame portion 111, and protrude to the inside of the frame portion 111.
As shown in fig. 4, a base 114 for supporting the transfer arm 110 is disposed on the lower surface side of the transfer arm 110. A drive mechanism 115 is provided on the base 114. The substrate transport apparatus 18 can move the transport arm 110 in the horizontal direction (X-axis direction in fig. 4) by operating the drive mechanism 115.
On the lower surface side of the drive mechanism 115, a shaft 116 supporting the base 114 is disposed. On the lower surface side of the shaft 116, a drive mechanism 117 is further provided. By operating the drive mechanism 117, the substrate transport apparatus 18 can raise and lower the transport arm 110 in the vertical direction (Z-axis direction in fig. 4) and can rotate the transport arm 110.
The cleaning device 19 has a processing container 120 with an opening on the side of the substrate transfer device 18. The cleaning device 19 can clean the holding portion 113 of the transport arm 110 in the processing container 120 by inserting the transport arm 110 from the opening 121 on the side surface of the processing container 120.
Gas injection units 130 for injecting gas are disposed above and below the opening 121 of the processing container 120. The gas injection unit 130 is fixed to an inner wall of the processing container 120 on the upper surface side and an inner wall of the processing container on the lower surface side.
The gas injection unit 130 has a gas injection nozzle 132 in which a plurality of gas injection ports 131 are arranged. The injection port 131 of the gas injection unit 130 located above the opening 121 is disposed at the lower end of the gas injection nozzle 132. Thereby, the gas injection portion 130 positioned above the opening 121 injects the gas vertically downward (in the negative Z-axis direction in fig. 4) from the injection port 131.
On the other hand, the injection port 131 of the gas injection unit 130 located below the opening 121 is disposed at the upper end of the gas injection nozzle 132. Thereby, the gas injection portion 130 positioned below the opening 121 injects the gas vertically upward (positive Z-axis direction in fig. 4) from the injection port 131.
As shown in fig. 5, the gas injection nozzle 132 extends in the short side direction (X-axis direction in fig. 5) of the processing container 120, and both ends thereof are supported by a fixing member 133 fixed to the upper or lower portion of the processing container 120.
Further, a gas supply source 135 is connected to the gas injection nozzle 132 via a supply pipe 134. A heating mechanism 136 such as a heater is disposed in the supply pipe 134. The heating mechanism 136 heats the gas supplied from the gas supply source 135.
When gas is supplied from the gas supply source 135 to the gas injection nozzle 132 and gas is injected from the gas injection nozzle 132, the opening 121 is closed by the flow of the injected gas, and a so-called air curtain (air current) is formed at the opening 121. Further, the gas ejected from the gas ejection nozzle 132 is, for example, air.
Further, an exhaust port, not shown, may be disposed in the processing container 120 so that the gas flow of the gas curtain does not flow to the outside of the processing container 120. In this case, the controller 5 (see fig. 1) can suppress the flow of the gas curtain to the outside of the processing container 120 by discharging the gas from the exhaust port when the gas curtain is formed.
As shown in fig. 4, a cleaning nozzle 140 for discharging a cleaning gas and a cleaning liquid is disposed at an upper portion in the processing container 120. The cleaning nozzle 140 has a size (for example, a size substantially equal to the size of the holding portion 113) that allows the cleaning gas and the cleaning liquid to be uniformly discharged from above the holding portion 113 of the transport arm 110.
The purge nozzle 140 is connected to a purge gas supply source 142 via a purge gas supply pipe 141. The supply pipe 141 is provided with a heating mechanism 143 such as a heater. The heating mechanism 143 heats the cleaning gas supplied from the cleaning gas supply source 142.
A cleaning liquid supply source 145 is connected to the cleaning nozzle 140 via a cleaning liquid supply pipe 144. The supply pipe 144 is provided with a heating mechanism 146 such as a heater. The heating mechanism 146 heats the cleaning liquid supplied from the cleaning liquid supply source 145. The cleaning liquid is heated to be atomized, for example.
Then, the cleaning liquid supplied from the cleaning liquid supply source 145 is discharged from the cleaning nozzle 140 at a high discharge pressure by the cleaning gas supplied from the cleaning gas supply source 142.
The cleaning gas may be, for example, nitrogen, compressed air, helium, or the like. Examples of the cleaning liquid include pure water (preferably at high temperature), a diluent, an amine-based organic solvent, HFE (hydrofluoroether), acetone, and IPA.
The cleaning nozzle 140 is connected to a moving mechanism 148 via an arm 147 as shown in fig. 5. The arm 147 can be moved by the moving mechanism 148 along a guide rail 149 provided to extend in the longitudinal direction (Y-axis direction in fig. 5) of the processing container 120.
The arm 147 is movable in the lateral direction (X-axis direction in fig. 5) of the processing container 120 by the movement mechanism 148, and is also movable in the vertical direction (Z-axis direction in fig. 5).
As shown in fig. 4, a drain port 150 is disposed on the bottom surface of the processing container 120, and the drain port 150 collects the cleaning liquid discharged from the cleaning nozzle 140 and falling to the bottom surface of the processing container 120. A drain pipe 151 is connected to the drain port 150. The liquid discharge port 150 can also be used as an exhaust port.
Next, the cleaning process of the transport arm 110 by the cleaning device 19 described above will be described. First, the controller 5 causes the transfer arm 110 to enter the processing container 120 through the opening 121. At this time, the gas injection from the gas injection nozzle 132 is stopped.
Then, the control unit 5 moves the transport arm 110 to a predetermined position, and then moves the cleaning nozzle 140 to a position directly above one of the holding portions 113 of the transport arm 110.
Next, the control section 5 discharges the cleaning gas and the cleaning liquid from the cleaning nozzle 140 to one holding section 113. At this time, the cleaning liquid is heated to, for example, 70 ℃ by the heating mechanism 146, and becomes mist. Similarly, the purge gas is heated by the heating means 143 to, for example, 70 ℃.
Then, since the cleaning liquid discharged from the cleaning nozzle 140 is discharged at a strong pressure by the cleaning gas, liquid particles of the mist-like cleaning liquid collide with the holding portion 113, and foreign matter adhering to the holding portion 113 is removed.
The cleaning liquid dropped on the bottom surface of the processing container 120 is discharged from the liquid discharge port 150. Further, when the cleaning gas and the cleaning liquid are discharged from the cleaning nozzle 140, the control section 5 causes the gas to be ejected from the gas ejection nozzle 132.
Thus, the air curtain is formed in the opening 121, and the cleaning liquid discharged from the cleaning nozzle 140 is not scattered to the outside of the processing container 120. When the cleaning gas and the cleaning liquid are discharged, the control unit 5 may mix the cleaning gas and the cleaning liquid to form a mixture, and then discharge the mixture from the cleaning nozzle 140.
The control unit 5 performs the release of the cleaning gas and the cleaning liquid for a predetermined time, and after cleaning one of the holding portions 113, only the cleaning gas is ejected from the cleaning nozzle 140. Thereby, the control unit 5 dries the holding portion 113 wetted with the cleaning liquid. When the holding unit 113 is subjected to the drying process, the controller 5 preferably injects gas from the gas injection nozzle 132 to form a gas curtain at the opening 121.
After the cleaning process and the drying process of the one holding unit 113 are completed, the control unit 5 moves the cleaning nozzle 140 to a position directly above the other holding unit 113, and performs the cleaning process and the drying process of the other holding unit 113. In this way, the controller 5 cleans all the 3-position holding units 113 of the transport arm 110.
After the cleaning of all the holding units 113 is completed, the control unit 5 withdraws the transfer arm 110 from the processing container 120. At this time, the controller 5 injects the gas from the gas injection nozzle 132, and heats the gas to, for example, 70 ℃.
Thus, the controller 5 can completely dry the transport arm 110 with the heated gas when the holding portion 113 of the transport arm 110 passes through the opening 121.
< Structure of control device >
Next, the detailed configuration of the control device 4 according to the embodiment will be described with reference to fig. 6 to 13. Fig. 6 is a block diagram showing a specific configuration example of the control device 4 according to the embodiment. As described above, the control device 4 includes the control section 5 and the storage section 6.
In addition, the substrate processing system 1 may include: an input unit (for example, a keyboard, a mouse, etc.) for receiving various operations from a user or the like using the substrate processing system 1; a display unit (e.g., a liquid crystal display) for displaying various information.
The control Unit 5 is realized by executing various programs stored in the storage Unit 6 as a work area by a RAM (Random Access Memory) such as a CPU (Central Processing Unit) or an MPU (Micro Processing Unit). The control unit 5 is realized by an Integrated Circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array).
As shown in fig. 6, the controller 5 includes a substrate processing section 5a, a relief processing section 5b, a selector 5c, a transport processing section 5d, a re-relief processing section 5e, and an inspection section 5f, and performs or executes the functions and functions of substrate processing described below. The internal configuration of the control unit 5 is not limited to the configuration shown in fig. 6, and may be a configuration for performing at least a substrate process described later, or may be another configuration.
The storage unit 6 is implemented by, for example, a semiconductor Memory element such as a RAM or a Flash Memory (Flash Memory), or a storage device such as a hard disk or an optical disk. As shown in fig. 6, the storage unit 6 includes a conveyance pattern storage unit 6a, an inspection information storage unit 6b, a recipe information storage unit 6c, and a conveyance information storage unit 6 d.
The substrate processing section 5a reads the processing recipe and the transfer recipe for the wafer W from the storage section 6 and the like, controls each section based on the recipes, and performs the processing of the wafer W in each of the plurality of processing units 17. The processing conditions for the wafer W are set in advance in the processing recipe, and the transport conditions for the wafer W are set in advance in the transport recipe.
For example, in the processing recipe, an etching process using an etching liquid, a rinsing process using a rinse liquid, a cleaning process using a cleaning liquid, a rinsing process using a rinse liquid, and a drying process using a drying liquid are set in this order. The processing set in the processing recipe is not limited to the above example, and various kinds of processing that can be performed in the processing unit 17 may be set.
When an abnormality occurs in one of the plurality of processing units 17, the relief processing unit 5b performs relief processing on the wafer W (hereinafter, also referred to as a "retained wafer") processed in the abnormality processing unit 17A (see fig. 8) in the same abnormality processing unit 17A. The retaining wafer is an example of a retaining substrate.
The relief process is, for example, a process of washing the chemical solution adhering to the retained wafer with a rinse solution. Since the chemical reaction caused by the chemical solution adhering to the residual wafer is stopped by the relief treatment (water washing treatment), the residual wafer can be prevented from being discarded by separately performing the subsequent substrate treatment.
That is, in the embodiment, even when an abnormality occurs in the processing unit 17, the number of discarded wafers W can be reduced by the relief processing.
When the abnormality processing unit 17A cannot perform relief processing on the remaining wafer, the selection unit 5c selects one transfer mode to be executed by the transfer processing unit 5d from among the plurality of transfer modes stored in the transfer mode storage unit 6 a. The details of the selection processing of the transport mode by the selection unit 5c will be described later.
When the retained wafer cannot be saved in the abnormal processing unit 17A, the transport processing unit 5d transports the retained wafer from the abnormal processing unit 17A to the other normal processing unit 17 based on a transport pattern set in advance.
For example, when the retained wafer cannot be subjected to relief processing in the abnormal processing unit 17A, the transport processing unit 5d transports the retained wafer from the abnormal processing unit 17A to the other processing unit 17 based on the one transport mode selected by the selection unit 5 c.
Fig. 7 is a diagram showing an example of the conveyance pattern storage unit 6a according to the embodiment. As shown in fig. 7, the conveyance pattern storage unit 6a stores a plurality of conveyance patterns (for example, patterns 1 to 3).
The transfer pattern stored in the transfer pattern storage unit 6a includes a transfer order different from the transfer order of the plurality of wafers W performed when all of the plurality of processing units 17 are normal. Specific examples of the conveyance mode will be described below.
Fig. 8 is a diagram for explaining mode 1 of the conveyance mode of the embodiment. In fig. 8 to 10, for the sake of easy understanding, the order of transporting the wafers W in the normal state is shown on the left side, and the order of transporting the wafers W in the abnormal state is shown on the right side. In fig. 8 to 10, the order of sending out the wafers W from the 10 processing units 17 is indicated by numerals in circles.
As shown in fig. 8, in the mode 1 which is one of the plurality of conveyance modes, the wafers W which can be normally processed are preferentially conveyed, and the retained wafers processed in the abnormality processing unit 17A are finally conveyed.
For example, in mode 1, the conveyance order of the staying wafers processed in the abnormality processing unit 17A is changed from the 7 th at the normal time to the 10 th at the end. The wafers W normally processed in each of the processing units 17 are sent out in the order in accordance with a predetermined transport order.
The transfer processing unit 5d controls the substrate transfer device 18 and the like to transfer the normally processed wafers W in the order of the selected pattern 1 and transfer the remaining wafers W from the abnormal processing unit 17A to the vacant other processing unit 17 in the order of the pattern 1.
Fig. 9 is a diagram for explaining mode 2 of the conveyance mode of the embodiment. As shown in fig. 9, mode 2, which is one of the plurality of conveyance modes, is a conveyance mode in which the retained wafers retained in the abnormality processing unit 17A are conveyed with priority and the retained wafers processed in the abnormality processing unit 17A are conveyed first.
For example, in mode 2, the conveyance order of the staying wafers processed in the abnormality processing unit 17A is changed from the 7 th to the 2 nd in the normal time. The reason why the wafer W is not the first (1 st) but the 2 nd is that in order to transfer the retained wafer to another processing unit 17, it is necessary to first send out the wafer W from the other processing unit 17 as a transfer target.
The wafers W that have been processed normally in each of the processing units 17 are sent out in the order in accordance with a predetermined transport order.
The transfer processing unit 5d controls the substrate transfer device 18 and the like to transfer the normally processed wafers W in the order of the selected pattern 2 and transfer the remaining wafers W from the abnormal processing unit 17A to the vacant other processing unit 17 in the order of the pattern 2.
Fig. 10 is a diagram for explaining mode 3 of the conveyance mode of the embodiment. As shown in fig. 10, the mode 3, which is one of the plurality of transfer modes, is a transfer mode in which a wafer W having a short Q-Time is preferably transferred from among the wafers W processed in all the processing units 17 including the abnormality processing unit 17A.
Here, Q-time is a limit time set for the standing time after dry etching in order to prevent oxidation of metal wiring exposed by dry etching, for example.
The transfer processing unit 5d controls the substrate transfer device 18 and the like to transfer the wafers W that have been normally processed in the order of the selected pattern 3 and to transfer the remaining wafers W from the abnormal processing unit 17A to the empty processing unit 17 in the order of the pattern 3.
The explanation returns to fig. 6. The re-relief processing unit 5e performs a re-relief process (hereinafter, also referred to as a re-relief process) on the retained wafer transferred to the other processing unit 17. The re-relief process is a process similar to the above-described relief process, and is, for example, a process of washing the chemical solution adhering to the retained wafer with a rinse solution.
Since the chemical reaction caused by the chemical solution adhering to the residual wafer is stopped by the rescuer process, the residual wafer can be prevented from being discarded by separately performing the subsequent substrate processing. .
That is, in the embodiment, even when the relief processing cannot be performed in the abnormality processing unit 17A, the number of discarded wafers W can be reduced by the relief processing.
In the embodiment, the substrate transfer device 18 may be cleaned by the cleaning device 19 immediately after the transfer processing unit 5d transfers the retained wafer from the abnormal processing unit 17A to the empty processing unit 17 (i.e., immediately before transferring the next wafer W).
Thus, even when the substrate transfer device 18 is contaminated with the chemical solution adhering to the residual wafer, contamination of the wafer W normally processed by the substrate transfer device 18 can be suppressed.
The inspection unit 5f inspects the processing state of the residual wafer subjected to the relief processing or the re-relief processing by the inspection device 15. The inspection unit 5f stores various parameters of the remaining wafers inspected by the inspection device 15 in the inspection information storage unit 6b, the recipe information storage unit 6c, and the transportation information storage unit 6d of the storage unit 6.
The inspection information storage unit 6b stores inspection information on the inspection result of the retained wafer. Fig. 11 is a diagram showing an example of the inspection information storage unit 6b according to the embodiment. The inspection information storage 6b shown in fig. 11 stores a wafer ID, a process alarm, a relief alarm, a process restart time, a transport mode, and an inspection result in association with each other.
Here, the wafer ID is an identification mark for identifying the remaining wafer. The process-time alarm is information indicating the type of alarm generated at the time of the process (i.e., before the relief process) in the abnormality processing unit 17A that has processed the remaining wafer indicated by the associated wafer ID.
The relief processing time alarm is information indicating the type of alarm generated at the time of relief processing (i.e., before the relief processing) in the abnormality processing unit 17A that has processed the remaining wafer indicated by the associated wafer ID. The process alarm and the relief alarm are examples of the abnormality information.
The process resumption time is information indicating the time elapsed from the normal process interruption to the resumption of the continuous process for the remaining wafers indicated by the associated wafer ID.
The transport mode is information indicating the transport mode selected by the selection unit 5c when the retained wafer indicated by the associated wafer ID is transported from the abnormal processing unit 17A to the normal processing unit 17, and is an example of the transport mode information. The inspection result is information indicating the inspection result of the inspection apparatus 15 of the retained wafer indicated by the associated wafer ID, and is an example of the inspection information.
The recipe information storage unit 6c stores recipe information on the conveyance process and the process of the retained wafer. Fig. 12 is a diagram showing an example of the scenario information storage unit 6c according to the embodiment. The recipe information storage unit 6c shown in fig. 12 stores the wafer ID, the transport recipe, and the processing recipe.
The transport recipe is information indicating a transport recipe set in advance for a retained wafer indicated by the associated wafer ID. The process recipe is information indicating a process recipe set in advance in the retained wafer indicated by the associated wafer ID. The delivery scenario and the processing scenario are examples of scenario information.
The conveyance information storage unit 6d stores conveyance information related to the conveyance process of the retained wafer. Fig. 13 is a diagram showing an example of the conveyance information storage unit 6d according to the embodiment. The transport information storage unit 6d shown in fig. 13 stores the wafer ID, the Q-Time setting Time, the carrier carry-out/carry-in Time, and the transport passing module in association with each other.
The Q-Time setting Time is information indicating the Q-Time set in advance in the retained wafer indicated by the associated wafer ID. The carrier carry-out/carry-in time is information of a time from when the remaining wafer indicated by the associated wafer ID is carried out from the carrier C (see fig. 1) to when the remaining wafer is carried in the carrier C.
The transport-through module is information indicating various modules through which the retained wafer indicated by the associated wafer ID passes when transported in the substrate processing system 1. The transport passage module stores, for example, the number of the table on which the carrier C is placed (S1, etc.), the number of the processing unit 17 that has processed the retained wafer (P1, etc.), the number of the inspection apparatus 15 that has inspected the retained wafer (T1, etc.), and the like.
The transport information storage unit 6d may store details of the time when the wafer is left in each of the various modules in the substrate processing system 1.
Here, in the embodiment, the selection unit 5c may select one conveyance mode from a plurality of conveyance modes using the various information stored in the inspection information storage unit 6b, the recipe information storage unit 6c, and the conveyance information storage unit 6d of the storage unit 6 described above. The details of the selection processing of the transport mode by the selection unit 5c will be described below.
First, the selection unit 5c extracts data in which the "process alarm" and the "relief alarm" stored in the inspection information storage unit 6b and the "transport recipe" and the "processing recipe" stored in the recipe information storage unit 6c all match.
When the extracted data is equal to or greater than a predetermined number, the selection unit 5c further extracts data for each of the "transport modes" from the extracted data.
Then, when the extracted data for each of the "conveyance patterns" is equal to or greater than a predetermined number, the selection unit 5c calculates the failure rate in the inspection result for each of the "conveyance patterns", and selects the conveyance pattern with the lowest calculated failure rate.
In this manner, the selection unit 5c may select one conveyance mode from the plurality of conveyance modes based on the type of abnormality occurring in the abnormality processing unit 17A. Thus, the conveyance processing section 5d can convey the retained wafer from the abnormal processing unit 17A to the other processing unit 17 in the conveyance mode with the lowest abnormality rate.
Therefore, according to the embodiment, the number of remaining wafers saved by the re-saving process can be further increased, and thus the number of discarded wafers W can be further reduced.
In addition, when the number of data extracted in the above-described selection process is less than a predetermined number, the selection unit 5c may select a preset transport mode. For example, the selection unit 5c may select the mode 2 in which the relief process of the retained wafer is prioritized in a normal state, and may select the mode 1 in which the process of the normal wafer W is prioritized when there are few tasks to be processed of the wafer W in the substrate processing system 1.
The selection unit 5c may prioritize mode 3 for processing wafers W having a shorter Q-Time when a product defect due to an excess of Q-Time is observed in a product inspection in a subsequent process than the substrate processing system 1.
In addition, when the number of data extracted in the above-described selection process is less than a predetermined number, the selection unit 5c may simply select the transport mode having the lowest abnormality rate.
When the failure rate is significantly higher in the case where the rescure processing is performed in a certain processing unit 17 than in the case where the rescure processing is performed in another processing unit 17, the transport processing unit 5d may not transport the residual wafer to the processing unit 17 having the higher failure rate.
This can further increase the number of wafers retained by the re-relief process, and thus can further reduce the number of discarded wafers W.
The substrate processing system 1 of the embodiment includes a plurality of processing units 17, a transport device (substrate transport device 18), and a control section 5. The plurality of processing units 17 can perform the same process る on the substrate (wafer W). The transfer device (substrate transfer device 18) transfers substrates (wafers W) to the plurality of processing units 17. The control section 5 controls the plurality of process units 17 and the transport device (substrate transport device 18). The control unit 5 includes a relief processing unit 5b, a conveyance processing unit 5d, and a re-relief processing unit 5 e. The relief processing unit 5b performs relief processing on the retained substrate (retained wafer) being processed in the abnormal processing unit 17A in which the abnormality has occurred, in the abnormal processing unit 17A. When the retained substrate (retained wafer) cannot be subjected to relief processing in the abnormal processing unit 17A, the transport processing unit 5d transports the retained substrate (retained wafer) from the abnormal processing unit 17A to another processing unit 17 based on a transport pattern set in advance. The re-relief processing section 5e performs a re-relief process on the retained substrate (retained wafer) transferred to the other processing unit 17. This can reduce the number of discarded wafers W even when an abnormality occurs in the processing unit 17.
In the substrate processing system 1 according to the embodiment, the transfer mode includes a transfer order different from the transfer order of the plurality of substrates (wafers W) performed when all of the plurality of processing units 17 are normal. This can reduce the number of discarded wafers W even when an abnormality occurs in the processing unit 17.
The substrate processing system 1 according to the embodiment further includes a selection unit 5c for selecting one transport mode to be executed by the transport processing unit 5d from among a plurality of transport modes having different transport orders. This can reduce the number of discarded wafers W even when an abnormality occurs in the processing unit 17.
In the substrate processing system 1 according to the embodiment, the selection unit 5c selects one transport mode from the plurality of transport modes based on the type of abnormality generated in the abnormality processing unit 17A. This can further reduce the number of discarded wafers W.
In addition, the substrate processing system 1 of the embodiment includes the inspection device 15 and the storage unit 6. The inspection device 15 inspects the processing state of the processed substrate (wafer W). The storage unit 6 stores the inspection information, the transportation mode information, the abnormality information, and the recipe information in association with each other. The inspection information is information on the processing state of the retained substrate (retained wafer) inspected in the inspection apparatus 15. The conveyance mode information is information on a conveyance mode when the retained substrate (retained wafer) is conveyed to another processing unit 17. The abnormality information is information relating to the kind of abnormality generated in the abnormality processing unit 17A. Recipe information is information on a recipe related to processing of a stuck substrate (stuck wafer). This can reduce the number of discarded wafers W even when an abnormality occurs in the processing unit 17.
In the substrate processing system 1 according to the embodiment, the selection unit 5c selects one transport mode from the plurality of transport modes based on the inspection information, the transport mode information, the abnormality information, and the recipe information stored in the storage unit 6. This can further reduce the number of discarded wafers W.
In addition, the substrate processing system 1 of the embodiment further includes a cleaning device 19 that cleans the transfer device (substrate transfer device 18). The transport processing unit 5d also cleans the transport device (substrate transport device 18) in the cleaning device 19 immediately after the transport device (substrate transport device 18) transports the retained substrate (retained wafer) from the abnormal processing unit 17A to the other processing unit 17. Thus, even when the substrate transfer device 18 is contaminated with the chemical solution adhering to the residual wafer, contamination of the wafer W normally processed by the substrate transfer device 18 can be suppressed.
< flow of substrate treatment >
Next, a flow of substrate processing according to the embodiment will be described with reference to fig. 14. Fig. 14 is a flowchart showing a flow of substrate processing executed in the substrate processing system 1 of the embodiment.
First, the control unit 5 controls the substrate transfer devices 13 and 18 and the like based on a predetermined transfer recipe, and transfers the wafer W into each processing unit 17 (step S101). Then, the substrate processing section 5a controls each processing unit 17 based on a predetermined processing recipe to process a plurality of wafers W (step S102).
Next, the control unit 5 determines whether or not the processing has ended normally in all the processing units 17 (step S103). Here, when the processing is normally ended in all the processing units 17 (yes in step S103), the control unit 5 sends out the wafer W from each processing unit 17 (step S104), and completes the series of processing.
On the other hand, when the processing is not normally completed in any of the processing units 17 (no in step S103), the relief processing unit 5b performs a relief process on the remaining wafer remaining in the abnormal processing unit 17A (step S105). Then, the control unit 5 determines whether or not the relief processing has ended normally in the abnormality processing unit 17A (step S106).
Here, when the relief processing is normally ended in the abnormality processing unit 17A (yes in step S106), the control unit 5 proceeds to the processing of step S104.
On the other hand, when the relief processing in the abnormality processing unit 17A is not normally ended (no in step S106), the selector 5c selects one conveyance mode from the plurality of conveyance modes (step S107).
Next, the conveyance processing section 5d conveys the retained wafer from the abnormality processing unit 17A to another processing unit 17 based on the selected conveyance mode (step S108). Then, the re-relief processing section 5e performs re-relief processing on the remaining wafer in the other processing unit 17 (step S109), and the process proceeds to step S104.
The substrate processing method of the embodiment includes a relief step (step S105), a transport step (step S108), and a re-relief step (step S109). The relief step (step S105) performs relief processing in the abnormal processing unit 17A on a remaining substrate (remaining wafer) being processed in the abnormal processing unit 17A in which an abnormality has occurred among the plurality of processing units 17 capable of performing the same type of processing on the substrate (wafer W). In the transfer step (step S108), when the residual substrate (residual wafer) cannot be saved in the abnormal processing unit 17A, the residual substrate (residual wafer) is transferred from the abnormal processing unit 17A to the other processing unit 17 based on a predetermined transfer pattern. The re-relief step (step S109) re-performs the relief process on the retained substrate (retained wafer) transferred to the other processing unit 17. This can reduce the number of discarded wafers W even when an abnormality occurs in the processing unit 17.
While the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit and scope of the invention. For example, although the above embodiment has been described with the example in which the plurality of processing units 17 for processing the wafers W by wet processing are provided, a plurality of processing units for processing the wafers W by various dry processing may be provided.
The embodiments disclosed herein are illustrative in all respects, and are not intended to be limiting. In fact, the above-described embodiments can be implemented in a variety of ways. Further, the above-described embodiments may be omitted, replaced, or changed in various ways without departing from the spirit and scope of the appended claims.
The "section (module, unit)" may be read as a "mechanism" or a "circuit" instead. For example, the selection unit may be read as a selection mechanism or a selection circuit.
Description of the reference numerals
W wafer (one example of substrate)
1 substrate processing system
4 control device
5 control part
5b relief processing part
5c selection part
5d conveying processing part
5e reliving part
5f inspection part
6 storage part
6a transport mode storage section
6b inspection information storage part
6c plan information storage part
6d conveyance information storage unit
15 inspection device
17 processing unit
17A exception handling unit
18 substrate transport device (an example of transport device)
19 cleaning the device.

Claims (8)

1. A substrate processing system, comprising:
a plurality of processing units capable of performing the same kind of processing on the substrate;
a transport device for transporting the substrate to the plurality of processing units; and
a control section that controls the plurality of processing units and the transport device,
the control unit includes:
a relief processing unit that performs relief processing on a retained substrate being processed in an abnormality processing unit in which an abnormality has occurred, in the abnormality processing unit;
a conveyance processing unit that conveys the retained substrate from the abnormality processing unit to another processing unit based on a conveyance pattern set in advance when the retained substrate cannot be subjected to relief processing in the abnormality processing unit; and
and a re-relief processing unit that performs a re-relief process on the retained substrate conveyed to the other processing unit.
2. The substrate processing system of claim 1, wherein:
the transport mode includes a transport order different from a transport order of the plurality of substrates performed when all of the plurality of processing units are normal.
3. The substrate processing system of claim 1 or 2, wherein:
the control unit further includes a selection unit that selects one of the conveyance modes to be executed by the conveyance processing unit from among a plurality of conveyance modes having different conveyance orders.
4. The substrate processing system of claim 3, wherein:
the selection unit selects one of the transport modes based on a type of an abnormality occurring in the abnormality processing unit.
5. The substrate processing system of claim 4, further comprising:
an inspection device that inspects a processing state of the processed substrate; and
a storage unit that stores inspection information relating to a processing state of the retained substrate that has been inspected in the inspection apparatus, transport mode information relating to the transport mode when the retained substrate is transported to another processing unit, abnormality information relating to a type of abnormality that has occurred in the abnormality processing unit, and recipe information relating to a recipe relating to processing of the retained substrate in association with each other.
6. The substrate processing system of claim 5, wherein:
the selection unit selects one of the conveyance modes from among the plurality of conveyance modes based on the inspection information, the conveyance mode information, the abnormality information, and the recipe information stored in the storage unit.
7. The substrate processing system of any of claims 1 to 6, wherein:
also comprises a cleaning device for cleaning the conveying device,
the transport processing unit may be configured to clean the transport device in the cleaning device immediately after the transport device transports the retained substrate from the abnormal processing unit to another processing unit.
8. A method of processing a substrate, comprising:
a relief step of performing relief processing in an abnormality processing unit, which is capable of performing the same kind of processing on a substrate, on a retained substrate being processed in the abnormality processing unit in which an abnormality has occurred, among a plurality of processing units capable of performing the same kind of processing on the substrate;
a conveying step of conveying the retained substrate from the abnormal processing unit to another processing unit based on a preset conveying mode when the retained substrate cannot be subjected to relief processing in the abnormal processing unit; and
and a re-relief step of performing a re-relief process on the retained substrate conveyed to another processing unit.
CN202111254312.1A 2020-11-02 2021-10-27 Substrate processing system and substrate processing method Pending CN114446820A (en)

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