CN114443541A

CN114443541A - Safety isolation and information interaction system

Info

Publication number: CN114443541A
Application number: CN202210049381.7A
Authority: CN
Inventors: 申祥材
Original assignee: Beijing Dongda Jinzhi Technology Co ltd
Current assignee: Beijing Dongda Jinzhi Technology Co ltd
Priority date: 2022-01-17
Filing date: 2022-01-17
Publication date: 2022-05-06

Abstract

The application relates to a safety isolation and information interaction system, comprising: a board card; the board card is an ARM board card; the board card is provided with a processor and an electronic device; the processor is an LS1043 circuit board, and four Cortex-A53 cores are arranged in the processor; the electronic device comprises a memory, a storage module, a USB interface, a PCIE module, a network port, a Console port and a SATA interface; the storage module comprises a NOR flash memory chip, a NAND flash memory chip and an EMMC chip, the PCIE module comprises a MinPCIE interface and a PCIE interface, and the network port comprises an Ethernet interface and a COMBOSFP optical port; the board card is also provided with a power input module and a level conversion chip which are electrically connected; the level conversion chip is provided with a plurality of output ends, and the plurality of output ends of the level conversion chip are respectively and electrically connected with each electronic device on the mainboard card and used for providing corresponding driving voltage for each electronic device. The hardware cost is low, the power consumption of the whole machine is low, the machine can be used in severe environment, wide temperature can be realized, and the board card uses the reduced instruction set RISC and has high working efficiency.

Description

Safety isolation and information interaction system

Technical Field

The application relates to the field of information communication, in particular to a safety isolation and information interaction system.

Background

The safety isolation and information interaction system is an information safety device which uses a solid-state switch read-write medium with multiple control functions and is connected with two independent host systems. Because two independent host systems are isolated through the gatekeeper, no physical connection, logical connection and information transmission protocol for communication exist between the systems, no information exchange performed by the protocol exists, and only no protocol ferry is performed in a data file form.

Two sets of independent systems are respectively connected with a safe network and a non-safe network, and information ferry is carried out between the two sets of systems through a network brake, so that no direct physical access exists between the two sets of systems. In the communication process, when the storage medium is connected with a secure network, the connection with an insecure network is disconnected; disconnecting the connection with the secure network when connected with the unsecured network; the data exchange is carried out by using the data paths in the two systems in a time-sharing manner so as to achieve the purposes of isolation and exchange. All network connections with potential attack possibility to the secure network are logically isolated and blocked, so that an external attacker cannot directly invade, attack or destroy the secure network, and the security of a host in the secure network is guaranteed.

The existing security isolation and information interaction system uses an X86 mainboard, and the hardware cost is high.

Disclosure of Invention

In view of the above, the present application provides a security isolation and information interaction system. The hardware cost is low, the power consumption of the whole machine is low, the machine can be used in severe environment, wide temperature can be realized, and the board card uses the reduced instruction set RISC and has high working efficiency.

According to an aspect of the present application, there is provided a security isolation and information interaction system, including:

a board card;

the board card is an ARM board card;

the board card is provided with a processor and an electronic device;

the processor is an LS1043 circuit board, and four Cortex-A53 cores are arranged in the processor;

the electronic device comprises a memory, a storage module, a USB interface, a PCIE module, a network port, a Console port and a SATA interface;

the memory, the storage module, the USB interface, the PCIE module, the network port, the Console port and the SATA interface are all electrically connected with the processor;

the storage module comprises a NOR flash memory chip, a NAND flash memory chip and an EMMC chip, the PCIE module comprises a MinPCIE interface and a PCIE interface, and the network interface comprises an Ethernet interface and a COMBOSFP optical interface;

the board card is also provided with a power input module and a level conversion chip;

the power input module comprises a first capacitor, a second capacitor, a third capacitor, a voltage stabilizer and a connector;

one end of the first capacitor is electrically connected with a power supply, and the other end of the first capacitor is grounded;

the second capacitor, the third capacitor and the voltage stabilizer are all arranged in parallel with the first capacitor;

the input end of the connector is electrically connected to two poles of the voltage stabilizer, and the output end of the connector is electrically connected with the level conversion chip;

the level conversion chip is provided with a plurality of output ends, and the plurality of output ends of the level conversion chip are respectively electrically connected with the electronic devices on the main board card and used for providing corresponding driving voltage for the electronic devices.

In a possible implementation manner, the board card is further provided with a PHY;

the PHY and the processor are electrically connected through an RGMII bus, and the PHY outputs to the Ethernet interface and the COMBOSFP optical port.

In one possible implementation manner, the level conversion chip includes a first conversion chip and a second conversion chip;

the VIN pin of the first conversion chip is used for receiving 12V voltage, and a plurality of capacitors connected in parallel are externally connected to the VIN pin of the first conversion chip;

the SW pin of the first conversion chip is externally connected with a first inductor and then outputs 5V voltage;

the VIN pin of the second conversion chip is used for receiving the 5V voltage output by the first conversion chip, and a plurality of capacitors connected in parallel are externally connected to the VIN pin of the second conversion chip;

and the SW pin of the second conversion chip is externally connected with a second inductor, and the output end of the second inductor is electrically connected with the PHY and used for providing 1.1V voltage for the PHY.

In a possible implementation manner, the level conversion chip further includes a third conversion chip, a fourth conversion chip, and a fifth conversion chip

The VIN pin of the third conversion chip is used for receiving 12V voltage, and a plurality of capacitors connected in parallel are externally connected to the VIN pin of the third conversion chip;

the LX pin of the third conversion chip is externally connected with a third inductor which is arranged in series, and the output end of the third capacitor is also electrically connected with a plurality of capacitors which are connected in parallel and then outputs 3.3V voltage;

a power supply input pin of the fourth conversion chip is connected to the 3.3V voltage output by the output end of the third capacitor;

a first conversion output pin of the fourth conversion chip is externally connected with a fourth inductor, and an output end of the fourth inductor is electrically connected with the capacitor and then outputs 1.5V voltage;

a second conversion output pin of the fourth conversion chip is externally connected with a fifth inductor, and the output end of the fifth inductor is electrically connected with more than two capacitors connected in parallel and then outputs 1.8V voltage;

a third conversion output pin of the fourth conversion chip is externally connected with a sixth inductor, and the output end of the sixth inductor is electrically connected with a plurality of capacitors connected in parallel and then outputs 2.5V voltage;

a fourth conversion output pin of the fourth conversion chip is externally connected with a seventh inductor, and the output end of the seventh inductor is electrically connected with more than two capacitors connected in parallel and then outputs 0.6V voltage;

a VIN pin of the fifth conversion chip is externally connected with a capacitor, and the VIN pin of the fifth conversion chip is connected with 1.8V voltage;

the VOUT pin of the fifth conversion chip is externally connected with more than two capacitors connected in parallel and then outputs 1.5V voltage to supply power to the MinPCIE interface;

a first resistor and a second resistor are also connected in series to a VOUT pin of the fifth conversion chip, and the second resistor is grounded;

the SET pin of the fifth conversion chip is electrically connected between the first resistor and the second resistor.

In a possible implementation manner, the level conversion chip further includes a sixth conversion chip;

a VIN pin of the sixth conversion chip is externally connected with a capacitor and used for accessing 1.8V voltage;

the VOUT pin of the sixth conversion chip is externally connected with more than two capacitors connected in parallel and then outputs 1.35V voltage to the processor;

a third resistor and a fourth resistor are further connected in series to a VOUT pin of the sixth conversion chip, and the fourth resistor is grounded;

the SET pin of the sixth conversion chip is electrically connected between the third resistor and the fourth resistor.

In a possible implementation manner, the level conversion chip further includes a seventh conversion chip;

a VIN pin of the seventh conversion chip is externally connected with a plurality of parallel number capacitors and is used for receiving 12V voltage;

and an LX pin of the seventh conversion chip is externally connected with an eighth inductor which is connected in series, and the output end of the eighth inductor is electrically connected with a plurality of capacitors which are connected in parallel and then outputs 1V voltage to the processor.

In one possible implementation manner, the memory uses 4 DDR4 memory particles with 8 bits and 1GB capacity;

the processor and the memory grain are connected through a DDR4 bus.

In a possible implementation manner, the NOR flash memory chip is 1 NOR flash memory of 128MB, and is connected with the processor through an IFC local bus;

the NAND flash memory chip is 1GBNAND flash memory with 1 chip.

In one possible implementation, the EMMC chip is 1 EMMC of 16GB and is extensible to 64 GB.

In a possible implementation manner, there are 6 ethernet interfaces, and there are two COMBOSFP optical interfaces;

the PHYs comprise 2 single-port PHYs and 1 4-port PHY;

2 single port PHY and processor are connected by RGMI bus, and each outputs 1 Ethernet interface and 1 COMBOSFP optical port;

the 4-port PHY is connected with the processor through a QSGMII bus, and the 4-port PHY outputs to 4 paths of the Ethernet interfaces.

The safety isolation and information interaction system of the embodiment of the application are provided with the integrated circuit board, be provided with the treater on the integrated circuit board, storage module, the USB interface, the PCIE module, the net gape, the Console mouth, the SATA interface, power input module and level conversion chip, wherein, the treater is LS1043 circuit board, four built-in Cortex-A53 kernels, and input the power through power input module, convert the electricity of power input module input through level conversion chip, and to the treater, storage module, the USB interface, the PCIE module, the net gape, the Console mouth, SATA interface power supply. The processor of the safety isolation and information interaction system is based on an LS system architecture, 4 Cortex-A53 kernels are combined with data path acceleration and network, peripheral interfaces required by networking, wireless infrastructure and a general embedded application program, and the LS1043 circuit board processor has enterprise-level performance and safety functions, so that the safety isolation and information interaction system is suitable for small-size, low-power-consumption and low-cost consumption and network application. And the ARM board card is used, so that the hardware cost is low, the power consumption of the whole machine is low, the ARM board card can be used in a severe environment, the wide temperature range can be realized, and the working efficiency of the RISC board card using the reduced instruction set is high.

Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the application and, together with the description, serve to explain the principles of the application.

Fig. 1 shows a board card block diagram of a security isolation and information interaction system according to an embodiment of the present application;

FIG. 2 illustrates a circuit diagram of a power input module of a security isolation and information interaction system of an embodiment of the present application;

FIG. 3 is a circuit diagram of a first conversion chip of the security isolation and information interaction system according to the embodiment of the present application;

FIG. 4 shows a circuit diagram of a second conversion chip of the security isolation and information interaction system according to the embodiment of the present application;

FIG. 5 is a circuit diagram of a third conversion chip of the security isolation and information interaction system according to the embodiment of the present application;

FIG. 6 is a circuit diagram of a fourth conversion chip of the security isolation and information interaction system according to the embodiment of the present application;

FIG. 7 is a circuit diagram of an eighth conversion chip of the security isolation and information interaction system according to the embodiment of the present application;

FIG. 8 is a circuit diagram of a fifth conversion chip of the security isolation and information interaction system according to the embodiment of the present application;

FIG. 9 is a circuit diagram of a sixth conversion chip of the security isolation and information interaction system according to the embodiment of the present application;

fig. 10 shows a circuit diagram of a seventh conversion chip of the security isolation and information interaction system according to the embodiment of the present application.

Detailed Description

Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

It will be understood, however, that the terms "central," "longitudinal," "lateral," "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in an orientation or positional relationship indicated in the drawings for convenience in describing or simplifying the description, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be considered as limiting the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present application. It will be understood by those skilled in the art that the present application may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present application.

Fig. 1 shows a board card block diagram of a security isolation and information interaction system according to an embodiment of the present application. Fig. 2 shows a circuit diagram of a power input module of a security isolation and information interaction system according to an embodiment of the present application. Fig. 3 shows a circuit diagram of a first conversion chip of the security isolation and information interaction system according to an embodiment of the present application. Fig. 4 shows a circuit diagram of a second conversion chip of the security isolation and information interaction system according to the embodiment of the present application. Fig. 5 shows a circuit diagram of a third conversion chip of the security isolation and information interaction system according to the embodiment of the present application.

Fig. 6 shows a circuit diagram of a fourth conversion chip of the security isolation and information interaction system according to the embodiment of the present application.

Fig. 7 shows a circuit diagram of an eighth conversion chip of the security isolation and information interaction system according to the embodiment of the present application.

Fig. 8 shows a circuit diagram of a fifth conversion chip of the security isolation and information interaction system according to an embodiment of the present application.

Fig. 9 shows a circuit diagram of a sixth conversion chip of the security isolation and information interaction system according to the embodiment of the present application. Fig. 10 shows a circuit diagram of a seventh conversion chip of the security isolation and information interaction system according to the embodiment of the present application. As shown in fig. 1 or fig. 2, the security isolation and information interaction system includes: the integrated circuit board comprises a board card and a processor, wherein the board card is an ARM board card, the processor and an electronic device are configured on the board card, the processor is an LS1043 circuit board, and four Cortex-A53 cores are arranged in the processor. The electronic device comprises a memory, a storage module, a USB interface, a PCIE module, a network port, a Console port and a SATA interface, wherein the memory, the storage module, the USB interface, the PCIE module, the network port, the Console port and the SATA interface are all electrically connected with the processor. The storage module comprises a NOR flash memory chip, a NAND flash memory chip and an EMMC chip, the PCIE module comprises a MinPCIE interface and a PCIE interface, and the network interface comprises an Ethernet interface and a COMBOSFP optical interface. The board card is further provided with a power input module and a level conversion chip, the power input module comprises a first capacitor C32, a second capacitor C188, a third capacitor C183, a voltage stabilizer D4 and a connector, one end of the first capacitor C32 is electrically connected with a 12V power supply, and the other end of the first capacitor C32 is grounded. The second capacitor C188, the third capacitor C183 and the voltage stabilizer D4 are all arranged in parallel with the first capacitor C32, the input end of the connector is electrically connected to the two poles of the voltage stabilizer D4, and the output end of the connector is electrically connected with the level conversion chip. The level conversion chip is provided with a plurality of output ends, and the plurality of output ends of the level conversion chip are respectively and electrically connected to each electronic device on the mainboard and used for providing corresponding driving voltage for each electronic device.

In a possible implementation manner, the board card is further provided with a PHY, the PHY is electrically connected with the processor through an RGMII bus, and the PHY outputs to the ethernet interface and the COMBOSFP optical port.

As shown in fig. 1, fig. 2, fig. 3 or fig. 4, further, in a possible implementation, the level conversion chip includes a first conversion chip U682 and a second conversion chip U685, a VIN pin of the first conversion chip U682 is used for receiving a voltage of 12V, and a VIN pin of the first conversion chip U682 is externally connected with a plurality of capacitors connected in parallel. The SW pin of the first conversion chip U682 is externally connected with the first inductor L9 to output 5V voltage. The VIN pin of the second conversion chip U685 is configured to receive the 5V voltage output by the first conversion chip U682, and the VIN pin of the second conversion chip U685 is externally connected to a plurality of capacitors connected in parallel. The SW pin of the second converter chip U685 is externally connected with a second inductor L10, and the output end of the second inductor L10 is electrically connected to the PHY for providing a voltage of 1.1V to the PHY.

Here, it should be noted that the VIN pin of the first conversion chip U682 is externally connected with a plurality of capacitors connected in parallel as a first capacitor, and a connection terminal of the plurality of capacitors connected in parallel and a combined terminal of the VIN pin of the first conversion chip U682 are electrically connected to an output terminal of the connector for receiving a voltage of 12V. The VIN pin of the second conversion chip U685 is externally connected with a plurality of capacitors connected in parallel, which is a second capacitor, and the connection ends of the plurality of capacitors connected in parallel and the combined end of the VIN pin of the second conversion chip U685 are used for receiving the 5V voltage output by the first conversion chip U682.

Here, it should also be noted that, in one possible implementation, there are four capacitors, that is, the capacitor C2402, the capacitor C5264, the capacitor C5261 and the capacitor C5267, one end of the capacitor C2402, the capacitor C5264, the capacitor C5261 and the capacitor C5267 after being connected in parallel is electrically connected between the output end of the connector and the VIN pin of the first conversion chip U682, and the other end is grounded. The resistor R3781 and the resistor R3785 are electrically connected, one end of the resistor R3781, which is not connected with the resistor R3785, is electrically connected between one end of the resistor R3781, which is connected in parallel with the capacitor C5261 and the capacitor C5267, the capacitor C2402, the capacitor C5264, the capacitor C5261 and the capacitor C5267, and the pin VIN of the first conversion chip U682, and the other end of the resistor R3785 is grounded. The EN pin of the first conversion chip U682 is electrically connected between the resistor R3781 and the resistor R3785. The VCC pin of the first conversion chip U682 is externally connected and connected in parallel to the capacitor C5366 and the capacitor C5312, and the other end of the first conversion chip U682 connected in parallel to the capacitor C5366 and the capacitor C5312 is grounded. A resistor R3782 and a capacitor C5263 are also connected in series between the BST pin of the first conversion chip U682 and the SW pin of the first conversion chip U682. The output end side of the first inductor L9 is further electrically connected with a capacitor C5265 and a capacitor C5266 which are arranged in parallel, and the other ends of the capacitor C5265 and the capacitor C5266 which are arranged in parallel are grounded. The FB pin of the first conversion chip U682 is externally connected with a resistor R3834, a resistor R3784 and a resistor R3783, wherein one end of the resistor R3834 is electrically connected with the FB pin of the first conversion chip U682, the other end of the resistor R3834 is electrically connected with one end of the resistor R3784, and the other end of the resistor R3784 is electrically connected with the output end of the first inductor L9. One end of the resistor R3783 is electrically connected between the resistor R3834 and the resistor R3783, and the other end is grounded.

Here, it should also be noted that, in one possible implementation, there are four capacitors in the second number, four capacitors in the second number are respectively the capacitor C5302, the capacitor C5303, the capacitor C5300, and the capacitor C5306, and one end of the parallel connection of the capacitors C5302, C5303, C5300, and C5306 is electrically connected between the output end of the first inductor L9 and the VIN pin of the second conversion chip U685, and the other end is grounded. A resistor R3799 is electrically connected between the VIN pin of the second converting chip U685 and the EN pin of the second converting chip U685. A resistor R3800 and a capacitor C5301 which are arranged in series are electrically connected between the BST pin of the second conversion chip U685 and the SW pin of the second conversion chip U685. The output end of the second inductor L10 is electrically connected to one end of the capacitor C5304, the capacitor C5305, the capacitor C5314, and the capacitor C5315, which are arranged in parallel, and one end of the capacitor C5304, the capacitor C5305, the capacitor C5314, and the capacitor C5315 is grounded. And one end of the capacitor C5304, the capacitor C5305, the capacitor C5314, the capacitor C5315 and the output end of the second inductor L10, which are arranged in parallel, are electrically connected is used as a voltage output end of 1.1V. The FB pin of the second converter chip U685 is externally connected with a resistor R3802 and a capacitor C5313, which are arranged in parallel, and the other ends of the resistor R3808 and the capacitor C5313 arranged in parallel are electrically connected to the output end of the second inductor L10. The FB pin of the second converter chip U685 is further externally connected with a resistor R3801, and the other end of the resistor R3801 is grounded.

As shown in fig. 1, fig. 2, fig. 5, fig. 6, fig. 7, or fig. 8, in a possible implementation manner, the level converting chip further includes a third converting chip U683, a fourth converting chip U33C, and a fifth converting chip U686, wherein a VIN pin of the third converting chip U683 is configured to receive a voltage of 12V, and a VIN pin of the third converting chip U683 is externally connected with a plurality of capacitors connected in parallel. The LX pin of the third converting chip U683 is externally connected with a third inductor L67 connected in series, and the output terminal of the third capacitor is further electrically connected with a plurality of capacitors connected in parallel to output a 3.3V voltage. The power supply input pin of the fourth conversion chip U33C is connected to the voltage of 3.3V output by the output terminal of the third capacitor. The first conversion output pin of the fourth conversion chip U33C is externally connected with a fourth inductor L25, and the output end of the fourth inductor L25 is electrically connected to the capacitor and outputs 1.5V. The second conversion output pin of the fourth conversion chip U33C is externally connected with a fifth inductor L27, and the output end of the fifth inductor L27 is electrically connected with more than two capacitors connected in parallel and outputs 1.8V voltage. A sixth inductor L24 is externally connected to a third conversion output pin of the fourth conversion chip U33C, and an output end of the sixth inductor L24 is electrically connected with a plurality of capacitors connected in parallel and outputs 2.5V. A seventh inductor L26 is externally connected to a fourth conversion output pin of the fourth conversion chip U33C, and an output end of the seventh inductor L26 is electrically connected with more than two capacitors connected in parallel and outputs 0.6V voltage. A capacitor is externally connected to the VIN pin of the fifth conversion chip U686, and the VIN pin of the fifth conversion chip U686 is connected with 1.8V voltage. And the VOUT pin of the fifth conversion chip U686 is externally connected with more than two capacitors connected in parallel and then outputs 1.5V voltage to supply power to the MinPCIE interface. The VOUT pin of the fifth conversion chip U686 is further connected in series with a first resistor and a second resistor, the second resistor is grounded, and the SET pin of the fifth conversion chip U686 is electrically connected between the first resistor and the second resistor.

Here, it should be noted that, in one possible implementation, the VIN pin of the third converting chip U683 is externally connected with a plurality of capacitors connected in parallel, and the combined terminal of the connecting terminals of the plurality of capacitors connected in parallel and the VIN pin of the third converting chip U683 is electrically connected to the output terminal of the connector to receive the voltage of 12V. The output end of the third inductor L67 is electrically connected with a plurality of capacitors arranged in parallel, wherein the capacitors are No. four capacitors, and the connection ends of the capacitors arranged in parallel and the output end merging end of the third capacitor C183 are used for outputting 3.3V voltage. The output end of the fourth inductor L25 is electrically connected to a plurality of parallel capacitors, which are No. five capacitors, and the combined end of the connection ends of the plurality of parallel capacitors and the output end of the fourth inductor L25 outputs 1.5V voltage. The output end of the fifth inductor L27 is electrically connected with more than two capacitors connected in parallel, namely a sixth capacitor, and the combined end of the connecting end of the more than two capacitors connected in parallel and the output end of the fifth inductor L27 outputs 1.8V voltage. The multiple capacitors connected in parallel at the output end of the sixth inductor L24 are No. seven capacitors, and the connection ends of the multiple parallel capacitors and the output end combination end of the sixth inductor L24 are used for outputting 2.5V voltage. More than two capacitors connected in parallel at the output end of the seventh inductor L26 are eighth capacitors, and the connection end of the more than two capacitors connected in parallel and the output end of the seventh inductor L26 are combined to output 0.6V voltage. The capacitor externally connected with the VIN pin of the fifth conversion chip U686 is a ninth capacitor, and the combined end of the ninth capacitor and the VIN pin of the fifth conversion chip U686 is connected with 1.8V voltage. More than two capacitors which are externally connected with the VOUT pin of the fifth conversion chip U686 and connected in parallel are No. ten capacitors, and the joint ends of the more than two capacitors and the joint end of the VOUT pin of the fifth conversion chip U686 output 1.5V voltage to supply power to the MinPCIE interface.

Here, it should be noted that, in one possible implementation, the capacitor No. three includes a capacitor C5273, a capacitor C5272, a capacitor C5269, a capacitor C5270, a capacitor C5269 and a capacitor C5271, and one end of the parallel connection of the capacitor C5273, the capacitor C5272, the capacitor C5269, the capacitor C5270, the capacitor C5269 and the capacitor C5271 is connected to a VIN pin (the VIN pin includes a VIN1 pin, a VIN2 pin and a VIN3 pin) of the third conversion chip U683, and is connected to a 12V voltage, and the other end is grounded. A resistor R3786 is electrically connected between the VIN pin and the TON pin of the third conversion chip U683. The VCC pin of the third conversion chip U683 is externally connected with a capacitor C5274 and a capacitor C5275 which are arranged in parallel, one end of the capacitor C5274 and one end of the capacitor C5275 which are arranged in parallel are connected with 5V voltage, and the other end of the capacitor C5274 and the other end of the capacitor C5275 which are arranged in parallel are grounded. A resistor R3787 is electrically connected between the EN pin of the third converting chip U683 and the VCC pin of the third converting chip U683, a resistor R3788 is electrically connected between the PFM pin of the third converting chip U683 and the VCC pin of the third converting chip U683, and one end of the resistor R3787 and one end of the resistor R3788 are electrically connected to the VCC pin of the third converting chip U683 after being combined. The PFM pin of the third converting chip U683 is also externally connected with a resistor R3789, one end of the resistor R3789 is electrically connected between the resistor R3788 and the PFM pin of the third converting chip U683, and the other end is grounded. And a capacitor C5276 is electrically connected between the SS pin of the third conversion chip U683 and the AGND pin of the third conversion chip U683.

The fourth capacitor comprises a capacitor C5283, a capacitor C5282, a capacitor C5279, a capacitor C5280, a capacitor C5278 and a capacitor C5281, one end of the capacitor C5283, the capacitor C5282, the capacitor C5279, the capacitor C5280, the capacitor C5278 and the capacitor C5281 after being connected in parallel is electrically connected with the output end of the third inductor L67 and outputs 3.3V voltage, and the other end of the capacitor C5280, the capacitor C5278 and the capacitor C5281 are grounded. Five LX pins of the third conversion chip U683 are arranged, and all the five LX pins are electrically connected to the input end of the third inductor L67. A capacitor C5277 is externally connected to the BOOT pin of the third converting chip U683, and the other end of the capacitor C5277 is electrically connected to the LX pin of the third converting chip U683 and the input end of the third inductor L67. The FB pin of the third switching chip U683 is externally connected with a resistor R3790 and a resistor R3791 having one combined end, wherein the other end of the resistor R3790 is electrically connected to the output end of the third inductor L67, and the other end of the resistor R3791 is grounded. The POK pin of the third conversion chip U683 is externally connected with a resistor R244, and the other end of the resistor R244 is used for outputting 3.3V voltage.

The power input pins of the fourth conversion chip U33C include a PVIN1 pin, a PVIN2 pin and a PVIN3 pin, the PVIN1 pin, the PVIN2 pin and the PVIN3 pin are all connected to the 3.3V voltage converted by the third conversion chip U683, the PVIN1 pin is further externally connected with a capacitor C590 and a capacitor C587 which are arranged in parallel, and the other ends of the capacitor C590 and the capacitor C587 which are arranged in parallel are grounded. The pin PVIN2 is externally connected with a capacitor C594 and a capacitor C593 which are arranged in parallel, the other ends of the capacitor C590 and the capacitor C587 which are arranged in parallel are grounded, the pin PVIN3 is externally connected with a capacitor C605 and a capacitor C599 which are arranged in parallel, and the other ends of the capacitor C605 and the capacitor C599 which are arranged in parallel are grounded.

The eighth capacitor comprises a capacitor C97, a capacitor C98, a capacitor C104 and a capacitor C103, wherein one end of the capacitor C97, one end of the capacitor C98, one end of the capacitor C104 and one end of the capacitor C103 which are arranged in parallel are electrically connected with the output end of the seventh inductor L26, and the other end of the capacitor C38103 is grounded.

The SHDN-B pin of the fifth conversion chip U686 is externally connected with a resistor R3806.

Here, it should be noted that in one possible implementation, the level conversion chip further includes an eighth conversion chip U33B, where the vldo 1 pin, the vldo 23 pin, and the vldo 45 pin of the eighth conversion chip U33B are all connected to the 3.3V voltage output by the third conversion chip U683. And the vldo 1 pin of the eighth conversion chip U33B is further externally connected with a capacitor C691, the vldo 23 pin of the eighth conversion chip U33B is further externally connected with a capacitor C598, and the vldo 45 pin of the eighth conversion chip U33B is further externally connected with a capacitor C578. LDO1, LDO2, LDO3, LDO4 and LDO5 of the eighth conversion chip U33B output voltages of 1.35V, 2.5V, 1.8V and 3.3V, respectively.

As shown in fig. 1, fig. 2, or fig. 9, in a possible implementation manner, the level conversion chip further includes a sixth conversion chip U687, a capacitor C5308 is externally connected to a VIN pin of the sixth conversion chip U687, and the VIN pin of the sixth conversion chip U687 is used for accessing a voltage of 1.8V. And the VOUT pin of the sixth conversion chip U687 is externally connected with more than two capacitors connected in parallel and then outputs 1.35V voltage to the processor. The VOUT pin of the sixth conversion chip U687 is also connected in series with a third resistor R3810 and a fourth resistor R3808, and the fourth resistor R3808 is grounded. The SET pin of the sixth conversion chip U687 is electrically connected between the third resistor R3810 and the fourth resistor R3808.

Here, it should be noted that, in one possible implementation, two capacitors (C5311 and C5309) are provided externally to the VOUT pin of the sixth conversion chip U687. The SHDN-B pin of the sixth conversion chip U687 is externally connected to a resistor R3809, and the other end of the resistor R3809 is grounded.

As shown in fig. 1, fig. 2, or fig. 10, in a possible implementation, the level conversion chip further includes a seventh conversion chip U684, a VIN pin of the seventh conversion chip U684 is externally connected with a plurality of parallel number capacitors (a capacitor C5293, a capacitor C5294, a capacitor C5295, a capacitor C5696, a capacitor C5297, and a capacitor C5298), and the VIN pin of the seventh conversion chip U684 is configured to receive a voltage of 12V. An eighth inductor L68 connected in series is externally connected to an LX pin of the seventh conversion chip U684, and an output end of the eighth inductor L68 is electrically connected with a plurality of capacitors (a capacitor C5284, a capacitor C5285, a capacitor C5286, a capacitor C5287, a capacitor C5288 and a capacitor C5289) connected in parallel and then outputs 1V voltage to the processor.

Here, it should be noted that, in one possible implementation manner, the last end of the capacitor C5293, the capacitor C5294, the capacitor C5295, the capacitor C5696, the capacitor C5297 and the capacitor C5298 is connected to the VIN pin (the VIN pin includes a VIN1 pin, a VIN2 pin and a VIN3 pin) of the seventh conversion chip U684, and is connected to the 12V voltage, and the other end is connected to the ground. A resistor R3798 is electrically connected between the VIN pin and the TON pin of the seventh conversion chip U684, a capacitor C5299 and a capacitor C5292 which are arranged in parallel are externally connected to the VCC pin of the seventh conversion chip U684, the capacitor C5299 and the capacitor C5292 which are arranged in parallel are connected with 5V voltage, and the other end of the capacitor C5299 and the capacitor C5292 which are arranged in parallel are grounded. A resistor R3793 and a resistor R3794 are electrically connected between the PFM pin of the seventh conversion chip U684 and the VCC pin of the seventh conversion chip U684, one end of the resistor R3794 is electrically connected between the resistor R3793 and the PFM pin of the seventh conversion chip U684, and the other end is grounded. A capacitor C5291 is electrically connected between the SS pin of the seventh conversion chip U684 and the AGND pin of the seventh conversion chip U684. One end of the capacitor C5284, the capacitor C5285, the capacitor C5286, the capacitor C5287, the capacitor C5288 and the capacitor C5289 which are connected in parallel is electrically connected with the output end of the eighth inductor L68 and outputs 1V voltage to the processor, and the other end is grounded. The LX pin of the seventh switching chip U684 has five LX pins each electrically connected to the input terminal of the eighth inductor L68. A capacitor C5290 is externally connected to the BOOT pin of the seventh switching chip U684, and the other end of the capacitor C5290 is electrically connected to the LX pin of the seventh switching chip U684 and the input terminal of the eighth inductor L68. The FB pin of the seventh switching chip U684 is externally connected to a resistor R3795 and a resistor R3796, both ends of which are combined, wherein the other end of the resistor R3706 is electrically connected to the output end of the eighth inductor L68, and the other end of the resistor R3795 is grounded. A resistor R294 and a resistor R3816 are externally connected to the POK pin of the seventh conversion chip U684, one end of the resistor R294 and one end of the resistor R3816 are combined and then electrically connected to the POK pin of the seventh conversion chip U684, and the other end of the resistor R294 outputs 3.3V.

As shown in fig. 1, fig. 2, fig. 3, fig. 4, fig. 5, fig. 6, fig. 7, fig. 8, fig. 9, or fig. 10, to sum up, the security isolation and information interaction system according to the embodiment of the present application inputs a 12V voltage through the power input module, and is connected to each level conversion chip through the connector in the power input module. The first conversion chip U682 receives the 12V voltage of the power input module and converts the voltage into a 5V voltage to be supplied to the second conversion chip U685, and the second conversion chip U685 receives the 5V voltage and converts the 5V voltage into a 1.1V voltage to be supplied to the PHY. The third conversion chip U683 receives the 12V voltage of the power input module, converts the 12V voltage into a 3.3V voltage, and outputs the 3.3V voltage to the fourth conversion chip U33C, and the fourth conversion chip U33C converts the 3.3V voltage into 0.6V, 1.2V, 1.8V, and 2.5V voltages, so as to supply power to the electronic devices on the board card. And the fifth conversion chip U686 receives the 1.8V voltage converted by the fourth conversion chip U33C, and supplies power to the MinPCIE interface after converting the 1.8V voltage into a 1.5V voltage. The sixth conversion chip U687 also receives the 1.8V voltage converted by the fourth conversion chip U33C, and converts the 1.8V voltage into a 1.35V voltage to supply power to the processor. The seventh conversion chip U684 receives the 12V voltage from the power input block and asserts the 1V voltage to the processor.

In one possible implementation, the memory adopts 4 DDR4 memory granules with 8 bits and 1GB capacity, and the processor and the memory granules are connected through a DDR4 bus.

In one possible implementation, the NOR flash memory chips are 1 128MB NOR flash memory, and are connected to the processor through the IFC local bus, and the NAND flash memory chips are 1GBNAND flash memory.

In one possible implementation, there are 6 ethernet interfaces, two COMBOSFP optical ports, and the PHY includes 2 single-port PHYs and 1 4-port PHY. The 2 single port PHYs and the processor are connected by an RGMI bus and each output 1 ethernet interface and 1 COMBOSFP optical port. The 4-port PHY is connected to the processor through a QSGMII bus, and the 4-port PHY outputs to a 4-way ethernet interface.

In one possible implementation, the debug port of the processor and the processor are connected via a JTAG bus.

In a possible implementation manner, the board card is further provided with a clock generator, and the clock generator produces 6 paths of 100M check clocks to supply to the processor and the PCIE interface.

In a possible implementation manner, a real-time clock chip is further arranged on the board card and used for timing.

In a possible implementation manner, a system debug port, RS232 level, is provided on the board.

In one possible implementation, a temperature sensor is disposed on the board card and is used for detecting the temperature of the processor and the board card.

In a possible implementation manner, the board card is further provided with a 4G module for wireless communication.

In a possible implementation manner, a network transformer is further disposed on the board card to isolate the PHY and the network signal.

Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A security isolation and information interaction system, comprising:

a board card;

the board card is an ARM board card;

the board card is provided with a processor and an electronic device;

the electronic device comprises a memory, a storage module, a USB interface, a PCIE module, a network port, a Console port and an SATA interface;

the level shifter chip is provided with a plurality of output ends, and the plurality of output ends of the level shifter chip are respectively electrically connected with the electronic devices on the main board card and used for providing corresponding driving voltages for the electronic devices.

2. The system for security isolation and information interaction according to claim 1, wherein the board card is further provided with a PHY;

3. The security isolation and information interaction system of claim 2, wherein the level conversion chip comprises a first conversion chip and a second conversion chip;

4. The system of claim 1, wherein the level shifting chip further comprises a third shifting chip, a fourth shifting chip and a fifth shifting chip

5. The system according to claim 4, wherein the level conversion chip further comprises a sixth conversion chip;

6. The system according to claim 1, wherein the level conversion chip further comprises a seventh conversion chip;

7. The system for security isolation and information interaction according to claim 1, wherein the memory employs 4 DDR4 memory particles with 8-bit 1GB capacity;

the processor and the memory grain are connected through a DDR4 bus.

8. The system according to claim 1, wherein the NOR flash memory chip is a 128MB NOR flash memory chip connected to the processor via an IFC local bus;

the NAND flash memory chip is 1GBNAND flash memory with 1 chip.

9. The system according to claim 1, wherein the EMMC chip is 1 EMMC of 16GB and is expandable to 64 GB.

10. The system for security isolation and information interaction according to claim 2, wherein there are 6 ethernet interfaces and two COMBOSFP optical ports;

the PHYs comprise 2 single-port PHYs and 1 4-port PHY;

the 4-port PHY is connected with the processor through a QSGMII bus, and the 4-port PHY outputs to 4 paths of Ethernet interfaces.