CN214756710U - High-definition digital ground wave signal receiver with network port - Google Patents
High-definition digital ground wave signal receiver with network port Download PDFInfo
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- CN214756710U CN214756710U CN202120620938.9U CN202120620938U CN214756710U CN 214756710 U CN214756710 U CN 214756710U CN 202120620938 U CN202120620938 U CN 202120620938U CN 214756710 U CN214756710 U CN 214756710U
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Abstract
The utility model discloses a take net gape high definition digit ground wave signal receiver, including main control chip, memory chip, communication interface, level shift circuit, clock signal circuit, antenna control circuit, radio reception tuning interface, USB interface, multimedia port, audio output port and network interface. The UI design icon of the utility model is popular and easy to understand and simple to operate; the method supports multiple IPTV protocols and supports the USB to import an IPTV program list in the format of M3U or TXT file; the storage of ultra-large channels is supported, 5000 effective channels can be stored, and a signal locking lamp is arranged on the front panel for indicating; support for Electronic Program Guide (EPG) functionality; the ultra-low threshold receiving, high sensitivity and sensitive signal detection are carried out on DVB-T/T2 signals; supporting the multimedia playing, recording and playing and upgrading of the U disk; the use cost of the user is reduced, and the resource waste is avoided.
Description
Technical Field
The utility model relates to a satellite communication system technical field specifically is a take net gape high definition digit ground wave signal receiver.
Background
The receiver is a circuit system having the following components: antenna, filter, amplifier, A/D converter. The navigation positioning signal sent by the GPS satellite is an information resource which can be shared by countless users. For a wide range of users on land, sea and space, the GPS signals can be used for navigation positioning measurement at any time as long as the users have receiving devices, i.e., GPS signal receivers, capable of receiving, tracking, transforming and measuring the GPS signals. The DVB-T2 terrestrial wave receiver operating system is a simple ECOS system, has low requirements on hardware configuration and only aims at signal decoding of DVB-T/T2. However, with the development of networks, the content of network information is rich, and the propagation of learning materials, such as the IPTV programs owned by the clients and some network videos self-made, cannot be watched by the traditional DVB-T/T2 receivers.
Although the Android + DVB receiver exists at present, the receiver is a player based on an Android system, and the hardware configuration is very high, so the cost is relatively high.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a take net gape high definition digit ground wave signal receiver to solve the problem that proposes among the above-mentioned background art.
In order to solve the technical problem, the utility model provides a following technical scheme: a high-definition digital ground wave signal receiver with a network port comprises a main control chip, a storage chip, a communication interface, a level conversion circuit, a clock signal circuit, an antenna control circuit, a radio tuning interface, a USB interface, a multimedia port, an audio output port and a network interface, wherein the output end of the main control chip is electrically connected with the storage chip, the communication interface, the level conversion circuit, the clock signal circuit, the antenna control circuit, the radio tuning interface, the USB interface, the multimedia port, the audio output port and the input end of the network interface.
Furthermore, the level shift circuit includes a +12V shift circuit, a +5V shift circuit, a +3.3V shift circuit, and a +1.5V _ +1.8V shift circuit, an output terminal of the +12V shift circuit is electrically connected to an input terminal of the +5V shift circuit, an output terminal of the +5V shift circuit is electrically connected to an input terminal of the +3.3V shift circuit, and an output terminal of the +3.3V shift circuit is electrically connected to an input terminal of the +1.5V _ +1.8V shift circuit.
Further, the +12V conversion circuit includes a first relay, the 3 pins of the first relay are grounded, the 1 pin of the first relay is connected in series with the 1 pin of a second relay, the 2 pins of the first relay are connected in series with the 2 pins of the second relay, the second relay is connected in parallel with a first capacitor, the first capacitor is connected in parallel with a first electrolytic capacitor, the first electrolytic capacitor is connected in parallel with a second capacitor, the second capacitor is connected in series with a +12V voltage and a first resistor, the first resistor is connected in series with a +5V voltage, the first relay is J1, the second relay is J6, the first capacitor is C1, the second capacitor is C2, and the first electrolytic capacitor is R2.
Further, the +5V conversion circuit includes a first conversion chip, wherein 2 pins of the first conversion chip are grounded, 4 pins of the first conversion chip are connected in series with a second resistor, 5 pins of the first conversion chip are connected in series with the second resistor and a third capacitor, the third capacitor and a fourth capacitor are connected in parallel, one end of the fourth capacitor is grounded, one end of the fourth capacitor is connected in series with a +12V voltage, 1 pin of the first conversion chip is connected in series with a fifth capacitor, the fifth capacitor is connected in series with 6 pins of the first conversion chip, 6 pins of the first conversion chip are connected in series with a first electromagnetic inductor, the first electromagnetic inductor is connected in parallel with a sixth capacitor, the sixth capacitor is connected in parallel with a seventh capacitor, the seventh capacitor is connected in parallel with a third resistor, the third resistor is connected in parallel with an eighth capacitor, and the eighth capacitor is connected in parallel with a ninth capacitor, one end of the ninth capacitor is grounded, one end of the ninth capacitor is connected with +5V voltage in series, the first conversion chip is U, 10, the third capacitor is C75, the fourth capacitor is C39, the fifth capacitor is C40, the sixth capacitor is C79, the seventh capacitor is C44, the eighth capacitor is C52, the ninth capacitor is C82, the second resistor is R55, the third resistor is R56, and the first electromagnetic inductor is L1.
Further, the +3.3V conversion circuit includes a second conversion chip, where pin 1 of the second conversion chip is connected in series with a fourth resistor and a tenth capacitor, the tenth capacitor is connected in series with pin 2 of the second conversion chip, the fourth resistor is connected in series with pin 4 of the second conversion chip, pin 4 of the second conversion chip is connected in series with an eleventh capacitor, the eleventh capacitor is connected in parallel with a twelfth capacitor, one end of the twelfth capacitor is grounded, one end of the twelfth capacitor is connected in series with a +5V voltage, pin 3 of the second conversion chip is connected in series with a second electromagnetic inductor, the second electromagnetic inductor is connected in series with a thirteenth capacitor, the thirteenth capacitor is connected in parallel with a fourteenth capacitor, the fourteenth capacitor is connected in parallel with a fifteenth capacitor, the fifteenth capacitor is connected in series with a fourth resistor, and the fourth resistor is connected in parallel with a sixteenth capacitor, one end of the sixteenth capacitor is connected in series with a +3.3V voltage, one end of the sixteenth capacitor is connected in series with a pin 5 of the second conversion chip, a pin 5 of the second conversion chip is connected in series with a fifth resistor, one end of the fifth resistor is connected to the ground, the tenth capacitor is C203, the eleventh capacitor is C200, the twelfth capacitor is C27, the thirteenth capacitor is C30, the fourteenth capacitor is C28, the fifteenth capacitor is C29, the sixteenth capacitor is C32, the fourth resistor is R47, the second electromagnetic inductance is L8, and the fifth resistor is R44.
Further, the 1.5V _ +1.8V conversion circuit includes a third conversion chip, a pin 1 of the third conversion chip is grounded, a pin 2 of the third conversion chip is connected in series with a seventeenth capacitor, the seventeenth capacitor is connected in parallel with an eighteenth capacitor, one end of the eighteenth capacitor is grounded, the other end of the eighteenth capacitor is connected in series with a voltage 1.5V _ +1.8V, a pin 3 of the third conversion chip is connected in series with a voltage +3.3V and a nineteenth capacitor, one end of the nineteenth capacitor is grounded, a pin 4 of the third conversion chip is connected in series with a pin 2, the third conversion chip is U4, the seventeenth capacitor is C65, the eighteenth capacitor is C74, and the nineteenth capacitor is C26.
Compared with the prior art, the utility model discloses the beneficial effect who reaches is:
1. the UI design icon of the utility model is popular and easy to understand and simple to operate; supporting various IPTV protocols, MEGOGO, YOUTUBE and Weather query; the IPTV program list supporting USB import of M3U or TXT file format; the storage of ultra-large channels is supported, 5000 effective channels can be stored, four-digit 32 x 10mm LED nixie tubes display is realized, and a signal locking lamp is arranged on the front panel for indication; support for Electronic Program Guide (EPG) functionality; the ultra-low threshold receiving, high sensitivity and sensitive signal detection are carried out on DVB-T/T2 signals; supporting the multimedia playing, recording and playing and upgrading of the U disk; the use cost of the user is reduced, and the resource waste is avoided.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a block diagram of the overall main control circuit of the present invention;
FIG. 2 is a block diagram of the overall power supply circuit of the present invention;
fig. 3 is a circuit diagram of the +12V conversion circuit of the present invention;
fig. 4 is a circuit diagram of the +5V conversion circuit of the present invention;
fig. 5 is a circuit diagram of the +3.3V conversion circuit of the present invention;
FIG. 6 is a circuit diagram of the +1.5V _ +1.8V conversion circuit of the present invention;
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1-6, the present invention provides a technical solution: a high-definition digital ground wave signal receiver with a network port comprises a main control chip, a storage chip, a communication interface, a level conversion circuit, a clock signal circuit, an antenna control circuit, a radio tuning interface, a USB interface, a multimedia port, an audio output port and a network interface, wherein the output end of the main control chip is electrically connected with the storage chip, the communication interface, the level conversion circuit, the clock signal circuit, the antenna control circuit, the radio tuning interface, the USB interface, the multimedia port, the audio output port and the input end of the network interface.
The level conversion circuit comprises a +12V conversion circuit, a +5V conversion circuit, a +3.3V conversion circuit and a +1.5V _ +1.8V conversion circuit, wherein the output end of the +12V conversion circuit is electrically connected with the input end of the +5V conversion circuit, the output end of the +5V conversion circuit is electrically connected with the input end of the +3.3V conversion circuit, and the output end of the +3.3V conversion circuit is electrically connected with the input end of the +1.5V _ +1.8V conversion circuit.
The +12V conversion circuit comprises a first relay, wherein 3 pins of the first relay are grounded, 1 pin of the first relay is connected with 1 pin of a second relay in series, 2 pins of the first relay are connected with 2 pins of the second relay in series, the second relay is connected with a first capacitor in parallel, the first capacitor is connected with a first electrolytic capacitor in parallel, the first electrolytic capacitor is connected with a second capacitor in parallel, the second capacitor is connected with +12V voltage and a first resistor in series, the first resistor is connected with +5V voltage in series, the first relay is J1, the second relay is J6, the first capacitor is C1, the second capacitor is C2, and the first electrolytic capacitor is R2.
The +5V conversion circuit comprises a first conversion chip, wherein 2 pins of the first conversion chip are grounded, 4 pins of the first conversion chip are connected with a second resistor in series, 5 pins of the first conversion chip are connected with the second resistor and a third capacitor in series, the third capacitor and a fourth capacitor are connected in parallel, one end of the fourth capacitor is grounded, one end of the fourth capacitor is connected with a +12V voltage in series, 1 pin of the first conversion chip is connected with a fifth capacitor in series, the fifth capacitor is connected with 6 pins of the first conversion chip in series, 6 pins of the first conversion chip are connected with a first electromagnetic inductor in series, the first electromagnetic inductor is connected with a sixth capacitor in parallel, the sixth capacitor is connected with a seventh capacitor in parallel, the seventh capacitor is connected with a third resistor in parallel, the third resistor is connected with an eighth capacitor in parallel, and the eighth capacitor is connected with a ninth capacitor in parallel, one end of the ninth capacitor is grounded, one end of the ninth capacitor is connected with +5V voltage in series, the first conversion chip is U, 10, the third capacitor is C75, the fourth capacitor is C39, the fifth capacitor is C40, the sixth capacitor is C79, the seventh capacitor is C44, the eighth capacitor is C52, the ninth capacitor is C82, the second resistor is R55, the third resistor is R56, and the first electromagnetic inductor is L1.
The +3.3V conversion circuit comprises a second conversion chip, wherein a pin 1 of the second conversion chip is connected with a fourth resistor and a tenth capacitor in series, the tenth capacitor is connected with a pin 2 of the second conversion chip in series, the fourth resistor is connected with a pin 4 of the second conversion chip in series, a pin 4 of the second conversion chip is connected with an eleventh capacitor in series, the eleventh capacitor is connected with a twelfth capacitor in parallel, one end of the twelfth capacitor is grounded, one end of the twelfth capacitor is connected with a +5V voltage in series, a pin 3 of the second conversion chip is connected with a second electromagnetic inductor in series, the second electromagnetic inductor is connected with a thirteenth capacitor in series, the thirteenth capacitor is connected with a fourteenth capacitor in parallel, the fourteenth capacitor is connected with a fifteenth capacitor in parallel, the fifteenth capacitor is connected with a fourth resistor in series, and the fourth resistor is connected with a sixteenth capacitor in parallel, one end of the sixteenth capacitor is connected in series with a +3.3V voltage, one end of the sixteenth capacitor is connected in series with a pin 5 of the second conversion chip, a pin 5 of the second conversion chip is connected in series with a fifth resistor, one end of the fifth resistor is connected to the ground, the tenth capacitor is C203, the eleventh capacitor is C200, the twelfth capacitor is C27, the thirteenth capacitor is C30, the fourteenth capacitor is C28, the fifteenth capacitor is C29, the sixteenth capacitor is C32, the fourth resistor is R47, the second electromagnetic inductance is L8, and the fifth resistor is R44.
The 1.5V _ +1.8V conversion circuit comprises a third conversion chip, wherein a pin 1 of the third conversion chip is grounded, a pin 2 of the third conversion chip is connected with a seventeenth capacitor in series, the seventeenth capacitor is connected with an eighteenth capacitor in parallel, one end of the eighteenth capacitor is grounded, the other end of the eighteenth capacitor is connected with a voltage 1.5V _ +1.8V in series, a pin 3 of the third conversion chip is connected with a voltage +3.3V and a nineteenth capacitor in series, one end of the nineteenth capacitor is grounded, a pin 4 of the third conversion chip is connected with a pin 2 in series, the third conversion chip is U4, the seventeenth capacitor is C65, the eighteenth capacitor is C74, and the nineteenth capacitor is C26.
The specific implementation mode is as follows: when the system is used, a user can import an IPTV program list in an M3U or TXT file format through the USB; the network or USB WIFI DONGLE is inserted into the corresponding server, so that the network video resources can be watched, and the operation is simple; the user can watch the DVB-T/T2 programs by using the low-cost DVB-T/T2 receiver, and can also watch network video resources such as IPTV, MEGOGO, YOUTUBE and the like; the application range of the client private IPTV protocol supported by the IPTV is very wide; the user does not need to purchase an Android + DVB receiver at a higher price or a common DVB-T/T2 receiver and a player of an Android system, the two methods can realize watching of DVB-T/T2 and network video resources, but the price of the two methods is higher, and the switching of the two methods frequently requires manual dialing and plugging of connecting lines; the HDTR800 of the DVB-T2 high-definition digital terrestrial signal receiver with the network port is developed based on an ECOS system, has low hardware configuration and low cost, is provided with 100MPHY inside a chip, and can realize the DVB-T/T2 function by adding TUNER (MXL 608). The DVB-T/T2 and network video resource sharing can be realized conveniently and at low cost by the end user; the product meets the international standard < ETSI EN 3302755 V1.4.1(2015-07) >, < ETSI TS 102831 V1.2.1(2012-08) >; the method supports the directional access of LAN (10/100Mbps) or USB WIFI DONGLE to the Internet; UI design icons are popular and easy to understand, and the operation is simple; supporting various IPTV protocols, MEGOGO, YOUTUBE and Weather query; the IPTV program list supporting USB import of M3U or TXT file format; the storage of ultra-large channels is supported, 5000 effective channels can be stored, four-digit 32 x 10mm LED nixie tubes display is realized, and a signal locking lamp is arranged on the front panel for indication; support for Electronic Program Guide (EPG) functionality; the ultra-low threshold receiving, high sensitivity and sensitive signal detection are carried out on DVB-T/T2 signals; supporting the multimedia playing, recording and playing and upgrading of the U disk; HDMI version 1.4 is supported.
The utility model discloses a theory of operation:
referring to the attached fig. 1-6 of the specification, the UI design icon of the present invention is popular and easy to understand and operate; supporting various IPTV protocols, MEGOGO, YOUTUBE and Weather query; the IPTV program list supporting USB import of M3U or TXT file format; the storage of ultra-large channels is supported, 5000 effective channels can be stored, four-digit 32 x 10mm LED nixie tubes display is realized, and a signal locking lamp is arranged on the front panel for indication; support for Electronic Program Guide (EPG) functionality; the ultra-low threshold receiving, high sensitivity and sensitive signal detection are carried out on DVB-T/T2 signals; supporting the multimedia playing, recording and playing and upgrading of the U disk; the use cost of the user is reduced, and the resource waste is avoided.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing embodiments, or equivalents may be substituted for elements thereof. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. The utility model provides a take net gape high definition digit ground wave signal receiver, includes main control chip, memory chip, communication interface, level shift circuit, clock signal circuit, antenna control circuit, radio reception tuning interface, USB interface, multimedia port, audio output port and network interface, its characterized in that: the output end of the main control chip is electrically connected with the input ends of the storage chip, the communication interface, the level conversion circuit, the clock signal circuit, the antenna control circuit, the radio tuning interface, the USB interface, the multimedia port, the audio output port and the network interface.
2. The network-port-equipped high-definition digital terrestrial signal receiver according to claim 1, wherein: the level conversion circuit comprises a +12V conversion circuit, a +5V conversion circuit, a +3.3V conversion circuit and a +1.5V _ +1.8V conversion circuit, wherein the output end of the +12V conversion circuit is electrically connected with the input end of the +5V conversion circuit, the output end of the +5V conversion circuit is electrically connected with the input end of the +3.3V conversion circuit, and the output end of the +3.3V conversion circuit is electrically connected with the input end of the +1.5V _ +1.8V conversion circuit.
3. The network-port-equipped high-definition digital terrestrial signal receiver according to claim 2, wherein: the +12V conversion circuit comprises a first relay, wherein 3 pins of the first relay are grounded, 1 pin of the first relay is connected with 1 pin of a second relay in series, 2 pins of the first relay are connected with 2 pins of the second relay in series, the second relay is connected with a first capacitor in parallel, the first capacitor is connected with a first electrolytic capacitor in parallel, the first electrolytic capacitor is connected with a second capacitor in parallel, the second capacitor is connected with +12V voltage and a first resistor in series, the first resistor is connected with +5V voltage in series, the first relay is J1, the second relay is J6, the first capacitor is C1, the second capacitor is C2, and the first electrolytic capacitor is R2.
4. The network-port-equipped high-definition digital terrestrial signal receiver according to claim 2, wherein: the +5V conversion circuit comprises a first conversion chip, wherein 2 pins of the first conversion chip are grounded, 4 pins of the first conversion chip are connected with a second resistor in series, 5 pins of the first conversion chip are connected with the second resistor and a third capacitor in series, the third capacitor and a fourth capacitor are connected in parallel, one end of the fourth capacitor is grounded, one end of the fourth capacitor is connected with a +12V voltage in series, 1 pin of the first conversion chip is connected with a fifth capacitor in series, the fifth capacitor is connected with 6 pins of the first conversion chip in series, 6 pins of the first conversion chip are connected with a first electromagnetic inductor in series, the first electromagnetic inductor is connected with a sixth capacitor in parallel, the sixth capacitor is connected with a seventh capacitor in parallel, the seventh capacitor is connected with a third resistor in parallel, the third resistor is connected with an eighth capacitor in parallel, and the eighth capacitor is connected with a ninth capacitor in parallel, one end of the ninth capacitor is grounded, one end of the ninth capacitor is connected with +5V voltage in series, the first conversion chip is U, 10, the third capacitor is C75, the fourth capacitor is C39, the fifth capacitor is C40, the sixth capacitor is C79, the seventh capacitor is C44, the eighth capacitor is C52, the ninth capacitor is C82, the second resistor is R55, the third resistor is R56, and the first electromagnetic inductor is L1.
5. The network-port-equipped high-definition digital terrestrial signal receiver according to claim 2, wherein: the +3.3V conversion circuit comprises a second conversion chip, wherein a pin 1 of the second conversion chip is connected with a fourth resistor and a tenth capacitor in series, the tenth capacitor is connected with a pin 2 of the second conversion chip in series, the fourth resistor is connected with a pin 4 of the second conversion chip in series, a pin 4 of the second conversion chip is connected with an eleventh capacitor in series, the eleventh capacitor is connected with a twelfth capacitor in parallel, one end of the twelfth capacitor is grounded, one end of the twelfth capacitor is connected with a +5V voltage in series, a pin 3 of the second conversion chip is connected with a second electromagnetic inductor in series, the second electromagnetic inductor is connected with a thirteenth capacitor in series, the thirteenth capacitor is connected with a fourteenth capacitor in parallel, the fourteenth capacitor is connected with a fifteenth capacitor in parallel, the fifteenth capacitor is connected with a fourth resistor in series, and the fourth resistor is connected with a sixteenth capacitor in parallel, one end of the sixteenth capacitor is connected in series with a +3.3V voltage, one end of the sixteenth capacitor is connected in series with a pin 5 of the second conversion chip, a pin 5 of the second conversion chip is connected in series with a fifth resistor, one end of the fifth resistor is connected to the ground, the tenth capacitor is C203, the eleventh capacitor is C200, the twelfth capacitor is C27, the thirteenth capacitor is C30, the fourteenth capacitor is C28, the fifteenth capacitor is C29, the sixteenth capacitor is C32, the fourth resistor is R47, the second electromagnetic inductance is L8, and the fifth resistor is R44.
6. The network-port-equipped high-definition digital terrestrial signal receiver according to claim 2, wherein: the 1.5V _ +1.8V conversion circuit comprises a third conversion chip, wherein a pin 1 of the third conversion chip is grounded, a pin 2 of the third conversion chip is connected with a seventeenth capacitor in series, the seventeenth capacitor is connected with an eighteenth capacitor in parallel, one end of the eighteenth capacitor is grounded, the other end of the eighteenth capacitor is connected with a voltage 1.5V _ +1.8V in series, a pin 3 of the third conversion chip is connected with a voltage +3.3V and a nineteenth capacitor in series, one end of the nineteenth capacitor is grounded, a pin 4 of the third conversion chip is connected with a pin 2 in series, the third conversion chip is U4, the seventeenth capacitor is C65, the eighteenth capacitor is C74, and the nineteenth capacitor is C26.
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| CN202120620938.9U CN214756710U (en) | 2021-03-27 | 2021-03-27 | High-definition digital ground wave signal receiver with network port |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114443541A (en) * | 2022-01-17 | 2022-05-06 | 北京东大金智科技有限公司 | Safety isolation and information interaction system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114443541A (en) * | 2022-01-17 | 2022-05-06 | 北京东大金智科技有限公司 | Safety isolation and information interaction system |
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