CN114425462B

CN114425462B - Microfluidic chip and preparation method thereof

Info

Publication number: CN114425462B
Application number: CN202011183044.4A
Authority: CN
Inventors: 邓睿君; 郭怡彤; 丁丁
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-10-29
Filing date: 2020-10-29
Publication date: 2023-10-31
Anticipated expiration: 2040-10-29
Also published as: CN114425462A

Abstract

The microfluidic chip comprises a first substrate and a second substrate which are oppositely arranged, wherein one side of the first substrate facing the second substrate comprises a plurality of mutually cascaded shift register units, a connecting circuit and a plurality of mutually spaced electrode pairs, and the output end of at least one shift register unit is connected with at least one electrode pair through the connecting circuit; the side of the second substrate facing the first substrate comprises micro-channels for accommodating liquid drops, and the orthographic projections of the electrode pairs on the first substrate are symmetrically distributed on two sides of the orthographic projections of the micro-channels on the first substrate. According to the micro-fluidic chip circuit, the plurality of cascaded shift register units and the connecting circuit are integrated on the first substrate, so that the integration and miniaturization of the micro-fluidic chip are realized, the constraints of a high-voltage power supply and redundant circuits are reduced, and the high integration of the micro-fluidic chip circuit is effectively realized.

Description

Microfluidic chip and preparation method thereof

Technical Field

The disclosure relates to the field of microfluidic technology in, but not limited to, micro total analysis, and in particular relates to a microfluidic chip and a preparation method thereof.

Background

Microfluidic technology (Microfluidics) is a technology that precisely controls and manipulates microscale fluids, by which researchers can integrate basic operating units for sample preparation, reaction, separation, detection, etc. onto a centimeter-scale chip. The technology is generally applied to the analysis process of trace medicines in the fields of biology, chemistry, pharmacy and the like, and mainly relates to the transportation, mixing and the like of trace reagents. The technology has important significance for the development of fields such as biomedical treatment, drug diagnosis, food sanitation, environmental monitoring, molecular biology and the like.

Because the operations such as separation and sample injection of the conventional microfluidic chip all need to be externally added with a high-voltage power supply, the portable requirement of an analysis instrument cannot be met.

Disclosure of Invention

The embodiment of the disclosure provides a microfluidic chip and a preparation method thereof, which can improve the integration and portability of the microfluidic chip.

The embodiment of the disclosure provides a microfluidic chip, which comprises a first substrate and a second substrate which are oppositely arranged, wherein: the side of the first substrate facing the second substrate comprises a plurality of mutually cascaded shift register units, a connecting circuit and a plurality of electrode pairs which are arranged at intervals, and the output end of at least one shift register unit is connected with at least one electrode pair through the connecting circuit; the side of the second substrate facing the first substrate comprises micro-channels for containing liquid drops, and the front projections of the electrode pairs on the first substrate are symmetrically distributed on two sides of the front projections of the micro-channels on the first substrate.

In an exemplary embodiment, the micro-channel comprises a sample injection channel and a separation channel which are mutually intersected, wherein a sample liquid storage tank and a sample waste liquid storage tank are arranged at two ends of the sample injection channel, and a buffer liquid storage tank and a buffer waste liquid storage tank are arranged at two ends of the separation channel; the electrode pairs comprise at least two groups, wherein the orthographic projections of one group of electrode pairs on the first substrate are symmetrically distributed on two sides of the orthographic projections of the sample injection channel on the first substrate; the other group of the electrode pairs are in orthographic projection on the first substrate and are symmetrically distributed on two sides of orthographic projection of the separation channel on the first substrate; the shift register unit comprises at least two groups, wherein the signal output end of one group of shift register unit is connected with one group of electrode pairs, and the signal output end of the other group of shift register unit is connected with the other group of electrode pairs.

In one exemplary embodiment, the shift register unit includes: an input sub-circuit, an output sub-circuit, a first control sub-circuit, a second control sub-circuit, and a pull-up control sub-circuit, wherein: the input sub-circuit is respectively connected with a first clock signal end, a signal input end and a first node and is used for providing signals of the signal input end for the first node under the control of the first clock signal end; the output sub-circuit is respectively connected with the first node, the second reference voltage end, the second clock signal end and the signal output end and is used for providing signals of the second reference voltage end or the second clock signal end for the signal output end under the control of the first node and the second node; the first control sub-circuit is respectively connected with the first clock signal end, the first reference voltage end and the second node and is used for providing signals of the first reference voltage end for the second node under the control of the first clock signal end; the second control sub-circuit is respectively connected with the first clock signal end, the first node and the second node and is used for providing signals of the first clock signal end for the second node under the control of the first node; the pull-up control sub-circuit is respectively connected with the second reference voltage end, the second clock signal end, the first node and the second node, and is used for providing signals of the second reference voltage end for the first node under the control of the second node and the second clock signal end.

In one exemplary embodiment, the input sub-circuit includes a first transistor, the output sub-circuit includes a second transistor, a third transistor, a first capacitance, and a second capacitance, the first control sub-circuit includes a fourth transistor, the second control sub-circuit includes a fifth transistor, and the pull-up control sub-circuit includes a sixth transistor and a seventh transistor; the grid electrode of the first transistor is connected with the first clock signal end, the first electrode of the first transistor is connected with the signal input end, and the second electrode of the first transistor is connected with the first node; the grid electrode of the second transistor is connected with the first node, the first electrode of the second transistor is connected with the second clock signal end, and the second electrode of the second transistor is connected with the signal output end; a gate of the third transistor is connected to the second node, a first pole of the third transistor is connected to the second reference voltage terminal, and a second pole of the third transistor is connected to the signal output terminal; one end of the first capacitor is connected with the second reference voltage end, and the other end of the first capacitor is connected with the second node; one end of the second capacitor is connected with the signal output end, and the other end of the second capacitor is connected with the first node; the grid electrode of the fourth transistor is connected with the first clock signal end, the first electrode of the fourth transistor is connected with the first reference voltage end, and the second electrode of the fourth transistor is connected with the second node; the grid electrode of the fifth transistor is connected with the first node, the first electrode of the fifth transistor is connected with the first clock signal end, and the second electrode of the fifth transistor is connected with the second node; the grid electrode of the sixth transistor is connected with the second node, the first electrode of the sixth transistor is connected with the second reference voltage end, and the second electrode of the sixth transistor is connected with the first electrode of the seventh transistor; and the grid electrode of the seventh transistor is connected with the second clock signal end, and the second electrode of the seventh transistor is connected with the first node.

In one exemplary embodiment, the first substrate includes a first substrate, a semiconductor layer disposed on the first substrate, a first insulating layer disposed on the semiconductor layer, a first metal layer disposed on the first insulating layer, a second insulating layer disposed on the first metal layer, and a second metal layer disposed on the second insulating layer, a third insulating layer disposed on the second metal layer, and a planarization layer disposed on the third insulating layer, in a plane perpendicular to the first substrate.

In an exemplary embodiment, the semiconductor layer includes an active layer of the first transistor to an active layer of the seventh transistor, wherein: the active layers of the first transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are arranged on one side far away from the active layers of the second transistor and the third transistor, the active layers of the second transistor and the third transistor are connected with each other to form an integral structure, the active layers of the sixth transistor and the seventh transistor are connected with each other to form an integral structure, and the active layers of the fourth transistor and the fifth transistor are connected with each other to form an integral structure.

In one exemplary embodiment, the first metal layer includes: the gate layer of the first transistor to the gate layer of the seventh transistor, the first connection line to the eighth connection line, the first plate of the first capacitor and the third plate of the second capacitor, and the second metal layer includes: the first electrode of the first transistor to the first electrode of the seventh transistor, the second electrode of the first transistor to the second electrode of the seventh transistor, the second electrode plate of the first capacitor, the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first reference voltage terminal, the second reference voltage terminal and the signal output terminal, and the gate of the second transistor includes a first gate and a second gate, wherein: the first connecting line is connected with the first pole of the first transistor and the signal input end, the second connecting line is connected with the grid of the first transistor and the grid of the fourth transistor, the third connecting line is connected with the first pole of the fifth transistor and the first clock signal end, the fourth connecting line is connected with the first pole of the second transistor and the second clock signal end, the fourth connecting line is connected with the grid of the seventh transistor into an integrated structure, the fifth connecting line is connected with the second pole plate of the first capacitor and the first pole of the third transistor, the sixth connecting line is connected with the grid of the fifth transistor and the second pole of the first transistor, the seventh connecting line is connected with the first grid of the second transistor and the grid of the fifth transistor, the grid of the sixth transistor and the first pole plate of the first capacitor are connected into an integrated structure, and the eighth connecting line is connected with the second pole plate of the first capacitor and the third pole plate of the third transistor into an integrated structure.

In an exemplary embodiment, the second insulating layer includes first through eleventh vias, the second metal layer further includes ninth through thirteenth connection lines, and a fourth plate of the second capacitor, wherein: the first pole and the second pole of each transistor are respectively connected with two ends of an active layer of each transistor through a first via hole, the first pole of the first transistor is connected with the signal input end through a second via hole, the sixth connecting wire is connected with the second pole of the first transistor through a third via hole, the ninth connecting wire is connected with the second connecting wire, the first pole of the fifth transistor and the third connecting wire through a fourth via hole, the first clock signal end is connected with the third connecting wire through a fifth via hole, the fourth connecting wire is connected with the second clock signal end through a sixth via hole, the fourth connecting wire is connected with the first pole of the second transistor through a seventh via hole, the tenth connecting wire is connected with the first pole of the sixth transistor and the second reference voltage end through a third via hole, the eleventh connecting wire is connected with the first pole of the fourth transistor and the first reference voltage end through a fourth via hole, the seventh connecting wire and the second pole of the fifth connecting wire are connected with the fifth pole of the third transistor through a fifth via hole, the eighth connecting wire is connected with the fourth pole of the fourth connecting wire and the third connecting wire is connected with the third pole of the fourth connecting wire and the fourth connecting wire is connected with the third pole of the fourth connecting wire.

In an exemplary embodiment, the second metal layer further includes: a start signal input line, a first clock signal line, a second reference voltage line, a first reference voltage line, a connection line, and an electrode pair, wherein: the signal input end of the shift register unit positioned at the first stage is connected with the initial signal input line, the signal input end of the shift register unit positioned at the i-th stage is connected with the signal output end of the shift register unit positioned at the i-1 th stage, i is more than or equal to 2 and less than or equal to N, and N is the total number of stages of the shift register unit; the signal output end of the shift register unit of each stage is connected with at least one electrode pair through a connecting line; the first clock signal end of the shift register unit of each stage is connected with a first clock signal line;

the second clock signal end of the shift register unit of each stage is connected with a second clock signal line; the first reference voltage end of the shift register unit of each stage is connected with a first reference voltage line; the second reference voltage terminal of the shift register unit of each stage is connected to a second reference voltage line.

In an exemplary embodiment, the micro-channels have a width of less than 5000 microns, a depth of 10 to 1000 microns, and a length of 1 to 500 millimeters.

In an exemplary embodiment, each electrode in the pair is less than 1000 microns wide, and the spacing d between adjacent electrodes satisfies: d is less than or equal to V t/2 and d is less than or equal to V/E, wherein V is the migration rate of substances to be separated, t is the clock signal period of the shift register unit, V is the output voltage of the shift register unit, and E is the electric field strength required by separation.

The embodiment of the disclosure also provides a preparation method of the microfluidic chip, which comprises the following steps:

preparing a first substrate and a second substrate respectively, wherein the first substrate comprises a plurality of mutually cascaded shift register units, a connecting circuit and a plurality of electrode pairs which are arranged at intervals, and the output end of at least one shift register unit is connected with at least one electrode pair through the connecting circuit; the second substrate includes a microchannel for receiving a droplet;

and aligning the first substrate with the second substrate, carrying out hot-pressing packaging on the first substrate and the second substrate, and carrying out orthographic projection of the electrode pairs on the first substrate, wherein the electrode pairs are symmetrically distributed on two sides of orthographic projection of the micro-channels on the first substrate.

The embodiment of the disclosure provides a microfluidic chip and a preparation method thereof, and integrates a plurality of cascaded shift register units and connecting lines on a first substrate, so that the integration and miniaturization of the microfluidic chip are realized, the constraints of a high-voltage power supply and redundant circuits are reduced, and the high integration of the microfluidic chip circuits is effectively realized, thereby more simply, conveniently and rapidly separating and analyzing sample components to be detected, and providing a new choice for the hot medical fields such as disease diagnosis, chemical and biological molecular separation analysis, gene sequencing and the like.

Of course, not all of the above-described advantages need be achieved simultaneously in practicing any one of the products or methods of the present disclosure. Additional features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the disclosure. The objectives and other advantages of the disclosed embodiments may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosed embodiments and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain, without limitation, the disclosed embodiments. The shapes and sizes of various components in the drawings are not to scale true, and are intended to be illustrative of the present disclosure.

Fig. 1 is a schematic structural diagram of a microfluidic chip according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a shift register unit shown in FIG. 1;

FIG. 3 is an equivalent circuit diagram of the shift register unit shown in FIG. 2;

FIG. 4 is a timing diagram illustrating operation of the shift register unit shown in FIG. 3;

FIG. 5 is a schematic plan view of the shift register unit shown in FIG. 3;

Fig. 6 is a schematic structural view of the first substrate after forming the semiconductor layer;

FIG. 7 is a schematic structural diagram of the first substrate after forming the first metal layer;

fig. 8 is a schematic structural diagram of the first substrate after forming the second insulating layer;

FIG. 9 is a schematic structural view of a second substrate according to an embodiment of the disclosure;

fig. 10 is a schematic flow chart of a method for manufacturing a microfluidic chip according to an embodiment of the disclosure.

Reference numerals illustrate:

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail hereinafter with reference to the accompanying drawings. Note that embodiments may be implemented in a number of different forms. One of ordinary skill in the art can readily appreciate the fact that the manner and content may be varied into a wide variety of forms without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure should not be construed as being limited to the following description of the embodiments. Embodiments of the present disclosure and features of embodiments may be combined with each other arbitrarily without conflict.

In the drawings, the size of each constituent element, the thickness of a layer, or a region may be exaggerated for clarity. Accordingly, one aspect of the present disclosure is not necessarily limited to this dimension, and the shapes and sizes of the various components in the drawings do not reflect actual proportions. Further, the drawings schematically show ideal examples, and one mode of the present disclosure is not limited to the shapes or numerical values shown in the drawings, and the like.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe positional relationships of constituent elements with reference to the drawings, only for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus are not to be construed as limiting the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the respective constituent elements are described. Therefore, the present invention is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or an electrical connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art in the specific context.

In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using a transistor having opposite polarity, or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in this specification, "source electrode" and "drain electrode" may be exchanged with each other.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit and receive an electric signal between the constituent elements connected. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In the present specification, "parallel" means a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and therefore, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which the angle is 85 ° or more and 95 ° or less.

In this specification, "film" and "layer" may be exchanged with each other. For example, the "conductive layer" may be sometimes replaced with a "conductive film". In the same manner, the "insulating film" may be replaced with the "insulating layer" in some cases.

The term "about" in this disclosure refers to values that are not strictly limited to the limits, but are allowed to fall within the limits of the process and measurement errors.

The embodiment of the disclosure provides a microfluidic chip, which comprises a first substrate and a second substrate which are oppositely arranged, wherein one side of the first substrate facing the second substrate comprises a plurality of mutually cascaded shift register units, a connecting circuit and a plurality of mutually spaced electrode pairs, and the output end of at least one shift register unit is connected with at least one electrode pair through the connecting circuit; the side of the second substrate facing the first substrate comprises micro-channels for containing liquid drops, and the front projection of the electrode pair on the first substrate is symmetrically distributed on two sides of the front projection of the micro-channels on the first substrate.

According to the microfluidic chip provided by the embodiment of the disclosure, through integrating a plurality of cascaded shift register units and connecting lines on the first substrate, the integration and miniaturization of the microfluidic chip are realized, the constraints of a high-voltage power supply and redundant circuits are reduced, and the high integration of the microfluidic chip circuit is effectively realized, so that components of a sample to be detected are separated and analyzed more simply and rapidly, and a new choice is provided for the hot medical fields such as disease diagnosis, chemical and biological molecular separation analysis, gene sequencing and the like.

The technical scheme of the present disclosure is described in detail below through specific embodiments.

Fig. 1 is a schematic structural diagram of a microfluidic chip according to an embodiment of the disclosure, as shown in fig. 1, where the microfluidic chip includes a first substrate and a second substrate that are disposed opposite to each other, and one side of the first substrate facing the second substrate includes a plurality of shift register units 1 cascaded to each other, a connection line 2, and a plurality of electrode pairs 4 arranged at intervals from each other, where an output end of at least one shift register unit 1 is connected to at least one electrode pair 4 through the connection line 2; the side of the second substrate facing the first substrate comprises micro-channels for accommodating liquid drops, and the front projections of the electrode pairs 4 on the first substrate are symmetrically distributed on two sides of the front projections of the micro-channels on the first substrate.

Because the electric field strength required by the separation of substances is fixed, according to E=V/d, E is the electric field strength required by the separation, V is the voltage applied to the two sides of the microelectrode, d is the distance between the microelectrodes, the conventional microfluidic chip does not integrate a shift register unit, a connecting circuit and a plurality of electrode pairs which are arranged at intervals, the electrodes of the microfluidic chip are arranged at the two ends of the whole separation channel, and the required voltage value is very high in order to achieve the separation of the electric field strength; according to the microfluidic chip disclosed by the embodiment of the disclosure, the plurality of mutually cascaded shift register units 1, the connecting circuit 2 and the plurality of mutually spaced electrode pairs 4 are integrated on the first substrate, the plurality of electrode pairs 4 form an array electric field, and as the distance between the electrodes is smaller, the separation electric field strength can be obtained only by smaller voltage, and the automatic progressive movement of the array electrode electric field can be realized by adopting the shift register, so that the sample separation is realized.

In an exemplary embodiment, the micro channel includes a sample introduction channel 80 and a separation channel 81 intersecting each other, a sample liquid reservoir 801 and a sample waste liquid reservoir 802 are provided at both ends of the sample introduction channel 80, and a buffer liquid reservoir 811 and a buffer waste liquid reservoir 812 are provided at both ends of the separation channel 81;

The electrode pairs 4 comprise at least two groups, wherein the orthographic projections of one group of electrode pairs 4 on the first substrate are symmetrically distributed on two sides of the orthographic projections of the sample injection channel 80 on the first substrate; the orthographic projection of the other group of electrode pairs 4 on the first substrate is symmetrically distributed on two sides of the orthographic projection of the separation channel 81 on the first substrate;

the shift register unit 1 comprises at least two groups, the signal output end of one group of shift register unit 1 is connected with one group of electrode pairs 4, and the signal output end of the other group of shift register unit 1 is connected with the other group of electrode pairs 4.

The embodiments of the present disclosure do not limit the number of micro channels, and accordingly, the number of groups of electrode pairs and the number of groups of shift register cells.

In an exemplary implementation, as shown in fig. 2, a shift register unit provided in an embodiment of the present disclosure includes: an input sub-circuit, an output sub-circuit, a first control sub-circuit, a second control sub-circuit, and a pull-up control sub-circuit.

The INPUT sub-circuit is respectively connected with the first clock signal end CK, the signal INPUT end INPUT and the first node N1 and is used for providing a signal of the signal INPUT end INPUT for the first node N1 under the control of the first clock signal end CK;

The OUTPUT sub-circuit is respectively connected with the first node N1, the second node N2, the second reference voltage end VGH, the second clock signal end CKB and the signal OUTPUT end OUTPUT and is used for providing signals of the second reference voltage end VGH or the second clock signal end CKB for the signal OUTPUT end OUTPUT under the control of the first node N1 and the second node N2;

the first control sub-circuit is respectively connected with the first clock signal end CK, the first reference voltage end VGL and the second node N2 and is used for providing a signal of the first reference voltage end VGL for the second node N2 under the control of the first clock signal end CK;

the second control sub-circuit is respectively connected with the first clock signal end CK, the first node N1 and the second node N2 and is used for providing a signal of the first clock signal end CK for the second node N2 under the control of the first node N1;

the pull-up control sub-circuit is respectively connected with the second reference voltage terminal VGH, the second clock signal terminal CKB, the first node N1 and the second node N2, and is configured to provide a signal of the second reference voltage terminal VGH to the first node N1 under the control of the second node N2 and the second clock signal terminal CKB.

In an exemplary embodiment, as shown in fig. 3, the INPUT sub-circuit includes a first transistor M1, a gate of the first transistor M1 is connected to the first clock signal terminal CK, a first pole of the first transistor M1 is connected to the signal INPUT terminal INPUT, and a second pole of the first transistor M1 is connected to the first node N1.

In an exemplary embodiment, as shown in fig. 3, the OUTPUT sub-circuit includes a second transistor M2, a third transistor M3, a first capacitor C1 and a second capacitor C2, the gate of the second transistor M2 is connected to the first node N1, the first pole of the second transistor M2 is connected to the second clock signal terminal CKB, and the second pole of the second transistor M2 is connected to the signal OUTPUT terminal OUTPUT; a gate of the third transistor M3 is connected to the second node N2, a first pole of the third transistor M3 is connected to the second reference voltage terminal VGH, and a second pole of the third transistor M3 is connected to the signal OUTPUT terminal OUTPUT; one end of the first capacitor C1 is connected with the second reference voltage end VGH, and the other end of the first capacitor C1 is connected with the second node N2; one end of the second capacitor C2 is connected to the signal OUTPUT terminal OUTPUT, and the other end of the second capacitor C2 is connected to the first node N1.

In an exemplary embodiment, as shown in fig. 3, the first control sub-circuit includes a fourth transistor M4, a gate of the fourth transistor M4 is connected to the first clock signal terminal CK, a first pole of the fourth transistor M4 is connected to the first reference voltage terminal VGL, and a second pole of the fourth transistor M4 is connected to the second node N2.

In an exemplary embodiment, as shown in fig. 3, the second control sub-circuit includes a fifth transistor M5, a gate of the fifth transistor M5 is connected to the first node N1, a first pole of the fifth transistor M5 is connected to the first clock signal terminal CK, and a second pole of the fifth transistor M5 is connected to the second node N2.

In an exemplary embodiment, as shown in fig. 3, the pull-up control sub-circuit includes a sixth transistor M6 and a seventh transistor M7, the gate of the sixth transistor M6 is connected to the second node N2, the first pole of the sixth transistor M6 is connected to the second reference voltage terminal VGH, and the second pole of the sixth transistor M6 is connected to the first pole of the seventh transistor M7; the gate of the seventh transistor M7 is connected to the second clock signal terminal CKB, and the second pole of the seventh transistor M7 is connected to the first node N1.

An exemplary configuration of the input sub-circuit, the output sub-circuit, the first control sub-circuit, the second control sub-circuit, and the pull-up control sub-circuit is shown in fig. 3. Those skilled in the art will readily appreciate that the implementation of each of the above sub-circuits is not limited thereto, as long as the respective functions thereof can be implemented.

In this embodiment, the transistors M1 to M7 may be N-type thin film transistors or P-type thin film transistors, and the unified process flow may be helpful to improve the yield of the product. For transistors with different doping types, only the effective level of the related signal needs to be adjusted. For example, when all the switching elements are N-type thin film transistors, the effective level is high, and when all the switching elements are P-type thin film transistors, the effective level is low. In addition, considering that the leakage current of the low-temperature polysilicon thin film transistor is small, it is preferable in the embodiments of the present disclosure that all the transistors are low-temperature polysilicon thin film transistors, and the thin film transistor may specifically be a thin film transistor with a bottom gate structure or a thin film transistor with a top gate structure, so long as a switching function can be realized.

The following describes a specific operation process of a shift register unit in a frame period by taking P-type thin film transistors as examples of transistors M1 to M7 in the shift register unit provided in the embodiments of the present disclosure, and combining the shift register unit shown in fig. 3 and the operation timing chart shown in fig. 4. As shown in fig. 3, the shift register unit provided in the embodiment of the present disclosure includes 7 transistor units (M1 to M7), 2 capacitor units (C1 to C2), 3 input terminals (INPUT, CK, CB), 1 OUTPUT terminal (OUTPUT), and 2 power supply terminals (VGH and VGL), wherein the first reference voltage terminal VGL continuously provides a low level signal and the second reference voltage terminal VGH continuously provides a high level signal. The first clock signal terminal CK outputs a periodically varying first clock signal, and the second clock signal terminal CKB outputs a periodically varying second clock signal. The waveforms of the first clock signal and the second clock signal are opposite. The working process comprises the following steps:

in the P1 stage, i.e., the INPUT stage, the signal INPUT terminal INPUT and the first clock signal terminal CK simultaneously INPUT a low level signal, the second clock signal terminal CKB INPUTs a high level signal, the first transistor M1 and the fourth transistor M4 are turned on, the first transistor M1 transmits the low level signal of the signal INPUT terminal INPUT to the first node N1, and the second transistor M2 is turned on, so that the high level signal of the second clock signal terminal CKB is OUTPUT to the OUTPUT terminal OUTPUT; the fifth transistor M5 is turned on, the low level signal of the first reference voltage terminal VGL and the low level signal of the first clock signal terminal CK are input to the second node N2 through the fourth transistor M4 and the fifth transistor M5, respectively, so that the third transistor M3 is turned on, and the high level signal of the second reference voltage terminal VGH is OUTPUT to the signal OUTPUT terminal OUTPUT through the third transistor M3.

A P2 stage, i.e., an output stage, in which the signal INPUT terminal INPUT and the first clock signal terminal CK INPUT a high level signal, the second clock signal terminal CKB INPUTs a low level signal, the first transistor M1 is turned off, the second transistor M2 and the fifth transistor M5 remain turned on due to the bootstrap effect of the second capacitor C2, and the high level signal of the first clock signal terminal CK is output to the second node N2 through the fifth transistor M5, so that the third transistor M3 and the sixth transistor M6 are turned off; meanwhile, the low level signal of the second clock signal terminal CKB is OUTPUT to the OUTPUT terminal OUTPUT of the shift register unit through the second transistor M2.

In the P3 stage, i.e., the buffer stage, the signal INPUT terminal INPUT and the second clock signal terminal CKB INPUT high level signals, the first clock signal terminal CK INPUTs low level signals, the first transistor M1 and the fourth transistor M4 are turned on, and the high level signals of the signal INPUT terminal INPUT are output to the first node N1 through the first transistor M1, so that the second transistor M2 and the fifth transistor M5 are turned off. The low level signal of the first reference voltage terminal VGL is input to the second node N2 through the fourth transistor M4, so that the third transistor M3 and the sixth transistor M6 are turned on, and the OUTPUT terminal OUTPUT of the shift register unit OUTPUTs the high level signal.

In the P4 stage, i.e., the stable stage, the signal INPUT terminal INPUT and the first clock signal terminal CK INPUT the high level signal, the second clock signal terminal CKB INPUTs the low level signal, at this time, the seventh transistor M7 is turned on, the first transistor M1 and the fourth transistor M4 are both turned off, the third transistor M3 and the sixth transistor M6 remain turned on due to the bootstrap effect of the first capacitor C1, the potential of the first node N1 is pulled high, the second transistor M2 remains turned off, and the OUTPUT terminal OUTPUT of the shift register unit OUTPUTs the high level signal.

The stages will repeat the P3 stage and the P4 stage, and output the high level until the signal INPUT terminal INPUT of the shift register unit receives the low level signal again, and output the low level signal in combination with each timing signal.

Fig. 5 is a schematic plan view of a shift register unit according to an exemplary embodiment of the present disclosure. As shown in fig. 5, the shift register unit may include a plurality of transistors, a plurality of capacitors, a signal INPUT terminal INPUT (not shown), a first clock signal terminal CK (not shown), a second clock signal terminal CKB (not shown), a signal OUTPUT terminal OUTPUT (not shown), a first reference voltage terminal VGL (not shown), and a second reference voltage terminal VGH (not shown), each transistor including an active layer, a gate electrode, a first electrode, and a second electrode, each capacitor including an upper plate and a lower plate, in a plane perpendicular to the first substrate, the first substrate comprises a first substrate base plate, a semiconductor layer, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer and a flat layer which are stacked on the first substrate base plate, wherein the semiconductor layer comprises an active layer of each transistor, the first metal layer comprises a grid electrode of each transistor, a first polar plate C1-2 of a first capacitor C1 and a third polar plate C2-2 of a second capacitor C2, the second metal layer comprises a first polar plate and a second polar plate of each transistor, a second polar plate C1-1 of the first capacitor C1, a fourth polar plate C2-1 of the second capacitor C2, a signal INPUT end INPUT, a first clock signal end CK, a second clock signal end CKB, a signal OUTPUT end OUTPUT, a first reference voltage end VGL and a second reference voltage end H; the first pole and the second pole of each transistor are respectively connected with two ends of the active layer of each transistor through a via hole on the second insulating layer.

In an exemplary embodiment, as shown in fig. 5, the plurality of transistors includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7, the plurality of capacitors includes a first capacitor C1 and a second capacitor C2, a gate 11 of the first transistor M1 is connected to the first clock signal terminal CK, a first pole 12 of the first transistor M1 is connected to the signal INPUT terminal INPUT, a second pole 13 of the first transistor M1 is connected to a third plate C2-2 of the second capacitor C2, a gate 51 of the fifth transistor M5, a gate 21 of the second transistor, and a second pole 73 of the seventh transistor M2 is connected to the second clock signal terminal b, a second pole 23 of the second transistor M2 is connected to a second pole 33 of the third transistor, and a signal OUTPUT terminal OUTPUT; the gate of the third transistor M3 is connected to the first plate C1-2 of the first capacitor C1, the gate 61 of the sixth transistor M6, the second pole 53 of the fifth transistor and the second pole 43 of the fourth transistor M4, and the first pole of the third transistor M3 is connected to the second reference voltage terminal VGH; the second polar plate C1-1 of the first capacitor C1 is connected with the second reference voltage end VGH, the second polar plate C2-1 of the second capacitor C2 is connected with the signal OUTPUT end OUTPUT, and the first polar plate C2-2 of the second capacitor C2 is connected with the first node N1; the gate 41 of the fourth transistor M4 is connected to the first clock signal terminal CK, the first pole 42 of the fourth transistor M4 is connected to the first reference voltage terminal VGL, the first pole 52 of the fifth transistor M5 is connected to the first clock signal terminal CK, the first pole 62 of the sixth transistor M6 is connected to the second reference voltage terminal VGH, and the second pole 63 of the sixth transistor M6 is connected to the first pole 72 of the seventh transistor M7; the gate 71 of the seventh transistor M7 is connected to the second clock signal terminal CKB.

The following is an exemplary description of a preparation process of a microfluidic chip. The "patterning process" referred to in this disclosure includes, for metallic materials, inorganic materials, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, photoresist stripping, and the like, and for organic materials, processes such as organic material coating, mask exposure, and development, and the like. The deposition may be any one or more of sputtering, evaporation, chemical vapor deposition, coating may be any one or more of spraying, spin coating, and ink jet printing, and etching may be any one or more of dry etching and wet etching, without limitation of the disclosure. "film" refers to a layer of film formed by depositing, coating, or other process a material on a substrate. The "film" may also be referred to as a "layer" if the "film" does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" prior to the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The phrase "a and B are arranged in the same layer" in the present disclosure means that a and B are formed simultaneously by the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the microfluidic chip. In the exemplary embodiments of the present disclosure, "the front projection of B is within the range of the front projection of a" means that the boundary of the front projection of B falls within the boundary range of the front projection of a, or the boundary of the front projection of a overlaps with the boundary of the front projection of B. "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

In an exemplary embodiment, the preparation process of the microfluidic chip mainly includes: first, preparing a first substrate and a second substrate respectively, and second, packaging the first substrate and the second substrate together.

Wherein, the preparing of the first substrate in the step (one) includes:

(1) A semiconductor layer pattern is formed. In an exemplary embodiment, forming the semiconductor layer pattern may include: a semiconductor thin film is deposited on the first substrate, and patterned by a patterning process to form a semiconductor layer covering the first substrate, as shown in fig. 6.

The shift register unit in the embodiments of the present disclosure may be any existing shift register unit circuit model, and illustratively, the shift register unit in the embodiments of the present disclosure is described taking the shift register unit circuit model of 7T2C as an example. The shift register cells provide voltages ranging from-2 volts to-50 volts or +2 volts to +50 volts.

In an exemplary embodiment, the semiconductor layer may include the active layer 10 of the first transistor M1, the active layer 20 of the second transistor M2, the active layer 30 of the third transistor M3, the active layer 40 of the fourth transistor M4, the active layer 50 of the fifth transistor M5, the active layer 60 of the sixth transistor M6, and the active layer 70 of the seventh transistor M7.

In an exemplary embodiment, the active layer 10 of the first transistor M1, the active layer 40 of the fourth transistor M4, the active layer 50 of the fifth transistor M5, the active layer 60 of the sixth transistor M6, and the active layer 70 of the seventh transistor M7 are disposed at a side of the active layer 30 remote from the active layer 20 of the second transistor M2 and the active layer 30 of the third transistor M3, the active layer 20 of the second transistor M2 and the active layer 30 of the third transistor M3 are in a unitary structure, and the active layer 60 of the sixth transistor M6 and the active layer 70 of the seventh transistor M7 are in a unitary structure, and the active layer 40 of the fourth transistor M4 and the active layer 50 of the fifth transistor M5 are in a unitary structure.

(2) A first metal layer pattern is formed. In an exemplary embodiment, forming the first metal layer pattern may include: sequentially depositing a first insulating film and a first metal film on a substrate on which the foregoing patterns are formed, patterning the first metal film by a patterning process to form a first insulating layer covering the semiconductor layer pattern, and a first metal layer pattern disposed on the first insulating layer, the first metal layer pattern including: the gate layers of the first transistor M1 to the seventh transistor M7, the first connection line L1, the second connection line L2, the third connection line L3, the fourth connection line L4, the fifth connection line L5, the sixth connection line L6, the seventh connection line L7, the eighth connection line L8, the first plate C1-2 of the first capacitor C1, and the third plate C2-2 of the second capacitor C2 are shown in fig. 7.

In the exemplary embodiment, the first connection line L1 is used for connecting the first electrode 12 of the subsequently formed first transistor M1 and the signal INPUT terminal INPUT, the second connection line L2 is used for connecting the gate 11 of the first transistor M1 and the gate 41 of the fourth transistor M4, the third connection line L3 is used for connecting the first electrode 52 of the subsequently formed fifth transistor M5 and the first clock signal terminal CK, the fourth connection line L4 is used for connecting the first electrode 22 of the subsequently formed second transistor M2 and the second clock signal terminal CKB, and the fourth connection line L4 and the gate 71 of the seventh transistor M7 are connected to each other in an integral structure, the fifth connection line L5 is used for connecting the second electrode plate C1-1 formed subsequently and the first electrode 32 of the third transistor M3, the sixth connection line L6 is used for connecting the gate 51 of the fifth transistor M5 and the second electrode 13 of the first transistor M1 formed subsequently, the seventh connection line L7 is connected with the first gate 211 of the second transistor M2 and the gate 51 of the fifth transistor M5, the gate 61 of the sixth transistor M6 is connected with the first electrode plate C1-2 into an integral structure, the eighth connection line L8 is connected with the first electrode plate C1-2 and the gate 31 of the third transistor M3, and the third electrode plate C2-2 and the gate (double gate, the first gate 211 and the second gate 212) of the second transistor M2 are connected into an integral structure.

In an exemplary embodiment, after the first metal layer pattern is formed, the semiconductor layer may be subjected to a conductive process using the first metal layer as a mask, the semiconductor layer of the region masked by the first metal layer forms channel regions of the active layers of the first to seventh transistors M1 to M7, and the semiconductor layer of the region not masked by the first metal layer is conductive.

(3) A second insulating layer pattern is formed. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate with the patterns, and patterning the second insulating film by a patterning process to form a second insulating layer covering the first metal layer, wherein a plurality of through holes are formed on the second insulating layer, and the plurality of through holes comprise: the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, and eleventh vias V1, V2, V3, V4, V5, V6, V7, V8, V9, V10, and V11 are shown in fig. 8.

In an exemplary embodiment, the first via V1 is configured to connect the first pole 12 to 72 of each of the subsequently formed transistors T1 to T7 with the second pole 13 to 73 through the via, respectively, to both ends of the active layers 10 to 70 of each of the transistors T1 to T7, the second via V2 is configured to connect the first pole 12 of the first transistor M1 with the subsequently formed signal INPUT terminal INPUT, the third via V3 is configured to connect the sixth connection line L6 with the second pole 13 of the subsequently formed first transistor M1, the fourth via V4 is configured to connect the ninth connection line L9 of the subsequently formed via the via with the second connection line L2, the first pole 52 of the fifth transistor, and the third connection line L3, the fifth via V5 is configured to connect the subsequently formed first clock signal terminal CK with the third connection line L3, the sixth via V6 is configured to connect the fourth connection line L4 with the second connection line b through the via, the seventh via is configured to connect the fifth connection line L2 with the fifth connection line C1 through the fifth connection line C2, the fifth via V2 is configured to connect the fifth connection line C1 through the fifth connection line C2 with the fifth connection line C2, the fifth via V2 is configured to connect the fifth connection line C2 with the fifth connection line C2 through the fifth connection line C2 and the fifth connection line C2 through the fifth connection line C2.

(3) And forming a second metal layer pattern. In an exemplary embodiment, forming the second metal layer pattern may include: depositing a second metal film on the substrate with the patterns, and patterning the second metal film by a patterning process to form a second metal layer pattern covering the second insulating layer, wherein the second metal layer pattern comprises: the first pole 12 of the first transistor M1 to the first pole 72 of the seventh transistor M7, the second pole 13 of the first transistor M1 to the second pole 73 of the seventh transistor M7, the ninth connection line L9, the tenth connection line L10, the eleventh connection line L11, the twelfth connection line L12, the thirteenth connection line L13, the second plate C1-1 of the first capacitor, the fourth plate C2-1 of the second capacitor, the signal INPUT terminal INPUT (not OUTPUT in the drawing), the first clock signal terminal CK (not OUTPUT in the drawing), the second clock signal terminal CKB (not OUTPUT in the drawing), the first reference voltage terminal VGL (not OUTPUT in the drawing), the second reference voltage terminal VGH (not OUTPUT in the drawing), the signal OUTPUT terminal OUTPUT (not OUTPUT in the drawing), the start signal INPUT line stv, the first clock signal line CK, the second clock signal line CKB, the second reference voltage line VGH, the first reference voltage line VGL, the connection line (not OUTPUT in the drawing), and the electrode pair (not OUTPUT in the drawing), as shown in fig. 6.

In the exemplary embodiment, in each stage of the shift register unit, the first pole 12 and the second pole 13 of the first transistor M1 are respectively connected to both ends of the active layer 10 of the first transistor M1 through the first via V1, the first pole 22 and the second pole 23 of the second transistor M2 are respectively connected to both ends of the active layer 20 of the second transistor M2 through the first via V1, the first pole 32 and the second pole 33 of the third transistor M3 are respectively connected to both ends of the active layer 30 of the third transistor M3 through the first via V1, the first pole 42 and the second pole 43 of the fourth transistor M4 are respectively connected to both ends of the active layer 40 of the fourth transistor M4 through the first via V1, the first pole 52 and the second pole 53 of the fifth transistor M5 are respectively connected to both ends of the active layer 50 of the fifth transistor M5 through the first via V1, the first pole 62 and the second pole 63 of the sixth transistor M6 are respectively connected to both ends of the active layer 60 of the sixth transistor M6 through the first via V1, the first and second poles 72 and 73 of the seventh transistor M7 are respectively connected to both ends of the active layer 70 of the seventh transistor M7 through the first via hole V1, the first pole 12 of the first transistor M1 is connected to the signal INPUT terminal INPUT through the second via hole V2, the second pole 13 of the first transistor M1 is connected to the sixth connection line L6 through the third via hole V3, the ninth connection line L9 is connected to the second connection line L2, the third connection line L3 and the first pole 52 of the fifth transistor M5 through the fourth via hole V4, the first clock signal terminal CK is connected to the third connection line L3 through the fifth via hole V5, the second clock signal terminal CKB is connected to the fourth connection line L4 through the sixth via hole V6, the first pole 22 of the second transistor is connected to the fourth connection line L4 through the seventh via hole V7, the tenth connection line L10 is connected to the first pole 62 of the sixth transistor and the second reference voltage terminal VGH, the eleventh connection line L11 connects the first pole 42 of the fourth transistor with the first reference voltage terminal VGL, the twelfth connection line L12 connects the seventh connection line L7 with the second gate 212 of the second transistor through the eighth via hole V8, the thirteenth connection line L13 connects the first pole plate C1-2 of the first capacitor C1 through the ninth via hole V9, the first pole 32 of the third transistor M3 connects the fifth connection line L5 through the tenth via hole V10, the second pole plate C1-1 of the first capacitor C1 connects the fifth connection line L5 through the eleventh via hole V11, the second pole plate C2-1 of the second capacitor C2, the second pole 33 of the third transistor, the second pole 23 of the second transistor and the signal OUTPUT terminal OUTPUT are connected to each other as an integral structure.

The signal INPUT end INPUT of the shift register unit positioned at the first stage is connected with the initial signal INPUT line stv, the signal INPUT end INPUT of the shift register unit positioned at the i-1 stage is connected with the signal OUTPUT end OUTPUT of the shift register unit positioned at the i-1 stage, 2 is equal to or more than i is equal to or less than N, N is the total number of stages of the shift register unit, the signal OUTPUT end OUTPUT of the shift register unit of each stage is connected with at least one electrode pair through a connecting line, the first clock signal end CK of the shift register unit of each stage is connected with the first clock signal line CK, the second clock signal end CKB of the shift register unit of each stage is connected with the second clock signal line CKB, the first reference voltage end VGL of the shift register unit of each stage is connected with the first reference voltage line VGL, and the second reference voltage end VGH of the shift register unit of each stage is connected with the second reference voltage line VGH.

(4) And forming a third insulating layer pattern. In an exemplary embodiment, forming the third insulating layer pattern may include: and depositing a third insulating film on the substrate with the patterns to form a third insulating layer covering the second metal layer.

(5) Forming a flat layer pattern. In an exemplary embodiment, forming the planarization layer pattern may include: on the substrate on which the foregoing pattern was formed, a first flat film was coated to form a flat (PLN) layer covering the entire substrate.

In an exemplary embodiment, the material of the semiconductor layer is not limited, and exemplary materials of the semiconductor layer may be polysilicon, indium gallium zinc oxide IGZO, etc., and materials of the first metal layer or the second metal layer may be a metal material or a metal composite material having good conductivity such as titanium Ti, platinum Pt, aluminum Al, molybdenum Mo, indium tin oxide ITO, neodymium Nd, etc., the thickness of the first metal layer is 500 to 10000 a/m, and the thickness of the second metal layer is 500 to 10000 a/m.

In an exemplary embodiment, in each electrode pair, the width of each electrode is greater than 0 and less than or equal to 1000 micrometers, the distance d between adjacent electrodes should follow d.ltoreq.v.t/2 and d.ltoreq.v/E, where V is the migration rate of the substance to be separated, t is the clock signal period of the shift register unit, V is the output voltage of the shift register unit, E is the electric field strength required for separation, V and E are obtained by looking up a table according to the properties of the substance to be separated, and t and V are obtained according to the design value of the shift register unit.

In an exemplary embodiment, the material of the third insulating layer may be an insulating material of silicon nitride SiNx, silicon oxide SiO, or the like, the thickness of the third insulating layer is greater than 0 and less than or equal to 10000 a, and the size of the third insulating layer is greater than or equal to the electrode size of the second metal layer.

In an exemplary embodiment, the first substrate further includes a low voltage pulse generator 3, and the low voltage pulse generator 3 is configured to generate a start signal, a first clock signal, a second reference voltage, and a first reference voltage, and input to the start signal input line, the first clock signal line, the second reference voltage line, and the first reference voltage line, respectively.

The preparation of the first substrate of this embodiment is completed through the above-described process.

Wherein the preparing of the second substrate in the step (one) includes:

a second substrate having micro-channels on the surface for receiving droplets is fabricated by a photolithography or thermal embossing process, as shown in fig. 9.

In an exemplary embodiment, the width of the micro-channel is greater than 0 and less than or equal to 5000um, the depth of the micro-channel is 10 to 1000um, the length of the micro-channel is 1 to 500mm, and the shape of the micro-channel is not limited, and may be rectangular, serpentine, spiral, etc., for example.

In an exemplary embodiment, as shown in fig. 9, the micro channel includes a sample introduction channel 80 and a separation channel 81 intersecting each other, a sample liquid reservoir 801 and a sample waste liquid reservoir 802 are provided at both ends of the sample introduction channel 80, and a buffer liquid reservoir 811 and a buffer waste liquid reservoir 812 are provided at both ends of the separation channel 81.

Wherein, the step (II) comprises the following steps: the method comprises the steps of turning over a second substrate (or a first substrate), enabling the surface of the first substrate on which the structural layer is formed to face the surface of the second substrate on which the structural layer is formed, aligning the first substrate with the second substrate, and then carrying out hot-pressing packaging on the first substrate and the second substrate.

In one exemplary embodiment, the first substrate and the second substrate are cleaned and then placed in a thermo-compression mold for thermo-compression packaging using a bonder (600 ℃).

The structure of the microfluidic chip of the present disclosure and the process of preparing the same are merely one exemplary illustration. In an exemplary embodiment, the corresponding structure may be changed and the patterning process may be increased or decreased according to actual needs, for example, the structure of the channels on the second substrate may be changed and/or the number of the channels on the second substrate may be increased according to actual needs, and accordingly, the number and arrangement manner of the shift register units and the connection lines on the first substrate may be designed according to the structure and the number of the channels on the second substrate, which is not limited herein.

According to the preparation process of the embodiment of the disclosure, the microfluidic chip integrates a plurality of cascaded shift register units and connecting lines on the first substrate, so that the integration and miniaturization of the microfluidic chip are realized, the constraints of a high-voltage power supply and redundant circuits are reduced, and the high integration of the microfluidic chip circuit is effectively realized, so that components of a sample to be detected are separated and analyzed more simply, conveniently and rapidly, and a new choice is provided for the hot medical fields such as disease diagnosis, chemical and biological molecular separation analysis, gene sequencing and the like. The preparation process of the microfluidic chip of the exemplary embodiment of the disclosure has good process compatibility, simple process implementation, easy implementation, high production efficiency, low production cost and high yield.

In an exemplary embodiment, the shift register cell of embodiments of the present disclosure employs a 7T2C circuit design. In each shift register unit, the length of each thin film transistor is 20 micrometers, the width is 10 micrometers, the signal falling Time (TF) of the start signal input line stv is 0.5 microsecond, the signal Pulse Width (PW) is 51 microseconds, the signal Period (PER) is 1 millisecond, the signal falling Time (TF) of the first clock signal line ck is 0.5 microsecond, the signal Pulse Width (PW) is 47 microseconds, the signal Period (PER) is 100 microseconds, the signal falling time (fall time, TF) of the second clock signal line ckb is 0.5 microsecond, the signal Pulse Width (PW) is 47 microseconds, the signal Period (PER) is 100 microseconds, the first reference voltage input by the first reference voltage line vgl is-7V, and the second reference voltage input by the second reference voltage line vgh is +7v. Simulation results show that the low-voltage signal pulse output by the shift register unit shifts, and the function of pressurizing line by line can be realized.

As shown in fig. 10, the present disclosure further provides a method for preparing a microfluidic chip, the method comprising:

S1, respectively preparing a first substrate and a second substrate, wherein the first substrate comprises a plurality of mutually cascaded shift register units, a connecting circuit and a plurality of electrode pairs which are mutually arranged at intervals, and the output end of at least one shift register unit is connected with at least one electrode pair through the connecting circuit; the second substrate includes a microchannel for accommodating the droplet;

s2, aligning the first substrate with the second substrate, carrying out hot-pressing packaging on the first substrate and the second substrate, carrying out orthographic projection of the electrode pair on the first substrate, and symmetrically distributing the electrode pair on two sides of orthographic projection of the micro-channel on the first substrate.

In an exemplary embodiment, step S1 includes:

forming a semiconductor layer on a first substrate base plate;

forming a first insulating layer covering the semiconductor layer on the semiconductor layer;

forming a first metal layer on the first insulating layer;

forming a second insulating layer on the first metal layer;

forming a second metal layer on the second insulating layer;

a third insulating layer and a planarization layer disposed on the third insulating layer are sequentially formed on the second metal layer.

In an exemplary embodiment, the semiconductor layer includes active layers of the first transistor to the seventh transistor, wherein: the active layer of the first transistor, the active layer of the fourth transistor, the active layer of the fifth transistor, the active layer of the sixth transistor and the active layer of the seventh transistor are disposed on a side away from the active layer of the second transistor and the active layer of the third transistor, the active layer of the second transistor and the active layer of the third transistor are connected to each other to form an integrated structure, the active layer of the sixth transistor and the active layer of the seventh transistor are connected to each other to form an integrated structure, and the active layer of the fourth transistor and the active layer of the fifth transistor are connected to each other to form an integrated structure.

In an exemplary embodiment, the first metal layer includes: the gate layers of the first transistor to the seventh transistor, the first connection line to the eighth connection line, the first plate of the first capacitor and the third plate of the second capacitor, and the second metal layer includes: the first electrode of the first transistor to the first electrode of the seventh transistor, the second electrode of the first transistor to the second electrode of the seventh transistor, the second polar plate of the first capacitor, the signal input end, the first clock signal end, the second clock signal end, the first reference voltage end, the second reference voltage end and the signal output end, the grid electrode of the second transistor comprises a first grid electrode and a second grid electrode, wherein:

the first connecting wire is connected with the first pole of the first transistor and the signal input end, the second connecting wire is connected with the grid of the first transistor and the grid of the fourth transistor, the third connecting wire is connected with the first pole of the fifth transistor and the first clock signal end, the fourth connecting wire is connected with the first pole of the second transistor and the second clock signal end, the fourth connecting wire is connected with the grid of the seventh transistor into an integrated structure, the fifth connecting wire is connected with the second pole plate of the first capacitor and the first pole of the third transistor, the sixth connecting wire is connected with the grid of the fifth transistor and the second pole plate of the first transistor, the seventh connecting wire is connected with the first grid of the second transistor and the grid of the fifth transistor, the grid of the sixth transistor and the first pole plate of the first capacitor are connected into an integrated structure, and the eighth connecting wire is connected with the first pole plate of the first capacitor and the grid of the third transistor into an integrated structure.

In an exemplary embodiment, the second insulating layer includes first through eleventh vias, the second metal layer further includes ninth through thirteenth connection lines, and a fourth plate of the second capacitor, wherein:

the first electrode and the second electrode of each transistor are respectively connected with two ends of an active layer of each transistor through a first through hole, the first electrode of the first transistor is connected with a signal input end through a second through hole, the sixth connecting wire is connected with the second electrode of the first transistor through a third through hole, the ninth connecting wire is connected with the second connecting wire, the first electrode of the fifth transistor and the third connecting wire through a fourth through hole, the first clock signal end is connected with the third connecting wire through a fifth through hole, the fourth connecting wire is connected with the second clock signal end through a sixth through hole, the fourth connecting wire is connected with the first electrode of the second transistor through a seventh through hole, the tenth connecting wire is connected with the first electrode of the sixth transistor and a second reference voltage end, the eleventh connecting wire is connected with the first electrode of the fourth transistor and a first reference voltage end, the seventh connecting wire and the second grid of the second transistor are connected with the twelfth connecting wire through an eighth through holes, the thirteenth connecting wire is connected with the first electrode plate of the first capacitor through the ninth through hole, the fifth connecting wire is connected with the fifth electrode of the third capacitor through the fifth through hole, and the third electrode of the third transistor is connected with the third electrode of the third capacitor.

In an exemplary embodiment, the second metal layer further includes: a start signal input line, a first clock signal line, a second reference voltage line, a first reference voltage line, a connection line, and an electrode pair, wherein:

the signal input end of the shift register unit positioned at the first stage is connected with the initial signal input line, the signal input end of the shift register unit positioned at the i-1 th stage is connected with the signal output end of the shift register unit positioned at the i-1 th stage, i is more than or equal to 2 and less than or equal to N, and N is the total number of stages of the shift register unit;

the signal output end of the shift register unit of each stage is connected with at least one electrode pair through a connecting line;

the first clock signal end of the shift register unit of each stage is connected with a first clock signal line;

the second clock signal end of the shift register unit of each stage is connected with a second clock signal line;

the first reference voltage end of the shift register unit of each stage is connected with a first reference voltage line;

the second reference voltage terminal of the shift register unit of each stage is connected to a second reference voltage line.

According to the preparation method of the microfluidic chip, the plurality of cascaded shift register units and the connecting lines are integrated on the first substrate, so that the integration and miniaturization of the microfluidic chip are realized, the constraints of a high-voltage power supply and redundant circuits are reduced, the high integration of the microfluidic chip circuit is effectively realized, and therefore components of a sample to be detected are separated and analyzed more simply and rapidly, and a new choice is provided for the hot medical fields such as disease diagnosis, chemical and biological molecular separation analysis and gene sequencing.

While the embodiments disclosed in the present disclosure are described above, the embodiments are only employed for facilitating understanding of the present disclosure, and are not intended to limit the present disclosure. Any person skilled in the art to which this disclosure pertains will appreciate that numerous modifications and changes in form and details can be made without departing from the spirit and scope of the disclosure, but the scope of the disclosure is to be determined by the appended claims.

Claims

1. A microfluidic chip comprising a first substrate and a second substrate disposed opposite one another, wherein:

the side of the first substrate facing the second substrate comprises a plurality of mutually cascaded shift register units, a connecting circuit and a plurality of electrode pairs which are arranged at intervals, and the output end of at least one shift register unit is connected with at least one electrode pair through the connecting circuit;

the side of the second substrate facing the first substrate comprises micro-channels for containing liquid drops, and the front projections of the electrode pairs on the first substrate are symmetrically distributed on two sides of the front projections of the micro-channels on the first substrate;

the shift register unit includes: an input sub-circuit, an output sub-circuit, a first control sub-circuit, a second control sub-circuit, and a pull-up control sub-circuit, wherein:

The input sub-circuit is respectively connected with a first clock signal end, a signal input end and a first node and is used for providing signals of the signal input end for the first node under the control of the first clock signal end;

the output sub-circuit is respectively connected with the first node, the second reference voltage end, the second clock signal end and the signal output end and is used for providing signals of the second reference voltage end or the second clock signal end for the signal output end under the control of the first node and the second node;

the first control sub-circuit is respectively connected with the first clock signal end, the first reference voltage end and the second node and is used for providing signals of the first reference voltage end for the second node under the control of the first clock signal end;

the second control sub-circuit is respectively connected with the first clock signal end, the first node and the second node and is used for providing signals of the first clock signal end for the second node under the control of the first node;

the pull-up control sub-circuit is respectively connected with the second reference voltage end, the second clock signal end, the first node and the second node, and is used for providing signals of the second reference voltage end for the first node under the control of the second node and the second clock signal end.

2. The microfluidic chip according to claim 1, wherein the micro-channel comprises a sample introduction channel and a separation channel which are intersected with each other, a sample liquid storage tank and a sample waste liquid storage tank are arranged at two ends of the sample introduction channel, and a buffer liquid storage tank and a buffer waste liquid storage tank are arranged at two ends of the separation channel;

the electrode pairs comprise at least two groups, wherein the orthographic projections of one group of electrode pairs on the first substrate are symmetrically distributed on two sides of the orthographic projections of the sample injection channel on the first substrate; the other group of the electrode pairs are in orthographic projection on the first substrate and are symmetrically distributed on two sides of orthographic projection of the separation channel on the first substrate;

the shift register unit comprises at least two groups, wherein the signal output end of one group of shift register unit is connected with one group of electrode pairs, and the signal output end of the other group of shift register unit is connected with the other group of electrode pairs.

3. The microfluidic chip of claim 1, wherein the input sub-circuit comprises a first transistor, the output sub-circuit comprises a second transistor, a third transistor, a first capacitance, and a second capacitance, the first control sub-circuit comprises a fourth transistor, the second control sub-circuit comprises a fifth transistor, and the pull-up control sub-circuit comprises a sixth transistor and a seventh transistor;

The grid electrode of the first transistor is connected with the first clock signal end, the first electrode of the first transistor is connected with the signal input end, and the second electrode of the first transistor is connected with the first node;

the grid electrode of the second transistor is connected with the first node, the first electrode of the second transistor is connected with the second clock signal end, and the second electrode of the second transistor is connected with the signal output end;

a gate of the third transistor is connected to the second node, a first pole of the third transistor is connected to the second reference voltage terminal, and a second pole of the third transistor is connected to the signal output terminal;

one end of the first capacitor is connected with the second reference voltage end, and the other end of the first capacitor is connected with the second node;

one end of the second capacitor is connected with the signal output end, and the other end of the second capacitor is connected with the first node;

the grid electrode of the fourth transistor is connected with the first clock signal end, the first electrode of the fourth transistor is connected with the first reference voltage end, and the second electrode of the fourth transistor is connected with the second node;

The grid electrode of the fifth transistor is connected with the first node, the first electrode of the fifth transistor is connected with the first clock signal end, and the second electrode of the fifth transistor is connected with the second node;

the grid electrode of the sixth transistor is connected with the second node, the first electrode of the sixth transistor is connected with the second reference voltage end, and the second electrode of the sixth transistor is connected with the first electrode of the seventh transistor;

and the grid electrode of the seventh transistor is connected with the second clock signal end, and the second electrode of the seventh transistor is connected with the first node.

4. A microfluidic chip according to claim 3, wherein on a plane perpendicular to the first substrate, the first substrate comprises a first substrate, a semiconductor layer disposed on the first substrate, a first insulating layer disposed on the semiconductor layer, a first metal layer disposed on the first insulating layer, a second insulating layer disposed on the first metal layer and a second metal layer disposed on the second insulating layer, a third insulating layer disposed on the second metal layer, and a planar layer disposed on the third insulating layer.

5. The microfluidic chip according to claim 4, wherein the semiconductor layer comprises an active layer of the first transistor to an active layer of the seventh transistor, wherein:

the active layers of the first transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are arranged on one side far away from the active layers of the second transistor and the third transistor, the active layers of the second transistor and the third transistor are connected with each other to form an integral structure, the active layers of the sixth transistor and the seventh transistor are connected with each other to form an integral structure, and the active layers of the fourth transistor and the fifth transistor are connected with each other to form an integral structure.

6. The microfluidic chip according to claim 4, wherein the first metal layer comprises: the gate layer of the first transistor to the gate layer of the seventh transistor, the first connection line to the eighth connection line, the first plate of the first capacitor and the third plate of the second capacitor, and the second metal layer includes: the first electrode of the first transistor to the first electrode of the seventh transistor, the second electrode of the first transistor to the second electrode of the seventh transistor, the second electrode plate of the first capacitor, the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first reference voltage terminal, the second reference voltage terminal and the signal output terminal, and the gate of the second transistor includes a first gate and a second gate, wherein:

The first connecting line is connected with the first pole of the first transistor and the signal input end, the second connecting line is connected with the grid of the first transistor and the grid of the fourth transistor, the third connecting line is connected with the first pole of the fifth transistor and the first clock signal end, the fourth connecting line is connected with the first pole of the second transistor and the second clock signal end, the fourth connecting line is connected with the grid of the seventh transistor into an integrated structure, the fifth connecting line is connected with the second pole plate of the first capacitor and the first pole of the third transistor, the sixth connecting line is connected with the grid of the fifth transistor and the second pole of the first transistor, the seventh connecting line is connected with the first grid of the second transistor and the grid of the fifth transistor, the grid of the sixth transistor and the first pole plate of the first capacitor are connected into an integrated structure, and the eighth connecting line is connected with the second pole plate of the first capacitor and the third pole plate of the third transistor into an integrated structure.

7. The microfluidic chip according to claim 6, wherein the second insulating layer comprises first through eleventh vias, the second metal layer further comprises ninth through thirteenth connection lines, and a fourth plate of the second capacitor, wherein:

the first pole and the second pole of each transistor are respectively connected with two ends of an active layer of each transistor through a first via hole, the first pole of the first transistor is connected with the signal input end through a second via hole, the sixth connecting wire is connected with the second pole of the first transistor through a third via hole, the ninth connecting wire is connected with the second connecting wire, the first pole of the fifth transistor and the third connecting wire through a fourth via hole, the first clock signal end is connected with the third connecting wire through a fifth via hole, the fourth connecting wire is connected with the second clock signal end through a sixth via hole, the fourth connecting wire is connected with the first pole of the second transistor through a seventh via hole, the tenth connecting wire is connected with the first pole of the sixth transistor and the second reference voltage end through a third via hole, the eleventh connecting wire is connected with the first pole of the fourth transistor and the first reference voltage end through a fourth via hole, the seventh connecting wire and the second pole of the fifth connecting wire are connected with the fifth pole of the third transistor through a fifth via hole, the eighth connecting wire is connected with the fourth pole of the fourth connecting wire and the third connecting wire is connected with the third pole of the fourth connecting wire and the fourth connecting wire is connected with the third pole of the fourth connecting wire.

8. The microfluidic chip according to claim 6, wherein the second metal layer further comprises: a start signal input line, a first clock signal line, a second reference voltage line, a first reference voltage line, a connection line, and an electrode pair, wherein:

the signal input end of the shift register unit positioned at the first stage is connected with the initial signal input line, the signal input end of the shift register unit positioned at the i-th stage is connected with the signal output end of the shift register unit positioned at the i-1 th stage, i is more than or equal to 2 and less than or equal to N, and N is the total number of stages of the shift register unit;

9. The microfluidic chip according to claim 1, wherein the width of the micro-channels is less than 5000 microns, the depth of the micro-channels is 10 to 1000 microns, and the length of the micro-channels is 1 to 500 millimeters.

10. The microfluidic chip according to claim 1, wherein each electrode in the pair of electrodes has a width of less than 1000 microns, and the spacing d between adjacent electrodes satisfies: d is less than or equal to V t/2 and d is less than or equal to V/E, wherein V is the migration rate of substances to be separated, t is the clock signal period of the shift register unit, V is the output voltage of the shift register unit, and E is the electric field strength required by separation.

11. A method of preparing a microfluidic chip comprising:

preparing a first substrate and a second substrate respectively, wherein the first substrate comprises a plurality of mutually cascaded shift register units, a connecting circuit and a plurality of electrode pairs which are arranged at intervals, and the output end of at least one shift register unit is connected with at least one electrode pair through the connecting circuit; the second substrate includes a microchannel for receiving a droplet; the shift register unit includes: an input sub-circuit, an output sub-circuit, a first control sub-circuit, a second control sub-circuit, and a pull-up control sub-circuit, wherein: the input sub-circuit is respectively connected with a first clock signal end, a signal input end and a first node and is used for providing signals of the signal input end for the first node under the control of the first clock signal end; the output sub-circuit is respectively connected with the first node, the second reference voltage end, the second clock signal end and the signal output end and is used for providing signals of the second reference voltage end or the second clock signal end for the signal output end under the control of the first node and the second node; the first control sub-circuit is respectively connected with the first clock signal end, the first reference voltage end and the second node and is used for providing signals of the first reference voltage end for the second node under the control of the first clock signal end; the second control sub-circuit is respectively connected with the first clock signal end, the first node and the second node and is used for providing signals of the first clock signal end for the second node under the control of the first node; the pull-up control sub-circuit is respectively connected with the second reference voltage end, the second clock signal end, the first node and the second node and is used for providing signals of the second reference voltage end for the first node under the control of the second node and the second clock signal end;