CN108889350B

CN108889350B - Microfluid array controller

Info

Publication number: CN108889350B
Application number: CN201810818393.5A
Authority: CN
Inventors: 刘立滨; 许诺; 臧金良; 李平; 刘宇航
Original assignee: Beijing Machinery Equipment Research Institute
Current assignee: Beijing Machinery Equipment Research Institute
Priority date: 2018-07-24
Filing date: 2018-07-24
Publication date: 2021-04-02
Anticipated expiration: 2038-07-24
Also published as: CN108889350A

Abstract

The invention relates to a microfluid array controller, belongs to the technical field of microfluid control, and solves the problem that large-scale fluid array control is difficult to realize in the prior art. The invention discloses a microfluid array controller, which comprises an M × N array formed by arranging and combining M × N control units, a power supply 1 and a power supply 2, wherein each control unit comprises a microfluid channel device, a thin film transistor device and a capacitor. Liquid is arranged in each micro-fluid channel device, under the combined action of the corresponding row control signal and the corresponding column control signal, the thin film transistor device gates the micro-fluid channel devices in the corresponding units, and the liquid moves, is divided and is fused in the micro-channels of the micro-fluid channel devices. The invention can realize large-scale fluid array control, greatly reduce the control difficulty of the large-scale microfluid array, reduce the number of leads and provide a new technical approach for the practicability of the microfluid control chip.

Description

Microfluid array controller

Technical Field

The invention relates to the technical field of microfluid control, in particular to a microfluid array controller.

Background

Microfluid control is a control technology for controlling operations such as movement, segmentation, fusion and the like of liquid droplets by using voltage signals, and is one of core technologies for realizing micro electrochemistry, chemistry, medical treatment and biochips.

Microfluidic controllers typically use arrayed control electrodes to effect control of the microfluidics. However, the existing microfluidic controller is limited by the number of interconnection leads, the scale of the electrode array of the existing microfluidic controller is far from the use requirement, and the popularization and application of the microfluidic control chip are seriously hindered.

The structure of the existing microfluidic array controller is shown in fig. 1, and if the array size is M × N, M × N +1 lead-out lines need to be led out in order to apply voltage to each microfluidic channel device. With the adoption of the structure, along with the increase of the array scale, the number of the leads is increased by geometric multiples, so that the difficulty of manufacturing the array is increased, and a peripheral control circuit is complex and large in size. Moreover, the microfluid control needs higher voltage, generally more than 50V, and the existing microfluid array control technology can not meet the requirements.

Disclosure of Invention

In view of the foregoing analysis, embodiments of the present invention are directed to a microfluidic array controller, so as to solve the problem that it is not easy to implement a large-scale microfluidic array controller in the prior art.

In one aspect, embodiments of the present invention provide a microfluidic array controller, including an mxn array formed by arranging mxn control units, a power supply 1, and a power supply 2;

each control unit comprises a microfluidic channel device, a thin film transistor device and a capacitor;

in each row of the array, the gate electrodes of all the thin film transistor devices are connected and connected with corresponding row control signals; in each column, the source electrodes of all the thin film transistor devices are connected and connected with corresponding column control signals; the drain electrodes of all thin film transistor devices are connected to a power supply 1 via the corresponding microfluidic channel device and to a power supply 2 via the corresponding capacitor.

The beneficial effects of the above technical scheme are as follows: the working state of the microfluidic channel device in each control unit can be accurately controlled through the row control signal and the column control signal, specifically, one row is gated through the gate electrode lead in the row direction, and then a voltage value is written into the target microfluidic channel device through the source electrode lead in the column direction. The voltage value in the whole array is set through sequential gating of the grid leads, so that microfluid control is realized. For an mxn array, the leads are only M + N +2, which is a significant reduction in the number of leads compared to the existing microfluidic array controllers described in the background. When M is 100 and N is 100, the number of leads is only 202, which is much smaller than 10001 in the existing microfluidic array control method. Obviously, the method can realize large-scale microfluid array control by creatively combining the microfluid channel device, the thin film transistor device and the capacitor, and provides a new technical approach for the practicability of the microfluid control chip.

In another embodiment based on the above scheme, the microfluidic channel device comprises, in order from top to bottom, a top electrode, a top hydrophobic layer, a channel region, a bottom hydrophobic layer, an insulating layer 1, and a bottom electrode;

and liquid is arranged in the channel area.

The beneficial effects of the above technical scheme are: by applying a voltage to the top and bottom electrodes, the movement, division, fusion, etc. of the liquid in the channel can be controlled. The top hydrophobic layer and the bottom hydrophobic layer may reduce resistance to liquid movement within the microfluidic channel.

Further, the thin film transistor device includes a source electrode, a drain electrode, a semiconductor layer, a gate insulating layer, and a gate electrode;

the gate insulating layer is arranged above the gate electrode; the semiconductor layer is arranged above the gate insulating layer; the source electrode and the drain electrode are arranged on two sides of the semiconductor layer and are in contact with the semiconductor layer.

The beneficial effects of the above further scheme are as follows: the structure forms a thin film transistor which can play a role of a switch and reduce crosstalk among different control units.

Further, the capacitor comprises a top electrode, an insulating layer 2 and a ground electrode from top to bottom in sequence;

the top electrode and the ground electrode are made of at least one of aluminum, aluminum-silicon alloy, gold, platinum, molybdenum, copper, titanium and ITO;

the material of the insulating layer 2 is at least one of silicon oxide, hafnium oxide, aluminum oxide, titanium oxide and silicon nitride.

The beneficial effects of the above further scheme are as follows: because the operating voltage of the micro-fluid device is high, in order to prevent the capacitor from generating electric leakage and even breakdown, the insulating layer 2 made of materials such as silicon oxide, hafnium oxide, aluminum oxide, titanium oxide, silicon nitride and the like with high dielectric constant is used, so that the capacitance density of the capacitor can be improved on the premise of increasing the dielectric withstand voltage, and the capacitor can be matched with the voltage and current characteristics of the micro-fluid device.

Further, the source electrode and the drain electrode of the thin film transistor device are respectively made of at least one of aluminum, aluminum-silicon alloy, gold, platinum, molybdenum, copper, titanium and ITO; the distance between the source electrode and the drain electrode is 1-50 μm;

the semiconductor layer is made of at least one of amorphous silicon, indium gallium zinc oxide, tin oxide and polycrystalline silicon, and the thickness of the semiconductor layer is less than 200 nm;

the gate insulating layer is made of at least one of silicon oxide, hafnium oxide, aluminum oxide, titanium oxide, silicon nitride, parylene, photoresist and polytetrafluoroethylene, and the thickness of the gate insulating layer is 50 nm-1 mu m;

the gate electrode is made of at least one of aluminum, aluminum-silicon alloy, gold, platinum, molybdenum, copper, titanium and ITO, and the thickness of the gate electrode is 50-300 nm.

The beneficial effects of the above further scheme are as follows: in order to improve the driving capability of the thin film transistor, it is necessary to increase the capacitance of the gate insulating layer. The micro-fluid device has a high working voltage, and in order to prevent the gate insulating layer from electric leakage and even breakdown, the capacitance density of the gate insulating layer needs to be further improved by improving the dielectric constant of the dielectric layer, so that the dielectric property of the gate insulating layer can be improved by adopting materials with high dielectric constants such as hafnium oxide, aluminum oxide, silicon nitride, silicon oxide, parylene, photoresist, polytetrafluoroethylene and the like. The above dimensions are experimentally tested to achieve the best performance of the thin film transistor device.

Further, the top electrode and the bottom electrode of the microfluidic channel device are made of transparent conductive material ITO;

the top hydrophobic layer is made of an organic hydrophobic material or a structural hydrophobic material, and the thickness of the top hydrophobic layer is 1-200 nm; the distance between the top hydrophobic layer and the bottom hydrophobic layer is 1-200 mu m;

the liquid filled in the channel area is at least one of silicone oil, water or organic material;

the bottom hydrophobic layer material is an organic hydrophobic material or a micro-nano scale super-hydrophobic material, and the thickness is 1-200 nm;

the insulating layer 1 is made of at least one of silicon oxide, hafnium oxide, aluminum oxide, titanium oxide, silicon nitride, parylene, photoresist and polytetrafluoroethylene, and the thickness of the insulating layer is 30 nm-20 microns.

The beneficial effects of the above further scheme are as follows: through the insulating layer 1 that sets up high dielectric constant for the microfluid control voltage of this scheme drops to about 20V, compares with prior art's 50V, and control voltage obviously reduces, can satisfy the user demand. Meanwhile, the leakage current of the microfluid device is reduced, so that the microfluid device is matched with the performance of a thin film transistor device.

Furthermore, a side wall made of a hydrophilic insulating material is arranged at the edge of the channel area; the side wall of the hydrophilic insulating material is not in contact with the top hydrophobic layer;

the hydrophilic insulating material comprises photoresist, oxide and parylene.

The beneficial effects of the above further scheme are as follows: the side wall made of the hydrophilic insulating material can play a role in limiting the liquid flowing mode and position in the microfluidic device and positioning liquid.

Furthermore, the width and the length of the top electrode and the ground electrode of the capacitor are respectively 10-1500 mu m, and the thickness is 50-300 nm;

the thickness of the insulating layer 2 is 50nm to 1 μm.

The beneficial effects of the above further scheme are as follows: by setting the above dimensions, the driving capability of the thin film transistor device can be matched with the microfluidic device, so that the thin film transistor device can drive the microfluidic device of the corresponding cell under the limitation of the dimensions.

Further, the microfluidic array controller further comprises a passivation layer, and the thin film transistor device and the capacitor are connected with the microfluidic channel device through the passivation layer;

the thin film transistor device and the capacitor are arranged on two sides below the microfluidic channel device;

a window is provided in the top electrode of the microfluidic channel device above the semiconductor layer that overlaps the semiconductor layer area.

The beneficial effects of the above further scheme are as follows: by the scheme, the microfluidic array controller can be integrated. Because the operating voltage of the microfluidic channel device is high, when a certain control unit works, the conductivity of the lower semiconductor layer may be changed due to the high voltage, so that the leakage of the stored charges of the capacitor and the failure of the upper microfluidic channel device are caused.

Further, the top electrode of the capacitor is connected with the drain electrode of the thin film transistor;

the passivation layer above the capacitor top electrode is provided with a through hole, the top electrode of the capacitor and the drain electrode of the thin film transistor are electrically connected with the top electrode of the microfluidic channel device through the through hole, and the ground electrode of the capacitor is connected with the power supply 2.

The beneficial effects of the above further scheme are as follows: by arranging the capacitor to be connected with the thin film transistor, the voltage in the microfluidic channel device can be kept by utilizing the charge storage capacity of the capacitor, so that the performance of the microfluidic channel device is stable in the refreshing process.

In the invention, the technical schemes can be combined with each other to realize more preferable combination schemes. Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The drawings are only for purposes of illustrating particular embodiments and are not to be construed as limiting the invention, wherein like reference numerals are used to designate like parts throughout.

FIG. 1 is a schematic diagram of a prior art microfluidic array controller;

FIG. 2 is a schematic diagram of a microfluidic array controller according to example 1 of the present invention;

FIG. 3 is a schematic diagram of a control unit according to embodiment 1 of the present invention;

FIG. 4 is a structural diagram of a microfluidic array controller according to example 2 of the present invention;

fig. 5 is a schematic view of a window disposed on the top electrode in example 2 of the present invention.

Reference numerals:

11-a top electrode; 12-a top hydrophobic layer; 13-a channel region; 14-bottom water transfer layer; 15-insulating layer 1; 16-a bottom electrode; 130-a liquid; 21-a source electrode; 22-a drain electrode; 23-a semiconductor layer; 24-a gate insulating layer; 25-a gate electrode; 31-top electrode of capacitance; 32-insulating layer 2; 33-ground electrode of the capacitance; 4-a passivation layer; 40-through holes; 5-glass or silicon wafer substrate; 6-glass.

Detailed Description

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention and not to limit the scope of the invention.

Example 1

As shown in FIG. 2, one embodiment of the present invention discloses a microfluidic array controller. The microfluidic controller comprises M × N control units arranged in an array, a power supply 1 and a power supply 2.

As shown in fig. 3, each control unit includes a microfluidic channel device, a thin film transistor device (TFT), and a capacitor. The thin film transistor device and the capacitor are positioned below the microfluidic channel device and used as a control module. Each control unit is integrated.

In each row of the array, the gate electrodes of all the thin film transistor devices in the control units are connected and are connected with external corresponding row control signals, namely, each row control signal can gate each control unit in one row through the gate electrode in the row direction; in each column, the source electrodes of all the thin film transistor devices in the control unit are connected and are connected with external corresponding column control signals, namely, voltage values are written into the microfluidic channel device through the source electrodes of the thin film transistor devices in the column direction; the drain electrodes of all thin film transistor devices are connected to a power supply 1 via the corresponding microfluidic channel device and to a power supply 2 via the corresponding capacitor. The capacitance is used to hold a voltage signal on a microfluidic channel, which is a region within the microfluidic channel device through which microfluid (droplets or liquids) passes.

In implementation, because each microfluidic channel device is provided with liquid, under the combined action of the corresponding row control signal and the corresponding column control signal, the thin film transistor device gates the microfluidic channel device of the corresponding control unit, and the liquid moves, divides, fuses and the like in the microchannel of the microfluidic channel device. Specifically, one row is gated through a gate electrode lead in the row direction, and then a voltage value is written into the target microfluidic channel device through a source electrode lead in the column direction. The voltage value in the whole array is set through sequential gating of the grid leads, so that microfluid control is realized.

Compared with the prior art, the microfluidic array controller provided by the embodiment can accurately control the working state of the microfluidic channel device in each control unit through the row control signal and the column control signal, and for an M × N array, the number of leads is only M + N +2, so that compared with the prior microfluidic array controller in the background art, the number of leads is obviously reduced. When M is 100 and N is 100, the number of leads is only 202, which is much smaller than 10001 in the existing microfluidic array control method. Obviously, the method can realize large-scale microfluidic array control, and provides a new technical approach for the practicability of the microfluidic control chip.

Example 2

Based on the above-described embodiment, the microfluidic channel device comprises, in order from top to bottom, a top electrode 11, a top hydrophobic layer 12, a channel region 13, a bottom hydrophobic layer 14, an insulating layer 1(15), and a bottom electrode 16, as shown in fig. 4. The passage zone 13 is provided with a liquid 130. The top electrode 11 and the bottom electrode 16 serve as conductive layers for controlling the flow of the liquid 130. By applying voltages to the top electrode 11 and the bottom electrode 16, the movement, division, fusion, etc. of the liquid 130 in the channel can be controlled. The top hydrophobic layer 12 and the bottom water transfer layer 14 may reduce the resistance to movement of the liquid 130 within the microfluidic channel.

Preferably, the material of the top electrode 11 and the bottom electrode 16 of the microfluidic channel device is ITO, which is transparent and conductive, and the length, width and thickness of the two electrodes are set according to actual requirements. The top hydrophobic layer 12 is made of an organic hydrophobic material or a structural hydrophobic material, and the thickness of the top hydrophobic layer is 1-200 nm; the distance between the top hydrophobic layer 12 and the bottom water transfer layer 14, i.e. the height of the channel region 13, is 1-120 μm. The liquid 130 filled in the channel region 13 is at least one of silicone oil, water or organic material. The bottom water transfer layer 14 is made of an organic hydrophobic material or a structural hydrophobic material, such as polytetrafluoroethylene, and has a thickness of 1-200 nm. The insulating layer 1(15) is a single-layer or multi-layer structure formed by at least one of inorganic insulating materials (silicon oxide, hafnium oxide, aluminum oxide, titanium oxide and silicon nitride) or organic materials (parylene, photoresist and polytetrafluoroethylene), and the thickness of the single-layer or multi-layer structure is 30 nm-20 mu m.

Preferably, the edge of the microfluidic channel region 13 is provided with a side wall of a hydrophilic insulating material, not shown in fig. 4, the side wall of the hydrophilic insulating material is not in contact with the top hydrophobic layer 12, and may be made of photoresist, oxide, parylene, or other materials. The hydrophilic insulating material may be formed in a columnar or rectangular parallelepiped shape.

Preferably, the thin film transistor device includes a source electrode 21, a drain electrode 22, a semiconductor layer 23, a gate insulating layer 24, and a gate electrode 25. The gate insulating layer 24 is disposed over the gate electrode 25, the semiconductor layer 23 is disposed over the gate insulating layer 24, and the source electrode 21 and the drain electrode 22 are disposed on both sides of the semiconductor layer 23 and in contact with the semiconductor layer 23. The thin film transistor can play a role of a switch, and crosstalk between different control units is reduced. The source electrode 21 and the drain electrode 22 of the thin film transistor device are respectively made of at least one of aluminum, aluminum-silicon alloy, gold, platinum, molybdenum, copper, titanium and ITO; the distance between the source electrode 21 and the drain electrode 22 is 1-50 μm; the semiconductor layer 23 is made of at least one of amorphous silicon, indium gallium zinc oxide, tin oxide and polycrystalline silicon, and the thickness of the semiconductor layer is less than 200 nm; the gate insulating layer 24 is made of at least one of silicon oxide, hafnium oxide, aluminum oxide, titanium oxide, silicon nitride, parylene, photoresist and polytetrafluoroethylene, and the thickness of the gate insulating layer is 50 nm-1 μm; the gate electrode 25 is made of at least one of aluminum, aluminum-silicon alloy, gold, platinum, molybdenum, copper, titanium and ITO, and has a thickness of 50-300 nm. In order to improve the driving capability of the thin film transistor, the capacitance of the gate insulating layer 24 needs to be increased. The operating voltage of the micro-fluid device is high, and in order to prevent the gate insulating layer 24 from electric leakage and even breakdown, the dielectric constant of the dielectric layer needs to be increased to further increase the capacitance density of the gate insulating layer 24, so that the dielectric property of the gate insulating layer 24 can be improved by adopting high-dielectric-constant materials such as hafnium oxide, aluminum oxide, silicon nitride, silicon oxide, parylene, photoresist, polytetrafluoroethylene and the like. The above dimensions can be tested by a plurality of tests to achieve the best performance of the thin film transistor device.

Preferably, the capacitor comprises a top electrode 31, an insulating layer 2(32) and a ground electrode 33 in sequence from top to bottom. The top electrode 31 and the ground electrode 33 are made of at least one of aluminum, aluminum-silicon alloy, gold, platinum, molybdenum, copper, titanium and ITO, the width and the length of the top electrode 31 and the ground electrode 33 are respectively 10-1500 mu m, and the thickness is 50-300 nm; the material of the insulating layer 2(32) is at least one of silicon oxide, hafnium oxide, aluminum oxide, titanium oxide and silicon nitride, and the thickness thereof is 50nm to 1 μm. In this embodiment, the insulating layer 2(32) and the gate insulating layer 24 are the same layer, as shown in fig. 4, and one material is used.

Preferably, the microfluidic array controller further comprises a passivation layer 4, and the thin film transistor device and the capacitor are connected to the microfluidic channel device through the passivation layer 4. The thin film transistor device and the capacitor are arranged on two sides below the microfluidic channel device. The top electrode 31 of the capacitor is connected to the drain electrode 22 of the thin film transistor.

Preferably, the passivation layer 4 above the top electrode 31 of the capacitor is provided with a through hole 40, the top electrode 31 of the capacitor and the drain electrode 22 of the thin film transistor are electrically connected with the top electrode 11 of the microfluidic channel device through the through hole 40, and the ground electrode of the capacitor is connected with the power supply 2. By arranging the capacitor to be connected with the thin film transistor, the voltage in the microfluidic channel device can be kept by utilizing the charge storage capacity of the capacitor, so that the performance of the microfluidic channel device is stable in the refreshing process. The capacitor ground electrode is arranged on a silicon wafer or glass substrate 5.

In each control unit, the thin film transistor device and the capacitor are used as control modules, are positioned below the microfluidic channel device and are used for controlling the microfluidic channel device above so as to realize the function of microfluidic control.

Preferably, there is a window in the top electrode 11 of the microfluidic channel device that overlaps the region of the semiconductor layer 23, as shown in fig. 5. This window may reduce the influence of higher steering voltages on the underlying semiconductor layer 23. Specifically, since the operating voltage of the microfluidic channel device is high, when a certain control unit operates, the high voltage may cause the conductivity of the lower semiconductor layer 23 to change, which may cause leakage of the stored charge of the capacitor and failure of the upper microfluidic channel device.

Preferably, a layer of glass 6 is disposed on the top electrode 11 to prevent dust in the environment from contaminating the top electrode 11 and affecting the lifetime of the microfluidic array controller.

Compared with embodiment 1, the microfluidic array controller provided in this embodiment creatively provides a window on the top electrode 11, which can reduce the influence of the top high voltage on the performance of the thin film transistor device, and can enable the thin film transistor device to be applied in a voltage environment as high as 200V. At the same time, through the inventive design and optimization of the parameters, the relevant parameters enable the top electrode 11 to operate in a high voltage range consistent with microfluidic control.

Example 3

A method for preparing the microfluidic array controller of example 2, comprising the steps of:

s1, depositing a layer of metal on a silicon wafer or glass substrate 5 using physical vapor deposition (sputtering or evaporation), and patterning the metal using photolithography to form a gate electrode 25 of a thin film transistor device and a ground electrode 33 of a capacitor.

And S2, depositing a layer of gate insulating medium as a gate insulating layer 24 by using Chemical Vapor Deposition (CVD) such as Plasma Enhanced Chemical Vapor Deposition (PECVD), low-pressure vapor deposition (LPCVD), Atomic Layer Deposition (ALD) and the like.

And S3, depositing a layer of semiconductor film material by using chemical vapor deposition or physical vapor deposition, and patterning the film material by using a photoetching technology to enable the semiconductor film material to be positioned above the gate electrode 25 to serve as a semiconductor layer 23.

And S4, depositing a layer of metal by using physical vapor deposition (sputtering or evaporation), and patterning the metal by utilizing photoetching to form a source electrode 21 of the thin film transistor device and a top electrode 31 of the capacitor. The source electrode 21 and the drain electrode 22 are located on both sides of the semiconductor layer 23, and are in contact with the semiconductor layer 23, and the distance between the source electrode 21 and the drain electrode 22 is 1 to 50 μm.

S5, depositing an insulating passivation layer 4 by using chemical vapor deposition or physical vapor deposition, wherein the material of the passivation layer 4 can be one or a combination of more of silicon oxide, hafnium oxide, aluminum oxide, titanium oxide, silicon nitride and parylene.

And S6, forming a through hole 40 area on the passivation layer 4 by using photoetching and etching processes.

S7, depositing a layer of metal by using physical vapor deposition (sputtering or evaporation), and patterning the metal by utilizing photoetching to form a bottom electrode 16 of the microfluidic channel device. The bottom electrode 16 is electrically connected to the top electrode 31 of the capacitor through a via 40.

S8. depositing the insulating layer 1(15) using chemical vapor deposition, such as Plasma Enhanced Chemical Vapor Deposition (PECVD), low pressure vapor deposition (LPCVD), Atomic Layer Deposition (ALD).

S9, forming a bottom water conveying layer 14 by using a chemical vapor deposition or spin coating mode, wherein the bottom water conveying layer 14 can be an organic hydrophobic material or a chemical super-hydrophobic material, or a micro-nano scale super-hydrophobic structure. The insulating layer and the hydrophobic layer function to electrically insulate and reduce the resistance to liquid flow. Preferably, the bottom insulating material and the insulating layer may be formed of the same material having insulating and surface super-hydrophobic properties, such as photoresist, parylene, teflon, etc., wherein the photoresist may be SU8 photoresist.

S10. suspend the top hydrophobic layer 12 and the conductive layer above the top hydrophobic layer 12 above the bottom water transfer layer 14, with the distance between the top hydrophobic layer 12 and the bottom water transfer layer 14 being less than 120 μm. The top hydrophobic layer 12 may be, but is not limited to, an organic hydrophobic material, such as polytetrafluoroethylene, teflon, etc., or a structurally hydrophobic material, as well as a multi-layer material with surface hydrophobic properties formed with other insulating materials. The conducting layer is made of transparent conducting material ITO.

By the above steps, a channel region 13 is formed between the top hydrophobic layer 12 and the bottom water transfer layer 14. According to the control requirement, the following conditions can be adopted in the channel region 13:

case 1: an aqueous solution in which water is used as a solvent is filled, and the behavior of the aqueous solution is controlled by controlling the voltage of the top electrode 11.

Case 2: and silicone oil is filled in the gaps, so that the flow resistance of the aqueous solution is reduced.

Case 3: and forming a patterned side wall region in the gap, wherein the side wall region is not in contact with the top hydrophobic layer 12, and other regions in the channel region 13 are filled with a mixed solution or a multilayer solution formed by an aqueous solution and an oily liquid. The sidewall spacer can be, but is not limited to, an inorganic oxide, an organic material, such as parylene, photoresist, and the like.

Case 4: at the edges inside the gaps, patterned sidewall regions are formed, which act to support the top structure and are connected to the top hydrophobic layer 12. The sidewall spacer can be, but is not limited to, an inorganic oxide, an organic material, such as parylene, photoresist, and the like.

Preferably, in relation to the top electrode 11 in a single control unit, in order to reduce the influence of higher steering voltages on the underlying semiconductor layer 23, a window is provided above the semiconductor layer 23, as shown in fig. 5.

In implementation, the microfluidic controller can be formed by periodically arranging the control units in an array, wherein the number of rows and columns of the array can be arbitrarily expanded. The control voltage range between the gate electrode 25 and the source lead is 100V when the array is in operation.

Compared with the prior art, the microfluid array controller manufactured by the manufacturing method provided by the embodiment has few leads and low control voltage, can realize large-scale microfluid array control, and provides a new technical approach for the practicability of microfluid control chips.

Those skilled in the art will appreciate that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program, which is stored in a computer readable storage medium, to instruct related hardware. The computer readable storage medium is a magnetic disk, an optical disk, a read-only memory or a random access memory.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.

Claims

1. A microfluidic array controller comprising an MxN array formed by arranging MxN control units, a passivation layer, a power supply 1 and a power supply 2;

each control unit comprises a microfluidic channel device, a thin film transistor device and a capacitor; in each row of the array, the gate electrodes of all the thin film transistor devices are connected and connected with corresponding row control signals; in each column, the source electrodes of all the thin film transistor devices are connected and connected with corresponding column control signals; the drain electrodes of all the thin film transistor devices are connected with a power supply 1 through corresponding microfluidic channel devices and connected with a power supply 2 through corresponding capacitors; the thin film transistor device and the capacitor are respectively arranged on two sides below the microfluidic channel device; the thin film transistor device and the capacitor are connected with the microfluidic channel device through the passivation layer;

the microfluidic channel device sequentially comprises a top electrode, a top hydrophobic layer, a channel area, a bottom hydrophobic layer, an insulating layer 1 and a bottom electrode from top to bottom; liquid is arranged in the channel area, and the edge of the channel area is provided with a side wall made of hydrophilic insulating material; the side wall of the hydrophilic insulating material is not in contact with the top hydrophobic layer;

the thin film transistor device comprises a source electrode, a drain electrode, a semiconductor layer, a gate insulating layer and a gate electrode; the gate insulating layer is arranged above the gate electrode; the semiconductor layer is arranged above the gate insulating layer; the source electrode and the drain electrode are arranged on two sides of the semiconductor layer and are in contact with the semiconductor layer;

the capacitor comprises a top electrode, an insulating layer 2 and a ground electrode from top to bottom in sequence; the top electrode of the capacitor is connected with the drain electrode of the thin film transistor;

2. The microfluidic array controller of claim 1, wherein the material of the top and ground electrodes is at least one of aluminum, aluminum silicon alloy, gold, platinum, molybdenum, copper, titanium, ITO;

the insulating layer 2 is made of at least one of silicon oxide, hafnium oxide, aluminum oxide, titanium oxide and silicon nitride.

3. The microfluidic array controller according to claim 1 or 2, wherein the material of the source electrode and the drain electrode of the thin film transistor device is at least one of aluminum, aluminum-silicon alloy, gold, platinum, molybdenum, copper, titanium, and ITO; the distance between the source electrode and the drain electrode is 1-50 μm;

4. The microfluidic array controller of claim 1 or 2, wherein the material of the top and bottom electrodes of the microfluidic channel device is ITO;

the top hydrophobic layer is made of an organic hydrophobic material or a structural hydrophobic material, and the thickness of the top hydrophobic layer is 1-200 nm; the distance between the top hydrophobic layer and the bottom hydrophobic layer is 1-120 mu m;

the liquid filled in the channel region is at least one of water or organic materials;

the bottom hydrophobic layer is made of an organic hydrophobic material or a structural hydrophobic material, and the thickness of the bottom hydrophobic layer is 1-200 nm;

5. The microfluidic array controller of claim 1 or 2, wherein the hydrophilic insulating material comprises photoresist, oxide, parylene.

6. The microfluidic array controller according to claim 2, wherein the top electrode and the ground electrode of the capacitor have a width and a length of 10-1500 μm and a thickness of 50-300 nm, respectively;

the thickness of the insulating layer 2 is 50nm to 1 μm.

7. The microfluidic array controller of claim 1, wherein the passivation layer over the top electrode of the capacitor is provided with a via hole through which the top electrode of the capacitor and the drain electrode of the thin film transistor device are electrically connected to the top electrode of the microfluidic channel device, and the ground electrode of the capacitor is connected to the power supply 2.