CN114421796A - I-type three-level topological overcurrent sealing wave control method - Google Patents

I-type three-level topological overcurrent sealing wave control method Download PDF

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Publication number
CN114421796A
CN114421796A CN202111681396.7A CN202111681396A CN114421796A CN 114421796 A CN114421796 A CN 114421796A CN 202111681396 A CN202111681396 A CN 202111681396A CN 114421796 A CN114421796 A CN 114421796A
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China
Prior art keywords
wave
overcurrent protection
diode
sealing
tube
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CN202111681396.7A
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Chinese (zh)
Inventor
曾建友
陈利
周党生
文熙凯
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Shenzhen Hopewind Electric Co Ltd
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Shenzhen Hopewind Electric Co Ltd
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Priority to CN202111681396.7A priority Critical patent/CN114421796A/en
Publication of CN114421796A publication Critical patent/CN114421796A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/10—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers
    • H02H7/12—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers
    • H02H7/122—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for converters; for rectifiers for static converters or rectifiers for inverters, i.e. dc/ac converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention discloses an I-type three-level topological overcurrent wave-sealing control method which is applied to an I-type three-level power circuit, wherein the output end of the I-type three-level power circuit is connected with an inductive current sampling unit, the output end of the inductive current sampling unit is connected with an inductive overcurrent protection comparison unit, the inductive overcurrent protection comparison unit comprises a first-stage overcurrent protection comparison circuit and a second-stage overcurrent protection comparison circuit, and the output ends of the first-stage overcurrent protection comparison circuit and the second-stage overcurrent protection comparison circuit are connected with a wave-sealing unit; according to the I-type three-level topological overcurrent sealing wave control method, the turn-off times of the inner tube of the power tube in the use process of the I-type three-level photovoltaic inverter are reduced, so that the voltage stress is reduced, the imbalance of positive and negative buses is eliminated, and the service life of a product is prolonged.

Description

I-type three-level topological overcurrent sealing wave control method
Technical Field
The invention relates to a photovoltaic inverter design technology, in particular to an I-type three-level topological overcurrent and wave-sealing control method.
Background
In order to improve the adaptability of a power grid, when the power grid is subjected to flicker/disturbance, an overcurrent wave-sealing action needs to be executed in order to ensure that a power device is in a safe working area. Taking the currently common I-type three-level topology as an example, as shown in fig. 1, when a wave-by-wave current-limiting threshold value is reached, a wave-sealing operation is performed, the current scheme is to seal an outer tube first and then seal an inner tube, as shown in fig. 2, when an overcurrent occurs, the inner tube is turned off, and as a commutation path is large when the inner tube is turned off, the inner tube is subjected to a large stress each time the wave-by-wave current-limiting operation is performed, as shown in fig. 3; in addition, when the inner tube is turned off, the charge and discharge circuit of the positive and negative bus bars changes, and the normal charge and discharge circuit of the positive and negative bus bars is switched to the charge of the negative bus bar by taking the positive half cycle as an example, so that the positive bus bar falls and the negative bus bar rises, and further imbalance between the positive bus bar and the negative bus bar is caused as shown in fig. 4.
Fig. 1 is a schematic diagram of an I-type three-level topology, fig. 2 is a schematic diagram of wave-sealing logic of a wave-chasing current-limiting scheme in the prior art, fig. 3 is a schematic diagram of voltage stress generated by an inner tube during wave-chasing current limiting in the prior art, and fig. 4 is a schematic diagram of imbalance of positive and negative buses caused during the wave-chasing current-limiting scheme in the prior art.
As shown in fig. 2, an existing wave-by-wave current limiting scheme is that S1_ ge, S2_ ge, S3_ ge, and S4_ ge are driving signals of switching tubes S1, S2, S3, and S4, S1_ ge ', S2_ ge', S3_ ge ', and S4_ ge' are driving signals after overcurrent blocking of S1, S2, S3, and S4, and ocp1 is an overcurrent protection signal, where when an inductor current exceeds a protection threshold, an ocp1 signal is set low, when an ocp1 signal is detected to be low, an outer tube S1 is immediately turned off, and after a delay t2, an inner tube S2 is turned off and is not turned on again in a current switching period.
Fig. 3 shows a schematic diagram of a large stress borne by the inner tube when the inner tube is turned off, taking a positive half cycle PF equal to 1 as an example, when current limiting occurs wave by wave, the outer tube S1 is turned off first, then the inner tube S2 is turned off, and after the inner tube S2 is turned off, current needs to follow through D3 and D4 because the inductive current cannot suddenly change, a current converting loop at this time is a large current converting path, the parasitic inductance is large, and a large voltage stress is generated on the switching tube S2.
Disclosure of Invention
The invention aims to solve the technical problem of providing an I-type three-level topological overcurrent sealing wave control method, which reduces the turn-off times of an inner tube of a power tube in the use process of an I-type three-level photovoltaic inverter so as to reduce the voltage stress, eliminate the imbalance of a positive bus and a negative bus and prolong the service life of a product.
In order to solve the technical problems, the invention provides an I-type three-level topological overcurrent sealing wave control method, which is applied to an I-type three-level power circuit, wherein the output end of the I-type three-level power circuit is connected with an inductive current sampling unit, the output end of the inductive current sampling unit is connected with an inductive overcurrent protection comparison unit, the inductive overcurrent protection comparison unit comprises a first-stage overcurrent protection comparison circuit and a second-stage overcurrent protection comparison circuit, and the output ends of the first-stage overcurrent protection comparison circuit and the second-stage overcurrent protection comparison circuit are connected with a sealing wave unit;
the first stage overcurrent protection comparison circuit and the second stage overcurrent protection comparison circuit are used for judging the inductive current I output by the inductive current sampling circuitLAnd if the overcurrent is triggered, the first-stage overcurrent protection comparison circuit and the second-stage overcurrent protection comparison circuit carry out wave sealing on the outer pipe and the inner pipe of the power tube of the I-type three-level power circuit in a grading manner according to an overcurrent protection signal of the inductance overcurrent protection comparison unit.
Preferably, the first stage overcurrent protection comparison circuit is provided with a first overcurrent protection point Iocp1, and the second stage overcurrent protection circuit is provided with a second overcurrent protection point Iocp 2;
when the first-stage overcurrent protection comparison circuit judges that the inductive current output by the inductive current sampling circuit exceeds a first overcurrent protection point Iocp1, outputting an execution wave-sealing signal to a wave-sealing unit, wherein the wave-sealing unit executes wave-sealing operation on an outer tube of a power tube of the I-type three-level power circuit; the inductance overcurrent protection comparison unit judges that the current is reduced and then does not output a wave sealing signal to the wave sealing unit any more; after the wave sealing unit executes outer tube wave sealing of the power tube, the second-stage overcurrent protection comparison circuit judges that the output inductive current of the inductive current sampling circuit exceeds a second overcurrent protection point Iocp2, then a wave sealing execution signal is output to the wave sealing unit, and the wave sealing unit executes inner tube wave sealing of the power tube;
the first overcurrent protection point Iocp1 is smaller than the second overcurrent protection point Iocp 2.
Preferably, the type I three-level topology circuit includes a first capacitor C1, a second capacitor C2, a switch S1, a switch S2, a switch S3 and a switch S4, a diode D1, a diode D2, a diode D3, a diode D4 and a diode D4, wherein a collector of the switch S4 is connected to the BUS + terminal and the output terminal of the diode, an emitter of the switch S4 is connected to a collector of the power transistor S4, an input terminal of the diode D4 and the output terminal of the diode D4, a collector of the power transistor S4 is connected to the output terminal of the diode D4 and the output terminal of the diode D4, an emitter of the power transistor S4 is connected to the input terminal of the diode D4, an inductor L4 and the collector of the power transistor S4, a pole of the power transistor S4 is connected to the output terminal of the inductor L4 and the output terminal of the diode D4, an emitter of the power transistor S4 is connected to the input terminal of the diode S4, the collector of the power tube S4 is connected with the output end of the diode D4, the emitter of the power tube S4 is connected with the BUS-end and the input end of the diode D4, the output end of the diode D6 is connected with the input end of the diode D5, the switch tube S1 and the switch tube S4 are power tube outer tubes, and the switch tube S2 and the switch tube S3 are power tube inner tubes.
Preferably, the first stage overcurrent protection comparison circuit comprises a first comparator, and one input end of the first comparator is connected with an inductive current sampling signal ILThe other end of the input of the first comparator is connected with a first protection threshold value Iocp1, and the output signal of the first comparator is connected with a wave sealing unit; the second stage overcurrent protection comparison circuit comprises a second comparator, wherein one input end of the second comparator is connected with an inductive current sampling signal ILThe other end of the input of the second comparator is connected with a second protection threshold value Iocp2, and the output signal of the second comparator is connected withAnd a wave sealing unit.
Preferably, the wave sealing unit is used for controlling the time sequence of the inner pipe and the outer pipe of the power pipe, controlling the dead zone and limiting the minimum pulse width, and the wave sealing control is carried out through the coordination of the time sequence control, the dead zone control and the minimum pulse width limitation.
After the method is adopted, the I-type three-level topological overcurrent wave-sealing control method is applied to an I-type three-level power circuit, the output end of the I-type three-level power circuit is connected with an inductive current sampling unit, the output end of the inductive current sampling unit is connected with an inductive overcurrent protection comparison unit, the inductive overcurrent protection comparison unit comprises a first-stage overcurrent protection comparison circuit and a second-stage overcurrent protection comparison circuit, and the output ends of the first-stage overcurrent protection comparison circuit and the second-stage overcurrent protection comparison circuit are connected with a wave-sealing unit; the first stage overcurrent protection comparison circuit and the second stage overcurrent protection comparison circuit are used for judging the inductive current I output by the inductive current sampling circuitLIf the overcurrent is triggered, the first-stage overcurrent protection comparison circuit and the second-stage overcurrent protection comparison circuit carry out wave sealing on the outer pipe and the inner pipe of the power tube of the I-type three-level power circuit in a grading manner according to an overcurrent protection signal of the inductance overcurrent protection comparison unit; according to the I-type three-level topological overcurrent sealing wave control method, the turn-off times of the inner tube of the power tube in the use process of the I-type three-level photovoltaic inverter are reduced, so that the voltage stress is reduced, the imbalance of positive and negative buses is eliminated, and the service life of a product is prolonged.
Drawings
FIG. 1 is a control connection diagram of a type I three-level topology of the present invention;
FIG. 2 is a waveform diagram of a prior art wave-by-wave current limiting scheme;
FIG. 3 is a graph of voltage stress generated by the inner tube during current limiting wave-by-wave in the prior art;
FIG. 4 is a diagram of positive and negative bus imbalance caused by wave-by-wave current limiting in the prior art;
FIG. 5 is a waveform diagram of the first-stage wave-sealing of the I-type three-level topology over-current wave-sealing control method of the present invention;
FIG. 6 is a waveform diagram of the first and second stages of all-wave-blocking in the I-type three-level topology over-current wave-blocking control method of the present invention;
FIG. 7 is a diagram showing the voltage changes of positive and negative buses when the I-type three-level topology overcurrent sealing wave control method of the present invention seals only the outer tube with the overcurrent sealing wave;
FIG. 8 is a two-stage over-current wave-sealing connection block diagram of the I-type three-level topology over-current wave-sealing control method of the present invention;
FIG. 9 is a comparison circuit diagram of the over-current protection of the over-current wave-sealing control method of the I-type three-level topology of the present invention;
FIG. 10 is a logic control diagram of the wave-blocking unit of the type I three-level topology of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Example one
Referring to fig. 5 to 7, fig. 6 is a waveform diagram of the first and second two-stage total sealing waves of the I-type three-level topology overcurrent sealing wave control method of the present invention, and fig. 7 is a diagram of the voltage change of the positive and negative buses when the I-type three-level topology overcurrent sealing wave control method of the present invention seals only the outer tube with the overcurrent sealing wave; the embodiment discloses an I-type three-level topological overcurrent wave-sealing control method, which is applied to an I-type three-level power circuit and is characterized in that the output end of the I-type three-level power circuit is connected with an inductive current sampling unit, the output end of the inductive current sampling unit is connected with an inductive overcurrent protection comparison unit, the inductive overcurrent protection comparison unit comprises a first-stage overcurrent protection comparison circuit and a second-stage overcurrent protection comparison circuit, and the output ends of the first-stage overcurrent protection comparison circuit and the second-stage overcurrent protection comparison circuit are connected with a wave-sealing unit;
the first stage overcurrent protection comparison circuit and the second stage overcurrent protection comparison circuit are used for judging the inductive current I output by the inductive current sampling circuitLWhether to trigger over-current, the first stage over-current protection comparison circuit and the second stageAnd the secondary overcurrent protection comparison circuit carries out wave sealing on the outer pipe and the inner pipe of the power pipe of the I-type three-level power circuit in a grading manner according to the overcurrent protection signal of the inductance overcurrent protection comparison unit.
In this embodiment, the first stage of overcurrent protection comparison circuit is provided with a first overcurrent protection point Iocp1, and the second stage of overcurrent protection circuit is provided with a second overcurrent protection point Iocp 2;
when the first-stage overcurrent protection comparison circuit judges that the inductive current output by the inductive current sampling circuit exceeds a first overcurrent protection point Iocp1, outputting an execution wave-sealing signal to a wave-sealing unit, wherein the wave-sealing unit executes wave-sealing operation on an outer tube of a power tube of the I-type three-level power circuit; the inductance overcurrent protection comparison unit judges that the current is reduced and then does not output a wave sealing signal to the wave sealing unit any more; after the wave sealing unit executes outer tube wave sealing of the power tube, the second-stage overcurrent protection comparison circuit judges that the output inductive current of the inductive current sampling circuit exceeds a second overcurrent protection point Iocp2, then a wave sealing execution signal is output to the wave sealing unit, and the wave sealing unit executes inner tube wave sealing of the power tube;
the first overcurrent protection point Iocp1 is smaller than the second overcurrent protection point Iocp 2.
When the power grid is subjected to flicker or disturbance, the inductive current exceeds the first overcurrent protection point Iocp1, the first-stage overcurrent protection action is performed, and the wave sealing of the power tube outer tube is executed, if the inductive current does not rise to the second overcurrent protection point Iocp2, the switching frequency of the power tube inner tube during overcurrent wave sealing can be effectively reduced, and the voltage stress borne by the power tube inner tube due to turn-off is avoided.
In an I-type three-level topology, when the circuit works normally, the inductive current returns to the BUSN end from the BUS + end through the switch tube S1, the switch tube S2, the inductor L1 and the third capacitor C3, and the positive BUS is in a discharging state; when the wave-sealing unit only seals the outer tube, the inductive current flows from the BUSN end through the diode D5, the diode D2, the inductor L1 and the third capacitor C3 and then returns to the BUSN end, and the voltage of the positive bus and the negative bus cannot change, as shown in FIG. 7; when the wave sealing unit seals the outer tube and then seals the inner tube, current flows out from the BUS-end and returns to the BUSN end through the diode D4, the diode D3, the inductor L1 and the third capacitor C3, which is equivalent to charging the negative half BUS, and the voltage of the negative BUS is increased.
In this embodiment, the I-type three-level topology circuit includes a first capacitor C1, a second capacitor C2, a switch S1, a switch S2, a switch S3, a switch S4, a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, and a diode D6, wherein a collector of the switch S1 is connected to a BUS + terminal and an output terminal of the diode, an emitter of the switch S1 is connected to a collector of the power S1, an input terminal of the diode D1, and an output terminal of the diode D1, a collector of the power S1 is connected to an output terminal of the diode D1, an emitter of the power S1 is connected to an input terminal of the diode D1, an inductor L1 and a collector of the power S1, a pole of the power S1 is connected to an output terminal of the inductor L1 and an emitter of the diode D1, and the power S1 is connected to an emitter of the power S1, The input end of a diode D6, the collector of the power tube S4 is connected with the output end of a diode D4, the emitter of the power tube S4 is connected with a BUS-end and the input end of a diode D4, the output end of a diode D6 is connected with the input end of a diode D5, a switch tube S1 and a switch tube S4 are outer tubes of the power tube, and a switch tube S2 and a switch tube S3 are inner tubes of the power tube.
In this embodiment, the second stage of overcurrent protection comparison circuit outputs a signal for releasing the sealing of the wave sealing unit, and first opens the inner tube of the power tube of the I-type three-level power circuit, and the first stage of overcurrent protection comparison circuit outputs a signal for releasing the sealing of the wave sealing unit, and opens the outer tube of the power tube of the I-type three-level power circuit.
In this embodiment, the first stage of overcurrent protection comparison circuit includes a first comparator, and an input end of the first comparator is connected to the inductor current sampling signal ILThe other end of the input of the first comparator is connected with a first protection threshold value Iocp1, and the output signal of the first comparator is connected with a wave sealing unit; the second stage overcurrent protection comparison circuit comprises a second comparator, wherein one input end of the second comparator is connected with an inductive current sampling signal ILThe other end of the input of the second comparator is connected with a second protection threshold value Iocp2, and the output signal of the second comparatorThe signal is connected with the wave sealing unit.
Referring to fig. 10, fig. 10 is a logic control diagram of the wave-blocking unit of the type I three-level topology of the present invention. The wave sealing unit is used for controlling the time sequence of the inner pipe and the outer pipe of the power pipe, controlling the dead zone and limiting the minimum pulse width, and the wave sealing control is carried out through the coordination of the time sequence control, the dead zone control and the minimum pulse width limitation.
According to the I-type three-level topological overcurrent sealing wave control method, the turn-off times of the inner tube of the power tube in the use process of the I-type three-level photovoltaic inverter are reduced, so that the voltage stress is reduced, the imbalance of positive and negative buses is eliminated, and the service life of a product is prolonged.
It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.

Claims (5)

1. An I-type three-level topological overcurrent wave-sealing control method is applied to an I-type three-level power circuit and is characterized in that the output end of the I-type three-level power circuit is connected with an inductive current sampling unit, the output end of the inductive current sampling unit is connected with an inductive overcurrent protection comparison unit, the inductive overcurrent protection comparison unit comprises a first-stage overcurrent protection comparison circuit and a second-stage overcurrent protection comparison circuit, and the output ends of the first-stage overcurrent protection comparison circuit and the second-stage overcurrent protection comparison circuit are connected with a wave-sealing unit;
the first stage overcurrent protection comparison circuit and the second stage overcurrent protection comparison circuit are used for judging the inductive current I output by the inductive current sampling circuitLAnd if the overcurrent is triggered, the first-stage overcurrent protection comparison circuit and the second-stage overcurrent protection comparison circuit carry out wave sealing on the outer pipe and the inner pipe of the power tube of the I-type three-level power circuit in a grading manner according to an overcurrent protection signal of the inductance overcurrent protection comparison unit.
2. The over-current wave-sealing control method of the type-I three-level topology according to claim 1, wherein the first stage over-current protection comparison circuit sets a first over-current protection point Iocp1, and the second stage over-current protection circuit sets a second over-current protection point Iocp 2;
when the first-stage overcurrent protection comparison circuit judges that the inductive current output by the inductive current sampling circuit exceeds a first overcurrent protection point Iocp1, outputting an execution wave-sealing signal to a wave-sealing unit, wherein the wave-sealing unit executes wave-sealing operation on an outer tube of a power tube of the I-type three-level power circuit; the inductance overcurrent protection comparison unit judges that the current is reduced and then does not output a wave sealing signal to the wave sealing unit any more; after the wave sealing unit executes outer tube wave sealing of the power tube, the second-stage overcurrent protection comparison circuit judges that the output inductive current of the inductive current sampling circuit exceeds a second overcurrent protection point Iocp2, then a wave sealing execution signal is output to the wave sealing unit, and the wave sealing unit executes inner tube wave sealing of the power tube;
the first overcurrent protection point Iocp1 is smaller than the second overcurrent protection point Iocp 2.
3. The method according to claim 1, wherein the I-type three-level topology circuit comprises a first capacitor C1, a second capacitor C2, a switch tube S1, a switch tube S2, a switch tube S3 and a switch tube S4, a diode D1, a diode D2, a diode D3, a diode D4, a diode D5 and a diode D6, wherein a collector of the switch tube S1 is connected to a BUS + terminal and an output terminal of the diode, an emitter of the switch tube S1 is connected to a collector of the power tube S2, an input terminal of the diode D1 and an output terminal of the diode D5, a collector of the power tube S2 is connected to an output terminal of the diode D2 and an output terminal of the diode D2, an emitter of the power tube S2 is connected to an input terminal of the diode D2, an inductor L2 and a collector of the power tube S2, and poles of the power tube S2 are electrically connected to the inductor L2 and the output terminal of the diode D2, the emitter of the power tube S3 is connected to the collector of the power tube S4 and the input terminal of the diode D6, the collector of the power tube S4 is connected to the output terminal of the diode D4, the emitter of the power tube S4 is connected to the BUS terminal and the input terminal of the diode D4, the output terminal of the diode D6 is connected to the input terminal of the diode D5, the switch tube S1 and the switch tube S4 are outer tubes of the power tube, and the switch tube S2 and the switch tube S3 are inner tubes of the power tube.
4. The I-type three-level topology overcurrent envelope control method according to claim 3, wherein the first-stage overcurrent protection comparison circuit comprises a first comparator, and one input end of the first comparator is connected with an inductor current sampling signal ILThe other end of the input of the first comparator is connected with a first protection threshold value Iocp1, and the output signal of the first comparator is connected with a wave sealing unit; the second stage overcurrent protection comparison circuit comprises a second comparator, wherein one input end of the second comparator is connected with an inductive current sampling signal ILThe other end of the input of the second comparator is connected with a second protection threshold value Iocp2, and the output signal of the second comparator is connected with the wave sealing unit.
5. The type-I three-level topology overcurrent wave-sealing control method according to claim 3, wherein the wave-sealing unit is used for timing sequence control, dead zone control and minimum pulse width limitation of an inner pipe and an outer pipe of the power tube, and the wave-sealing control is performed through the coordination of the timing sequence control, the dead zone control and the minimum pulse width limitation.
CN202111681396.7A 2021-12-31 2021-12-31 I-type three-level topological overcurrent sealing wave control method Pending CN114421796A (en)

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* Cited by examiner, † Cited by third party
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CN114614685A (en) * 2022-05-09 2022-06-10 锦浪科技股份有限公司 T-shaped three-level overload operation system and working method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114614685A (en) * 2022-05-09 2022-06-10 锦浪科技股份有限公司 T-shaped three-level overload operation system and working method thereof

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