CN114420748A - Enhanced GaN device based on p-InGaN/GaN superlattice structure and preparation method thereof - Google Patents

Enhanced GaN device based on p-InGaN/GaN superlattice structure and preparation method thereof Download PDF

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CN114420748A
CN114420748A CN202111301947.2A CN202111301947A CN114420748A CN 114420748 A CN114420748 A CN 114420748A CN 202111301947 A CN202111301947 A CN 202111301947A CN 114420748 A CN114420748 A CN 114420748A
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layer
ingan
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张苇杭
樊昱彤
张进成
刘茜
付李煜
黄韧
许国富
文钰
郝跃
张晓东
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Guangzhou Institute of Technology of Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/157—Doping structures, e.g. doping superlattices, nipi superlattices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

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Abstract

The invention discloses an enhanced GaN device based on a p-InGaN/GaN superlattice structure and a preparation method thereof, and the device sequentially comprises the following components from bottom to top: the device comprises a substrate, a buffer layer, a first UID-GaN layer and a barrier layer, wherein the upper surfaces of the left side and the right side of the barrier layer are provided with a source electrode and a drain electrode; the barrier layer between the source electrode and the drain electrode is sequentially provided with a second UID-GaN layer, a p-InGaN/GaN superlattice layer and a gate electrode upwards; a passivation layer is arranged on the partial upper surface of the first UID-GaN layer, the barrier layer and the p-InGaN/GaN superlattice layer; and the source electrode, the drain electrode and the gate electrode are all provided with interconnection metal. The device structure provided by the invention reduces the influence of impurity scattering on the carrier mobility, improves the hole mobility, increases the hole concentration, improves the threshold voltage of the device, further improves the reliability of the device, and lays a foundation for realizing tamping of high-performance GaN-based power electronic devices and integrated circuits.

Description

Enhanced GaN device based on p-InGaN/GaN superlattice structure and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to an enhanced GaN device based on a p-InGaN/GaN superlattice structure and a preparation method thereof.
Background
With the development of semiconductor technology, wide band gap semiconductor materials represented by gallium nitride (GaN) are widely used in the fields of aerospace power supplies, civil appliances and the like. Although GaN is much higher in material and process costs than Si semiconductor devices that have matured early in the industry, GaN-based power electronic devices have high breakdown electric fields, high output power densities, and low switching power losses that are difficult to achieve with conventional Si-based devices. The rapid development of wide bandgap semiconductors represented by GaN will become the key to break through the limitations of conventional semiconductors and improve the breakdown voltage and power conversion efficiency of chips. Gallium nitride High Electron Mobility Transistors (HEMTs) show great promise in next generation high power, high frequency switching applications.
To meet fail-safe requirements in practical applications, enhancement devices with normally-off functionality are of paramount importance. The enhancement mode device is turned off in a zero bias state, that is, the enhancement mode device does not need to be driven by a negative gate voltage in a non-working state, so that the additional power loss of the circuit can be greatly reduced, which is necessary in a high-speed switching circuit, and meanwhile, the design of the circuit can be simplified due to the use of the enhancement mode device. In order to realize the enhancement type GaN device, various manufacturing methods are available in the industry, such as a trench gate enhancement type device, a fluorine ion implantation enhancement type device, a cascode enhancement type device, and a p-GaN gate enhancement type device. Among these structures, the p-GaN gate-enhanced HEMT is of great interest for its good performance, reliability and manufacturability, and its conventional structure is shown in fig. 1.
However, the current research for p-GaN gate enhancement devices still has some problems to be further optimized, such as lower p-type doping activation rate and Mg diffusion problem during high temperature activation, which will result in lower threshold voltage and cause reliability problem, and hinder further application of p-GaN gate enhancement devices.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an enhanced GaN device based on a p-InGaN/GaN superlattice structure and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
in a first aspect, the present invention provides an enhanced GaN device based on p-InGaN/GaN superlattice structure, comprising in sequence from bottom to top: the device comprises a substrate, a buffer layer, a first UID-GaN layer and a barrier layer, wherein the upper surfaces of the left side and the right side of the barrier layer are provided with a source electrode and a drain electrode; wherein the content of the first and second substances,
a second UID-GaN layer, a p-InGaN/GaN superlattice layer and a gate electrode are sequentially and upwards arranged on the barrier layer between the source electrode and the drain electrode;
passivation layers are arranged on part of the upper surface of the first UID-GaN layer, the barrier layer and the p-InGaN/GaN superlattice layer;
and the source electrode, the drain electrode and the gate electrode are all provided with interconnection metal.
In one embodiment of the invention, the barrier layer is made of AlGaN and has a thickness of 10-20 nm; wherein, the Al component is 15-25%.
In one embodiment of the present invention, the second UID-GaN layer has a thickness of 5 to 10 nm.
In one embodiment of the invention, the p-InGaN/GaN superlattice layer comprises a plurality of p-InGaN layers and p-GaN layers which are alternately arranged up and down; wherein the content of the first and second substances,
the thickness of each p-InGaN layer is 1-2 nm, and the In component is 5% -10%;
the thickness of each p-GaN layer is 5-10 nm.
In one embodiment of the invention, the p-InGaN/GaN superlattice layer has a thickness of 72-96 nm.
In one embodiment of the invention, the p-InGaN layer and the p-GaN layer are both doped with Mg at a doping concentration of 1 × 1019～5×1019cm-3。
In one embodiment of the invention, an n-GaN layer is further included between the p-InGaN/GaN superlattice layer and the gate electrode.
In one embodiment of the invention, the thickness of the n-GaN layer is 30-50 nm, Si is adopted for doping, and the doping concentration is 1 multiplied by 1016～5×1016cm-3。
In a second aspect, the invention provides a method for preparing an enhanced GaN device based on a p-InGaN/GaN superlattice structure, comprising the following steps:
step 1: sequentially extending a GaN buffer layer, a first UID-GaN, an AlGaN barrier layer, a second UID-GaN and a p-InGaN/GaN superlattice layer on a substrate to obtain a GaN epitaxial wafer;
step 2: etching the GaN epitaxial wafer to form a gate region of a device, and performing mesa etching again to form device isolation;
and step 3: preparing a source electrode and a drain electrode in source and drain regions at two sides of the device, and preparing a gate electrode on the p-InGaN/GaN superlattice layer;
and 4, step 4: growing a passivation layer on the whole surface of the sample;
and 5: and depositing metal on the source electrode, the drain electrode and the gate electrode to form interconnection metal, thereby completing the preparation of the device.
In an embodiment of the present invention, after step 1 and before step 2, further comprising:
step x: and an n-GaN layer is epitaxially grown on the p-InGaN/GaN superlattice layer.
The invention has the beneficial effects that:
1. on one hand, a layer of UID-GaN grows on the AlGaN barrier layer, so that the influence of impurity scattering on the carrier mobility is reduced, the hole mobility is improved, and the UID-GaN and the AlGaN are polarized to form two-dimensional hole gas, so that the hole concentration is increased, and the threshold voltage of the device is improved; on the other hand, a p-InGaN/GaN superlattice layer is added on the GaN layer, so that the activation energy of Mg impurities is reduced, high-concentration holes are obtained, and the threshold voltage of the device is further improved; meanwhile, the UID-GaN layer inhibits the diffusion of Mg ions in the p-InGaN/GaN superlattice layer to a bottom material, improves the reliability of the device, and lays a foundation for realizing a high-performance GaN-based power electronic device and an integrated circuit;
2. the invention also inhibits grid leakage and improves the positive grid voltage swing by growing a layer of n-GaN on the p-InGaN/GaN superlattice layer.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a p-GaN gate enhanced HEMT structure provided by the prior art;
FIG. 2 is a schematic structural diagram of an enhanced GaN device based on a p-InGaN/GaN superlattice structure according to an embodiment of the invention;
FIG. 3 is a schematic structural diagram of another enhanced GaN device based on a p-InGaN/GaN superlattice structure provided by the embodiment of the invention;
FIG. 4 is a p-GaN/AlGaN/GaN heterojunction energy band diagram and an enhanced GaN device heterojunction energy band diagram based on a p-InGaN/GaN superlattice structure provided by an embodiment of the invention;
FIG. 5 is a flow chart of a method for fabricating an enhanced GaN device based on a p-InGaN/GaN superlattice structure according to an embodiment of the invention;
fig. 6a to 6h are schematic diagrams illustrating a manufacturing process of an enhanced GaN device based on a p-InGaN/GaN superlattice structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 2, fig. 2 is a schematic structural diagram of an enhanced GaN device based on a p-InGaN/GaN superlattice structure according to an embodiment of the present invention, which sequentially includes, from bottom to top: the structure comprises a substrate 1, a buffer layer 2, a first UID-GaN layer 3 and a barrier layer 4, wherein the upper surfaces of the left side and the right side of the barrier layer 4 are provided with a source electrode 7 and a drain electrode 8; wherein the content of the first and second substances,
a second UID-GaN layer 5, a p-InGaN/GaN superlattice layer 6 and a gate electrode 9 are sequentially arranged on the barrier layer 4 between the source electrode 7 and the drain electrode 8 upwards;
a passivation layer 10 is arranged on the upper surface of part of the first UID-GaN layer 3, the barrier layer 4 and the p-InGaN/GaN superlattice layer 6;
the source electrode 7, the drain electrode 8, and the gate electrode 9 are provided with interconnection metal 11.
In the present embodiment, the substrate 1 is made of a silicon material; the buffer layer 2 is made of AlGaN and has the thickness of 1-5 mu m; the thickness of the first UID-GaN layer 3 is 300-500 nm; the barrier layer 4 is made of AlGaN material, the thickness of the AlGaN material is 10-20 nm, and the Al component is 15% -25%; the thickness of the second UID-GaN layer 5 is 5-10 nm.
Further, the p-InGaN/GaN superlattice layer 6 comprises a plurality of p-InGaN layers and p-GaN layers which are alternately arranged up and down; wherein the content of the first and second substances,
the thickness of each p-InGaN layer is 1-2 nm, and the In component is 5% -10%; the thickness of each p-GaN layer is 5-10 nm, that is, the thickness ratio of the p-InGaN layer to the p-GaN layer is 1:5, so that the p-InGaN/GaN superlattice layer 6 can be further marked as p- (InGaN)1/(GaN)5And (3) a layer.
Specifically, the p-GaN layer and the p-InGaN layer are repeatedly arranged for 6-16 times to form the p-InGaN/GaN superlattice layer 6 with the total thickness of 72-96 nm.
Preferably, the p-InGaN layer and the p-GaN layer are both doped with Mg, and the doping concentration is 1 x 1019～5×1019cm-3。
In the embodiment, the source electrode 7 and the drain electrode 8 are made of titanium, aluminum, nickel and gold from bottom to top, and titanium metal forms ohmic contact with the AlGaN barrier layer 4, and the thicknesses of the titanium metal and the AlGaN barrier layer are both 200-300 nm; the gate electrode 9 is made of titanium nitride, titanium and gold, forms a schottky contact with the p-InGaN/GaN superlattice layer 6, and has a thickness of 200nm to 350 nm.
The passivation layer 10 is made of Al2O3The material is 20-30 nm thick; the interconnection metal 11 is made of nickel and gold.
The enhanced GaN device based on the p-InGaN/GaN superlattice structure provided by the embodiment grows a layer of UID-GaN on the AlGaN barrier layer, so that the influence of impurity scattering on the carrier mobility is reduced, the hole mobility is improved, and the UID-GaN and the AlGaN are polarized to form two-dimensional hole gas, so that the hole concentration is increased, and the threshold voltage of the device is improved; on the other hand, a p-InGaN/GaN superlattice layer is added on the GaN layer, so that the activation energy of Mg impurities is reduced, high-concentration holes are obtained, and the threshold voltage of the device is further improved; meanwhile, the UID-GaN layer inhibits the diffusion of Mg ions in the p-InGaN/GaN superlattice layer to the bottom material, and the reliability of the device is improved.
In another embodiment of the present invention, an n-GaN layer 12 is further included between the p-InGaN/GaN superlattice layer 6 and the gate electrode 9; wherein the thickness of the n-GaN layer 12 is 30-50 nm, and Si is adopted for doping, and the doping concentration is 1 multiplied by 1016～5×1016cm-3. Referring to fig. 3, fig. 3 is a schematic structural view of another enhanced GaN device based on p-InGaN/GaN superlattice structure according to an embodiment of the present invention.
In the embodiment, the n-GaN layer is grown on the p-InGaN/GaN superlattice layer, so that the grid leakage is inhibited, and the forward grid voltage swing is improved.
To further verify the beneficial effects of the present invention, the present example also compares the heterojunction energy band of the enhanced GaN device based on p-InGaN/GaN superlattice structure with the existing p-GaN/AlGaN/GaN heterojunction energy band. Referring to fig. 4, fig. 4 is a p-GaN/AlGaN/GaN heterojunction energy band diagram and an enhanced GaN device heterojunction energy band diagram based on a p-InGaN/GaN superlattice structure provided by an embodiment of the present invention, wherein a solid line represents the enhanced GaN device heterojunction energy band based on the p-InGaN/GaN superlattice structure of the present invention, and a dotted line represents the existing p-GaN/AlGaN/GaN heterojunction energy band diagram.
As can be seen from FIG. 4, compared with the existing p-GaN/AlGaN/GaN enhancement type device, the enhancement type GaN device based on the p-InGaN/GaN superlattice structure obtains high-concentration holes, has a better depletion effect on two-dimensional electron gas, and further improves the threshold voltage of the device.
Example two
On the basis of the first embodiment, the embodiment provides a preparation method of an enhanced GaN device based on a p-InGaN/GaN superlattice structure. Referring to fig. 5, fig. 5 is a flowchart of a method for manufacturing an enhanced GaN device based on a p-InGaN/GaN superlattice structure according to an embodiment of the present invention, which includes the following steps:
step 1: and sequentially extending a GaN buffer layer, a first UID-GaN, an AlGaN barrier layer, a second UID-GaN and a p-InGaN/GaN superlattice layer on the substrate to obtain the GaN epitaxial wafer.
Specifically, a metal organic chemical vapor deposition process is adopted, and a GaN buffer layer, a first UID-GaN layer, an AlGaN barrier layer, a second UID-GaN layer and a p-InGaN/GaN superlattice layer are sequentially extended on a silicon substrate to obtain a silicon substrate GaN epitaxial wafer substrate.
Specifically, for the p-InGaN/GaN superlattice layer, a metal organic chemical vapor deposition process can be adopted, and the p-GaN and the p-InGaN are alternately deposited in a certain period to form the p-InGaN/GaN superlattice layer.
Step 2: and etching the GaN epitaxial wafer to form a gate region of the device, and performing mesa etching again to form device isolation.
Firstly, etching a second UID-GaN, p-InGaN/GaN superlattice layer outside a gate region by adopting photoetching and inductively coupled plasma etching processes to form a gate region of the device.
And then, carrying out mesa etching by adopting photoetching and inductively coupled plasma etching processes to expose source and drain regions of the two devices and simultaneously form device isolation.
And step 3: and preparing a source electrode and a drain electrode in source and drain regions at two sides of the device, and preparing a gate electrode on the p-InGaN/GaN superlattice layer.
31) Preparation of Source and Drain electrodes
Specifically, a source and drain region is defined by photoetching, and then a BOE solution with the ratio of 20:1 is used for cleaning the sample for 1min to remove the oxide of the source and drain region. By adopting an electron beam evaporation process, titanium metal with the thickness of 20-50nm, aluminum metal with the thickness of 100-150nm, nickel metal with the thickness of 30-60nm and gold metal with the thickness of 40-60nm are sequentially deposited on the AlGaN barrier layer to form a source electrode and a drain electrode of the enhanced GaN power electronic device based on the p-InGaN/GaN superlattice structure, and annealing is carried out for 30s in a nitrogen atmosphere at the temperature of 850 ℃ so that the source electrode and the drain electrode are in ohmic contact with the AlGaN barrier layer.
32) Preparing a gate electrode
And defining a gate region by adopting photoetching, cleaning the sample for 1min by using a BOE solution with the ratio of 20:1, and removing oxide in the gate region. And depositing titanium nitride metal with the thickness of 20-40nm, titanium metal with the thickness of 20-50nm and gold metal with the thickness of 200-250nm on the p-InGaN/GaN superlattice layer in sequence by adopting a magnetron sputtering process to form a gate electrode of the enhanced GaN power electronic device based on the p-InGaN/GaN superlattice structure.
And 4, step 4: a passivation layer was grown on the entire sample surface.
Specifically, an atomic layer deposition process is adopted to deposit aluminum oxide with the thickness of 20nm on the whole sample to form a passivation layer of the enhanced GaN power electronic device based on the p-InGaN/GaN superlattice structure.
And 5: and depositing metal on the source electrode, the drain electrode and the gate electrode to form interconnection metal, thereby completing the preparation of the device.
Before the interconnection metal is manufactured, the passivation layer is etched and opened to expose the manufacturing area of the interconnection metal. Specifically, a wet etching process is adopted, and BOE solution with the ratio of 20:1 is used for etching away aluminum oxide covering the source electrode, the drain electrode and the gate electrode; or etching the aluminum oxide covering the source electrode, the drain electrode and the gate electrode by adopting a reactive ion etching process.
And then, depositing nickel metal with the thickness of 20-50nm and gold metal with the thickness of 200-500 nm in the opening etching areas of the source electrode, the drain electrode and the gate electrode in sequence by adopting an electron beam evaporation process to form interconnection metal.
Thus, the preparation of the enhanced GaN device based on the p-InGaN/GaN superlattice structure is completed.
In another embodiment of the present invention, in order to further improve the gate withstand voltage and reduce the gate leakage, a layer of n-GaN is grown on the p-InGaN/GaN superlattice layer, that is, after step 1 and before step 2, the method further includes:
step x: and (3) extending an n-GaN layer on the p-InGaN/GaN superlattice layer.
Correspondingly, when the source and drain regions of the device are formed in the step 2, the n-GaN layer is also required to be etched, so that the enhanced GaN power electronic device with the n-GaN and based on the p-InGaN/GaN superlattice structure is formed.
In order to form a schottky contact between the gate electrode and the n-GaN layer, nickel metal and metal are used for preparing the gate electrode on the subsequent epitaxial n-GaN layer. Specifically, the method comprises the following steps: and defining a gate region by adopting photoetching, cleaning the sample for 1min by using a BOE solution with the ratio of 20:1, and removing oxide in the gate region. And sequentially depositing nickel metal with the thickness of 20-50nm and gold metal with the thickness of 200-250nm on the n-GaN by adopting a magnetron sputtering process to form a gate electrode of the enhanced GaN power electronic device with the n-GaN based on the p-InGaN/GaN superlattice structure.
EXAMPLE III
The process of the preparation method provided by the invention is described in detail below with reference to the accompanying drawings.
Referring to fig. 6a to 6h, fig. 6a to 6h are schematic diagrams illustrating a process for manufacturing an enhanced GaN device based on a p-InGaN/GaN superlattice structure according to an embodiment of the present invention, which specifically include:
s1: manufacturing silicon substrate GaN epitaxial wafer
Sequentially extending a GaN Buffer layer (GaN Buffer), a first UID-GaN layer, an AlGaN barrier layer, a second UID-GaN layer and p- (InGaN) on a Si substrate by adopting a metal organic chemical vapor deposition process1/(GaN)5And (4) forming a superlattice layer to obtain a silicon substrate GaN epitaxial wafer, as shown in FIG. 6 a.
S2: p-GaN etch
And etching the UID-GaN, p-InGaN/GaN superlattice layer outside the gate region by adopting photoetching and inductively coupled plasma etching processes to form a device gate region, as shown in figure 6 b.
S3: mesa isolation
And (4) performing mesa etching by adopting photoetching and inductively coupled plasma etching processes to form device isolation, as shown in fig. 6 c.
S4: source electrode S and drain electrode D are fabricated as shown in fig. 6D. See step 31 in example two for a detailed procedure).
S5: a gate electrode S is fabricated as shown in fig. 6 e. See step 32 in example two for a detailed procedure).
S6: growth of passivated media
An atomic layer deposition process was used to deposit 20nm thick aluminum oxide on the entire sample to form a passivation layer for an enhanced GaN power electronic device based on a p-InGaN/GaN superlattice structure, as shown in fig. 6 f.
S7: etching and opening passivation layer
Etching the aluminum oxide covering the source electrode, the drain electrode and the gate electrode by using a 20:1 BOE solution by adopting a wet etching process; or a reactive ion etching process is used to etch away the aluminum oxide covering the source electrode, the drain electrode and the gate electrode, as shown in fig. 6 g.
S8: evaporation of interconnected metals
And sequentially depositing nickel metal with the thickness of 20nm and gold metal with the thickness of 200nm in the opening etching areas of the source electrode, the drain electrode and the gate electrode to form interconnection metal, as shown in figure 6 h.
Thus, the preparation of the enhanced GaN device based on the p-InGaN/GaN superlattice structure is completed.
In the description of the present invention, it is to be understood that the terms "thickness", "upper", "lower", "left", "right", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. An enhancement mode GaN device based on a p-InGaN/GaN superlattice structure is characterized by sequentially comprising from bottom to top: the thin film transistor comprises a substrate (1), a buffer layer (2), a first UID-GaN layer (3) and a barrier layer (4), wherein the upper surfaces of the left side and the right side of the barrier layer (4) are provided with a source electrode (7) and a drain electrode (8); wherein the content of the first and second substances,
a second UID-GaN layer (5), a p-InGaN/GaN superlattice layer (6) and a gate electrode (9) are sequentially arranged upwards on the barrier layer (4) between the source electrode (7) and the drain electrode (8);
a passivation layer (10) is arranged on the upper surface of part of the first UID-GaN layer (3), the barrier layer (4) and the p-InGaN/GaN superlattice layer (6);
and interconnection metal (11) is arranged on the source electrode (7), the drain electrode (8) and the gate electrode (9).
2. The enhancement mode GaN device based on the p-InGaN/GaN superlattice structure according to claim 1, wherein the barrier layer (4) is made of AlGaN and has a thickness of 10-20 nm; wherein, the Al component is 15-25%.
3. The enhanced GaN device based on p-InGaN/GaN superlattice structure according to claim 1, wherein the thickness of the second UID-GaN layer (5) is 5-10 nm.
4. The enhanced GaN device based on p-InGaN/GaN superlattice structure according to claim 1, characterized in that the p-InGaN/GaN superlattice layer (6) comprises several p-InGaN layers and p-GaN layers arranged alternately up and down; wherein the content of the first and second substances,
the thickness of each p-InGaN layer is 1-2 nm, and the In component is 5% -10%;
the thickness of each p-GaN layer is 5-10 nm.
5. An enhanced GaN device based on p-InGaN/GaN superlattice structure according to claim 4, characterized in that the p-InGaN/GaN superlattice layer (6) has a thickness of 72-96 nm.
6. p-In based according to claim 4The enhanced GaN device with the GaN/GaN superlattice structure is characterized in that the p-InGaN layer and the p-GaN layer are doped with Mg, and the doping concentration is 1 multiplied by 1019～5×1019cm-3。
7. An enhanced GaN device based on p-InGaN/GaN superlattice structure according to claim 1, characterized by further comprising an n-GaN layer (12) between the p-InGaN/GaN superlattice layer (6) and the gate electrode (9).
8. The p-InGaN/GaN superlattice structure-based enhanced GaN device according to claim 7, wherein the n-GaN layer (12) has a thickness of 30-50 nm, is doped with Si at a concentration of 1 x 1016～5×1016cm-3。
9. A preparation method of an enhanced GaN device based on a p-InGaN/GaN superlattice structure is characterized by comprising the following steps:
step 1: sequentially extending a GaN buffer layer, a first UID-GaN, an AlGaN barrier layer, a second UID-GaN and a p-InGaN/GaN superlattice layer on a substrate to obtain a GaN epitaxial wafer;
step 2: etching the GaN epitaxial wafer to form a gate region of a device, and performing mesa etching again to form device isolation;
and step 3: preparing a source electrode and a drain electrode in source and drain regions at two sides of the device, and preparing a gate electrode on the p-InGaN/GaN superlattice layer;
and 4, step 4: growing a passivation layer on the whole surface of the sample;
and 5: and depositing metal on the source electrode, the drain electrode and the gate electrode to form interconnection metal, thereby completing the preparation of the device.
10. The method of claim 9, further comprising, after step 1 and before step 2:
step x: and an n-GaN layer is epitaxially grown on the p-InGaN/GaN superlattice layer.
CN202111301947.2A 2021-11-04 2021-11-04 Enhanced GaN device based on p-InGaN/GaN superlattice structure and preparation method thereof Pending CN114420748A (en)

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