CN114420173B

CN114420173B - Memory structure and semiconductor memory

Info

Publication number: CN114420173B
Application number: CN202210060541.8A
Authority: CN
Inventors: 曹玲玲
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-01-19
Filing date: 2022-01-19
Publication date: 2024-02-06
Anticipated expiration: 2042-01-19
Also published as: CN114420173A

Abstract

The embodiment of the disclosure provides a storage structure and a semiconductor memory, wherein the storage structure comprises a control module, a plurality of signal processing modules and a plurality of BG modules correspondingly connected with the plurality of signal processing modules; the control module is used for receiving the initial command signal and carrying out delay processing on the initial command signal to obtain a target control signal; the signal processing module is used for receiving the BG signal and the target control signal, and carrying out signal combination processing on the BG signal and the target control signal to obtain a target signal with BG information; the BG signal carries BG information, and the BG information is used for determining a BG module which is correspondingly transmitted by the target signal. Therefore, the storage structure can eliminate deviation of signals in the transmission process, so that signal transmission time sequences are uniform, the circuit area can be reduced, and static power consumption is saved.

Description

Memory structure and semiconductor memory

Technical Field

The present disclosure relates to the field of memory technologies, and in particular, to a memory structure and a semiconductor memory.

Background

With the continuous development of semiconductor technology, higher and higher requirements are being placed on the data transmission speed when manufacturing and using devices such as computers. In order to obtain a faster Data transmission speed, a series of devices such as a memory capable of transmitting Data at Double Data Rate (DDR) have been developed.

In the related art, a memory unit (cell) is generally divided into a plurality of memory Bank Groups (BG), and when different BGs work, a control signal entering the BG needs to distinguish different BG information first; in addition, a plurality of central control modules (Center control block) generating control signals are correspondingly arranged. However, for these multiple central control modules, even if the circuits are identical, there may be deviations in the process of transmitting signals to different BGs due to layout routing, process manufacturing, etc., thereby affecting the memory operation.

Disclosure of Invention

The present disclosure provides a memory structure and a semiconductor memory device capable of eliminating deviation of signals in a transfer process so that signal transfer timings are uniform, and also capable of reducing a circuit area and saving static power consumption.

In a first aspect, an embodiment of the present disclosure provides a storage structure, where the storage structure includes a control module, a plurality of signal processing modules, and a plurality of BG modules correspondingly connected to the plurality of signal processing modules; wherein,

the control module is used for receiving an initial command signal and carrying out delay processing on the initial command signal to obtain a target control signal;

The signal processing module is used for receiving the BG signal and the target control signal, and carrying out signal combination processing on the BG signal and the target control signal to obtain a target signal with BG information; the BG signal carries BG information, and the BG information is used for determining a BG module which is correspondingly sent by the target signal.

In some embodiments, the control module and the plurality of signal processing modules are located at a central location of the storage structure, and the plurality of signal processing modules are distributed around the control module and are in a vertically and laterally symmetric structure.

In some embodiments, the plurality of BG modules are in one-to-one correspondence with the plurality of signal processing modules; the plurality of BG modules are located at peripheral positions of the storage structure, and are in a vertically and laterally symmetrical structure.

In some embodiments, the plurality of BG modules includes a first BG module, a second BG module, a third BG module, and a fourth BG module, and the plurality of signal processing modules includes a first signal processing module, a second signal processing module, a third signal processing module, and a fourth signal processing module; wherein,

the first BG module is located at the upper left position of the first signal processing module, the second BG module is located at the upper right position of the second signal processing module, the third BG module is located at the lower left position of the third signal processing module, and the fourth BG module is located at the lower right position of the fourth signal processing module.

In some embodiments, the memory structure further includes a first connection line, a second connection line, a third connection line, and a fourth connection line; wherein,

the first connecting wire is used for connecting the first signal processing module and the first BG module;

the second connecting wire is used for connecting the second signal processing module and the second BG module;

the third connecting wire is used for connecting the third signal processing module and the third BG module;

the fourth connecting wire is used for connecting the fourth signal processing module and the fourth BG module.

In some embodiments, the first connection line, the second connection line, the third connection line, and the fourth connection line are in a vertically and laterally symmetrical structure.

In some embodiments, the control module includes a number of delay sub-modules, wherein,

the control module is specifically configured to perform delay processing on the initial command signal through the plurality of delay sub-modules, so as to obtain the target control signal.

In some embodiments, the initial command signal includes at least one of: a write command signal and a read command signal;

the target control signal includes at least one of: column address decode control signals, local data line LIO precharge control signals, local data line LIO write enable signals, and local data line LIO read enable signals.

In some embodiments, the BG module is configured to correspondingly receive the target signal according to the BG information, and perform at least one of the following operations according to the target signal:

control column address decoding operations, control local data line LIO precharge operations, control local data line LIO write enable operations, and control local data line LIO read enable operations.

In some embodiments, the signal processing module is composed of a number of nand gates and nor gates.

In some embodiments, the memory structure further comprises a coding module; wherein,

the decoding module is used for receiving an input signal and performing decoding processing on the input signal to obtain at least one BG signal and the initial command signal.

In some embodiments, the at least one BG signal includes a first BG signal carrying BG information indicative of a first BG module and a second BG signal carrying BG information indicative of a second BG module, the first BG module being connected to a first signal processing module, the second BG module being connected to a second signal processing module; wherein,

the first signal processing module is configured to receive the first BG signal and the target control signal, perform signal combination processing on the first BG signal and the target control signal, obtain a first target signal, and correspondingly send the first target signal to the first BG module;

The second signal processing module is configured to receive the second BG signal and the target control signal, perform signal combination processing on the second BG signal and the target control signal, obtain a second target signal, and send the second target signal to the second BG module correspondingly.

In some embodiments, the at least one BG signal further comprises a third BG signal and a fourth BG signal, wherein the third BG signal carries BG information indicating a third BG module, the fourth BG signal carries BG information indicating a fourth BG module, and the third BG module is connected to a third signal processing module, and the fourth BG module is connected to a fourth signal processing module; wherein,

the third signal processing module is configured to receive the third BG signal and the target control signal, perform signal combination processing on the third BG signal and the target control signal, obtain a third target signal, and correspondingly send the third target signal to the third BG module;

the fourth signal processing module is configured to receive the fourth BG signal and the target control signal, perform signal combination processing on the fourth BG signal and the target control signal, obtain a fourth target signal, and send the fourth target signal to the fourth BG module correspondingly.

In a second aspect, embodiments of the present disclosure provide a semiconductor memory including a memory structure as described in the first aspect.

In some embodiments, the semiconductor memory is a dynamic random access memory chip.

The embodiment of the disclosure provides a storage structure and a semiconductor memory, wherein the storage structure comprises a control module, a plurality of signal processing modules and a plurality of BG modules correspondingly connected with the plurality of signal processing modules; the control module is used for receiving the initial command signal and carrying out delay processing on the initial command signal to obtain a target control signal; the signal processing module is used for receiving the BG signal and the target control signal, and carrying out signal combination processing on the BG signal and the target control signal to obtain a target signal with BG information; the BG signal carries BG information, and the BG information is used for determining a BG module which is correspondingly transmitted by the target signal. Therefore, the initial command signal entering the control module does not distinguish the BG information, so that the delay processing of the initial command signal can be realized by only one control module, a target control signal is obtained, and the target control signal and the BG signal carrying the BG information are combined into the target signal through the signal processing module and then sent to the corresponding BG module for working; therefore, the deviation of signals in the transmission process can be eliminated, so that the signal transmission time sequence is uniform, the circuit area can be reduced, and the static power consumption can be saved.

Drawings

FIG. 1 is a schematic diagram of a memory structure;

FIG. 2 is a schematic diagram of a central control module;

FIG. 3 is a schematic diagram of another memory structure;

FIG. 4 is a schematic diagram illustrating a memory structure according to an embodiment of the disclosure;

FIG. 5 is a schematic diagram illustrating another memory structure according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram illustrating the composition of a further memory structure provided by an embodiment of the present disclosure;

FIG. 7 is a schematic diagram illustrating the composition of a further memory structure according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a memory structure according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a specific structure of a control module according to an embodiment of the disclosure;

fig. 10 is a schematic diagram of a specific structure of a signal processing module according to an embodiment of the disclosure;

fig. 11 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present disclosure. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

It should be noted that the term "first\second\third" in relation to the embodiments of the present disclosure is merely to distinguish similar objects and does not represent a particular ordering for the objects, it being understood that the "first\second\third" may be interchanged in a particular order or sequencing where allowed, so that the embodiments of the present disclosure described herein may be implemented in an order other than that illustrated or described herein.

It can be understood that in the fourth-generation double data rate (4th Double Data Rate,DDR4) chip, the cells (cells) storing information are generally divided into four Banks (BG), when different BGs work, the control signals entering the BG need to be first distinguished into different BG information, and the circuit generating the control signals is a central control module (Center control block), and the central control module also corresponds to four. When different BGs are operating, it is desirable that the time required for the control signal to enter each BG be the same, so four central control modules need to be distributed symmetrically.

However, in the current common architecture, even if the circuits are identical for the four central control modules, the circuits may be also due to layout routing, process manufacturing and other reasons, and in the process of transmitting signals to different BGs, deviations are inevitably generated, so that the time sequence is not uniform, and the operation of the memory is affected.

Referring to fig. 1, a schematic composition of a memory structure 10 is shown. As shown in fig. 1, the storage structure 10 may include four BG modules BG0 (1011), BG1 (1012), BG2 (1013), and BG3 (1014), and a middle area 102. The four BG modules are symmetrically distributed in the storage structure 10, and the middle area 102 includes four central control modules corresponding to the four BG modules. In order to make the control signals into the 4 BG modules as symmetrical as possible, four central control modules are typically placed in the middle, as shown in fig. 1. Usually only one BG module works at the same time, and only in the X16 mode, two BG modules work simultaneously, which is specific to the X16 architecture.

For a specific distribution of four central control modules, see fig. 2, which shows a schematic of the distribution of one central control module. As shown in fig. 2, in the middle area, four central control modules (abbreviated as CTRL) are symmetrically distributed, and the four central control modules correspond to the four BG modules. Wherein, the first central control module 1011 (abbreviated as BG0 CTRL) represents a central control module corresponding to BG0, the second central control module 1012 (abbreviated as BG1 CTRL) represents a central control module corresponding to BG1, the third central control module 1013 (abbreviated as BG2 CTRL) represents a central control module corresponding to BG2, and the fourth central control module 1014 (abbreviated as BG3 CTRL) represents a central control module corresponding to BG 3. In this distributed structure, four central control modules may cause congestion in the middle area, and burden the layout and wiring of the circuit.

Referring to fig. 3, a schematic diagram of the composition of another memory structure 10 is shown. As shown in fig. 3, the storage structure 10 may include a decoding Block 103 (abbreviated as DEC or DEC module), four BG modules: BG0 (1011), BG1 (1012), BG2 (1013), and BG3 (1014), and four central control modules: a first central control module 1021, a second central control module 1022, a third central control module 1023, and a fourth central control module 1024.

In operation of the memory structure 10 shown in fig. 3, signals transmitted from Address (Address) ports are passed through the decoding module 103 to distinguish read/write command signals (RD/WR) having different BG information. In fig. 3, the read/write command signals having different BG information mainly include: bg0_read/write command signal (abbreviated bg0_rd/WR), bg1_read/write command signal (abbreviated bg1_rd/WR), bg2_read/write command signal (abbreviated bg2_rd/WR), and bg3_read/write command signal (abbreviated bg3_rd/WR). Then, these bg_read/write command signals with different BG information reenter the corresponding central control module to operate, where "×" indicates any one of values 0, 1, 2, 3, etc.

In the memory structure 10 shown in fig. 3, the bg_read/write command signal from the decoding module 103, from which the BG information is distinguished, is processed by the delay unit in the central control module, and four sets of corresponding control signals are generated to enter different BG modules, so that the time used in the process of entering the different BG modules by the corresponding control signals is the same, and when the control signals enter the different BG modules, the control signals can be matched and symmetrical.

However, as can be seen from fig. 3, the four central control modules cannot be placed at the same location, which causes different time taken for the BG-like read/write command signals corresponding to different BG modules to enter the central control modules, and thus causes time deviation.

Thus, in the memory structure 10 shown in fig. 3, the signal coming out of the decoding module 103 (i.e., bg_read/write command signal) already has BG information, so the middle area needs to be made with four central control modules. And because the four central control modules are different in position, wiring is not uniform, and time deviation of signal transmission can be generated. In addition, the BG-type read/write command signal, after entering the corresponding central control module, passes through a series of delay units to generate various control signals, and when the control signals enter different BG modules, the time required for the control signals is expected to be the same. However, due to the architecture limitation of the memory structure 10, the time taken for the control signal to enter different BG modules will also be different during the signal transmission process, resulting in non-uniformity in timing.

Based on this, the embodiment of the disclosure provides a storage structure, which includes a control module, a plurality of signal processing modules, and a plurality of BG modules correspondingly connected to the plurality of signal processing modules; the control module is used for receiving the initial command signal and carrying out delay processing on the initial command signal to obtain a target control signal; the signal processing module is used for receiving the BG signal and the target control signal, and carrying out signal combination processing on the BG signal and the target control signal to obtain a target signal with BG information; the BG signal carries BG information, and the BG information is used for determining a BG module which is correspondingly transmitted by the target signal. Therefore, the initial command signal entering the control module does not distinguish the BG information, so that the delay processing of the initial command signal can be realized by only one control module, a target control signal is obtained, and the target control signal and the BG signal carrying the BG information are combined into the target signal through the signal processing module and then sent to the corresponding BG module for working; therefore, the deviation of signals in the transmission process can be eliminated, so that the signal transmission time sequence is uniform, the circuit area can be reduced, and the static power consumption can be saved.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In one embodiment of the present disclosure, reference is made to fig. 4, which illustrates a schematic composition of a memory structure 40 provided by an embodiment of the present disclosure. As shown in fig. 4, the storage structure 40 may include a control module 401, a plurality of signal processing modules 402, and a plurality of BG modules 403 correspondingly connected to the plurality of signal processing modules 402; wherein,

the control module 401 is configured to receive an initial command signal, and perform delay processing on the initial command signal to obtain a target control signal;

the signal processing module 402 is configured to receive the BG signal and the target control signal, and perform signal combination processing on the BG signal and the target control signal to obtain a target signal with BG information; the BG signal carries BG information, and the BG information is used to determine a BG module 403 that corresponds to the target signal and sends the target signal.

It should be noted that, taking the storage structure 40 shown in fig. 4 as an example, the storage structure 40 may include one control module 401, four signal processing modules 402, and four BG modules 403; the control module 401 receives the initial command signal, delays the initial command signal to obtain a target control signal, and then transmits the target control signal to the corresponding signal processing module 402.

It should be further noted that, in the embodiment of the present disclosure, a signal processing module 402 is correspondingly connected to a BG module 403, where the signal processing module 402 receives BG signals and the target control signals transmitted by the control module 401; the BG signals carry BG information, and the BG information indicates corresponding BG modules. The signal processing module 402 performs a combination process on the BG signal and the target control signal to obtain a target signal with BG information, so that a BG module corresponding to the target signal can be determined, and the target signal is sent to the corresponding BG module. Thus, since the embodiment of the present disclosure is provided with only one control module, compared with fig. 3 in the related art, not only can the circuit area be reduced, but also the deviation of the signal in the transfer process can be eliminated, so that the signal transfer timing is uniform.

It should also be noted that, for the initial command signal and the BG signal, embodiments of the present disclosure may be output by the decoding module. Thus, in some embodiments, referring to fig. 5, a schematic diagram of the composition of another memory structure 40 provided by an embodiment of the present disclosure is shown, based on the memory structure 40 shown in fig. 4. As shown in fig. 5, the memory structure 40 may further include a decode module 404; wherein,

The decoding module 404 is configured to receive an input signal, and decode the input signal to obtain at least one BG signal and an initial command signal.

It should be noted that, the decoding module 404 receives an input signal and decodes the input signal, so as to obtain at least one BG signal and an initial command signal; then the initial command signal is sent to the control module 401 through the decoding module 404, and the initial command signal at this time does not carry BG information, so that the delay processing of the initial command signal can be realized through only one control module 401; meanwhile, the decoding module 404 also sends at least one BG signal to the signal processing module 402, and since the BG signal carries BG information, each BG signal can be sent to the corresponding signal processing module 402; after the control module 401 processes the initial command signal into the target control signal, it is also transferred to the signal processing module 402; the signal processing module 402 combines the BG signal and the target control signal into a target signal with BG information, and sends the target signal to the corresponding BG module 403.

Compared to the memory structure 10 shown in fig. 3, the embodiment of the disclosure combines the central control modules corresponding to the BG modules into one control module 401; in the decoding module 404, no BG information is distinguished from the initial command signal, that is, the initial command signal sent to the control module 401 does not distinguish which BG module is, and the BG signal carrying the BG information is directly transferred to the corresponding signal processing module 402; after the control module 401 processes the initial command signal to obtain a target control signal, the target control signal is sent to the signal processing module 402; the signal processing module 402 combines the target control signal with the BG signal to obtain a target signal having a different BG signal.

In this way, since the BG information is not discriminated from the initial command signal, the signal transmission deviation due to the difference in wiring is not involved by processing by one control module 401, and the deviation in signal transmission can be eliminated. In addition, only one control module 401 can also reduce the area of the wiring layout and reduce the static power consumption of the circuit.

It should be further noted that, as shown in fig. 5, when the initial command signal sent by the decoding module 404 does not have BG information, the four central control modules may be combined together, that is, the control module 401. In this way, deviations of the signals from the decoding module to the central control module can be eliminated compared to the memory structure 10 shown in fig. 3.

It should be further noted that, after the initial command signal passes through the control module 401, the various generated target control signals still need to enter into different BG modules to operate, and at this time, BG information still needs to be distinguished. Therefore, in the embodiment of the disclosure, the signal processing module 402 needs to be added after the control module 401, the signal processing module 402 receives the BG signal sent by the decoding module 404 and generates a target signal with BG information together with the target control signal sent by the control module 401, and the target signal enters a different BG module 403 to work.

Further, in some embodiments, for the initial command signal and the target control signal, the initial command signal may include at least one of: a write command signal and a read command signal;

the target control signal may include at least one of: column address decode control signals, local data line LIO precharge control signals, local data line LIO write enable signals, and local data line LIO read enable signals.

It should be noted that, in the embodiment of the present disclosure, the initial command signal mainly includes a write command signal or a read command signal, etc.; the control module 401 delays the write command signal or the read command signal to generate a corresponding target control signal.

Here, the target control signal mainly includes, but is not limited to, the following: a column address decode control signal; the local data line LIO precharges the control signal, the local data line LIO write enable signal, and the local data line LIO read enable signal.

It should be further noted that the target control signals shown herein are only exemplary, and other types of read-write related operations and control signals may be included in the actual application, for example: the control write intermediate data line MIO precharge signal, the control read intermediate data line MIO precharge signal, and the like are not limited in any way herein.

It should be further noted that, after the target control signal is combined with the BG signal through the signal processing module 402, the target signal with BG information can be obtained, and after the target signals with different BG information enter the corresponding BG modules, the BG modules can be instructed to execute the corresponding operations. Thus, in some embodiments, the BG module 403 is configured to correspondingly receive the target signal according to the BG information, and perform at least one of the following operations according to the target signal:

It should be noted that, based on the BG information, the BG module 403 can receive a corresponding target signal, and then perform a corresponding operation according to the target signal, for example: control column address decoding operations, control local data line LIO precharge operations, control local data line LIO write enable operations, and control local data line LIO read enable operations.

It should also be noted that the operations that the BG module 403 may perform shown here are merely exemplary, and in practice, the BG module 403 may perform various other operations based on other types of target signals, such as: the control write intermediate data line MIO precharge, the control read intermediate data line MIO precharge, and the like are not limited in any way herein.

In some embodiments, for a specific arrangement of the control module and the signal processing modules, as shown in fig. 5, the control module 401 and the plurality of signal processing modules 402 are located at a central position of the storage structure 40, and the plurality of signal processing modules 402 are distributed around the control module 401 and have a symmetrical structure.

That is, in the storage structure 40, the control module 401 and the plurality of signal processing modules 402 are located at a central position, and the control module 401 is located at a central position, and the plurality of signal processing modules 402 are symmetrically distributed around the control module 401. In this way, when the control module 401 transmits the target control signal to the different signal processing modules 402, the required wiring and transmission path are consistent, and the timing of the signal transmission can be ensured to be uniform.

Further, in some embodiments, for the specific arrangement of BG modules, as shown in fig. 5, a plurality of BG modules 403 are in one-to-one correspondence with a plurality of signal processing modules 402; the plurality of BG modules 403 are located at peripheral positions of the storage structure 40, and the plurality of BG modules 403 are in a vertically and laterally symmetrical structure.

That is, the BG modules 403 and the signal processing modules 402 are in one-to-one correspondence, in the storage structure 40, the plurality of BG modules 403 are distributed at peripheral positions of the storage structure 40, and the plurality of BG modules 403 are also distributed in a vertically and laterally symmetrical structure as in the signal processing modules 402.

It should be further noted that, in fig. 5, each set of signal processing modules 402 and the corresponding BG module 403 are connected by a connection line 405. Accordingly, there are a plurality of connection lines in the memory structure 40, and the plurality of connection lines 405 are also distributed in a vertically and laterally symmetrical structure.

Specifically, if a set of corresponding signal processing modules 402 and BG modules 403, and connection lines 405 connecting the two are taken as a set of integers, then the sets of integers are all symmetrically distributed around the control module 401.

Thus, according to the memory structure 40 shown in fig. 4 or 5, the time taken for each transmission of the target signal from the reception of the initial command signal to the transmission of the target signal to the BG module can be kept the same, thereby avoiding deviation of the target signals corresponding to different BG modules during transmission.

The embodiment of the disclosure provides a storage structure, which comprises a control module, a plurality of signal processing modules and a plurality of BG modules correspondingly connected with the plurality of signal processing modules; the control module is used for receiving the initial command signal and carrying out delay processing on the initial command signal to obtain a target control signal; the signal processing module is used for receiving the BG signal and the target control signal, and carrying out signal combination processing on the BG signal and the target control signal to obtain a target signal with BG information; the BG signal carries BG information, and the BG information is used for determining a BG module which is correspondingly transmitted by the target signal. Therefore, the initial command signal entering the control module does not distinguish the BG information, so that the delay processing of the initial command signal can be realized by only one control module, a target control signal is obtained, and the target control signal and the BG signal carrying the BG information are combined into the target signal through the signal processing module and then sent to the corresponding BG module for working; therefore, the deviation of signals in the transmission process can be eliminated, so that the signal transmission time sequence is uniform, the circuit area can be reduced, and the static power consumption can be saved.

In another embodiment of the present disclosure, reference is made to fig. 6, which illustrates a schematic composition of yet another memory structure 40 provided by an embodiment of the present disclosure. As shown in fig. 6, the plurality of BG modules may include a first BG module 4031, a second BG module 4032, a third BG module 4033, and a fourth BG module 4034, and the plurality of signal processing modules may include a first signal processing module 4021, a second signal processing module 4022, a third signal processing module 4023, and a fourth signal processing module 4024; wherein,

the first BG module 4031 is located at an upper left position of the first signal processing module 4021, the second BG module 4032 is located at an upper right position of the second signal processing module 4022, the third BG module 4033 is located at a lower left position of the third signal processing module 4023, and the fourth BG module 4034 is located at a lower right position of the fourth signal processing module 4024.

It should be noted that, for the plurality of BG modules, the plurality of BG modules may specifically include a first BG module (BG 0 for short), a second BG module (BG 1 for short), a third BG module (BG 2 for short), and a fourth BG module (BG 3 for short); for the plurality of signal processing modules, it may specifically include a first signal processing module 4021 (abbreviated as BG0 DEC MUX), a second signal processing module 4022 (abbreviated as BG1DEC MUX), a third signal processing module 4023 (abbreviated as BG2 DEC MUX), and a fourth signal processing module 4024 (abbreviated as BG3 DEC MUX).

In fig. 6, the first BG module 4031 is located in an upper left position of the first signal processing module 4021, and both are located in an upper left position of the control module 401; the second BG module 4032 is located in the upper right position of the second signal processing module 4022, and both are located in the upper right position of the control module 401; the third BG module 4033 is located in the lower left position of the third signal processing module 4023, and both are located in the lower left position of the control module 401; the fourth BG module 4034 is located in the lower right position of the fourth signal processing module 4024 and both are located in the lower right position of the control module 401.

In this way, the four BG modules and the four signal processing modules are all distributed symmetrically up and down and left and right, so that paths of input signals are consistent and the time spent is consistent in the process of generating target signals to enter different BG modules through some columns of processing.

Further, in some embodiments, as shown in fig. 6, the storage structure 40 may further include a first connection line 4051, a second connection line 4052, a third connection line 4053, and a fourth connection line 4054; wherein,

a first connection line 4051 for connecting the first signal processing module 4021 and the first BG module 4031;

a second connection line 4052 for connecting the second signal processing module 4022 and the second BG module 4032;

A third connection line 4053 for connecting the third signal processing module 4023 and the third BG module 4033;

a fourth connection line 4054 for connecting the fourth signal processing module 4024 and the fourth BG module 4034.

It should be noted that, corresponding to the four groups of BG modules and the signal processing modules, the storage structure 40 further includes four connection lines correspondingly connecting the four groups of BG modules and the signal processing modules, and each connection line is used for connecting the corresponding signal processing module and the BG module.

The first connecting line 4051, the second connecting line 4052, the third connecting line 4053, and the fourth connecting line 4054 are vertically and laterally symmetrical with respect to the four connecting lines.

Thus, in the disclosed embodiment, four connection lines connecting the BG module and the signal processing module are also symmetrically distributed on the storage structure 40. In this way, the time used in the process of transmitting the target signal from the signal processing module to the corresponding BG module is the same, and the uniformity of the time sequence among the signals is maintained.

It should also be noted that, in one possible implementation, referring to fig. 7, a schematic diagram of the composition of still another storage structure 40 provided by an embodiment of the disclosure is shown. As shown in fig. 7, the at least one BG signal may include a first BG signal and a second BG signal. Specifically, the first BG signal carries BG information indicating the first BG module 4031, the second BG signal carries BG information indicating the second BG module 4032, the first BG module 4031 is connected to the first signal processing module 4021, and the second BG module 4032 is connected to the second signal processing module 4022; wherein,

The first signal processing module 4021 is configured to receive the first BG signal and the target control signal, perform signal combination processing on the first BG signal and the target control signal, obtain a first target signal, and send the first target signal to the first BG module 4031 correspondingly;

the second signal processing module 4022 is configured to receive the second BG signal and the target control signal, perform signal combination processing on the second BG signal and the target control signal, obtain a second target signal, and send the second target signal to the second BG module 4032 correspondingly.

It should be noted that, as shown in fig. 7, when the number of BG modules is two, the two BG modules (the first BG module 4031 and the second BG module 4032) may be distributed in a vertically symmetrical structure at the upper and lower positions of the storage structure; at this time, two signal processing modules (the first signal processing module 4021 and the second signal processing module 4022) are correspondingly provided, and the two signal processing modules may be distributed in the upper and lower positions of the control module 401 in an up-down symmetrical structure.

Here, the operations of the signal processing module and the BG module are exemplarily described with the first signal processing module 4021 and the first BG module 4031. Specifically, the first signal processing module 4021 and the first BG module 4031 may be connected by a first connection line 4051, and the first signal processing module 4021 receives the first BG signal and the target control signal; the first BG module can be indicated by BG information carried by the first BG signal. The first signal processing module 4021 performs a combination process on the first BG signal and the target control signal to obtain a first target signal, and sends the first target signal to a corresponding first BG module, where the first BG module performs an operation according to an instruction of the first target signal.

It should be further noted that, in another possible implementation manner, as shown in fig. 6, on the basis of the storage structure 40 shown in fig. 7, the number of BG modules in the embodiment of the disclosure may also be four; i.e. the at least one BG signal may also comprise a third BG signal and a fourth BG signal. Specifically, the third BG signal carries BG information indicating the third BG module 4033, the fourth BG signal carries BG information indicating the fourth BG module, and the third BG module 4033 is connected to the third signal processing module 4023, and the fourth BG module 4034 is connected to the fourth signal processing module 4024; wherein,

the third signal processing module 4023 is configured to receive the third BG signal and the target control signal, perform signal combination processing on the third BG signal and the target control signal, obtain a third target signal, and send the third target signal to the third BG module 4033 correspondingly;

the fourth signal processing module 4024 is configured to receive the fourth BG signal and the target control signal, perform signal combination processing on the fourth BG signal and the target control signal, obtain a fourth target signal, and send the fourth target signal to the fourth BG module 4034 correspondingly.

It should be noted that, as shown in fig. 6, when the number of BG modules is four, the four BG modules may be distributed in an up-down position and a left-right position of the storage structure in an up-down and left-right symmetrical structure; at this time, the four signal processing modules are also correspondingly arranged, and the four signal processing modules can be distributed in the upper and lower positions and the left and right positions of the control module 401 in an up-down and left-right symmetrical structure.

It will be appreciated that although in fig. 7 the first and second BG modules are arranged symmetrically up and down, in fig. 6 the first and second BG modules are arranged adjacent to each other; however, the first and second modules are not specifically limited to the respective modules, and the symmetrical distribution structure between the BG modules and the respective signal processing modules is only described here, so long as the corresponding signal processing modules and BG modules are positioned in the same orientation, the symmetrical distribution structure can be maintained, and the timing between the signal transmission can be unified.

The four groups of signal processing modules and BG modules shown in fig. 6 are symmetrical up and down and side to side, and the operation is similar, and reference is specifically made to the foregoing description for the first signal processing module 4021 and the first BG module 4031.

That is, the four BG modules are in a structure of four-corner symmetrical distribution, so that the time sequence of the first target signal, the second target signal, the third target signal and the fourth target signal in the process from generation to transmission is unified.

Further, in some embodiments, for the signal processing module, the signal processing module may be composed of a plurality of nand gates and not gates.

It should be noted that, in the embodiment of the disclosure, the input signal is decoded by the decoding module into the BG signal and the initial command signal, where the initial command signal does not distinguish the BG information first and enters the control module, and the BG signal with the BG information enters the different signal processing modules; after the control module processes the initial command signal into a target control signal, the target control signal enters the signal processing module again, and the target control signal and the BG signal are combined through the signal processing module to generate a target signal with BG information; thus, the deviation between different signals can be eliminated.

It should be noted that, since the signal processing module is focused on providing BG information to the target signal, not too much logic operation is usually performed by a NAND gate (NAND) and a NAND gate (INV), so as to combine the target control signal and the BG information. Therefore, compared with the traditional central control module, the signal processing module has the advantages that the size is much smaller, the total number of transistors in a circuit is smaller, the total area of a circuit layout can be reduced, and the static power consumption is also small.

Illustratively, referring to FIG. 8, a partially enlarged schematic illustration of one memory structure provided by an embodiment of the present disclosure is shown. As shown in fig. 8, among the signals decoded by the decoding module 404, an initial control signal is transmitted to the control module 401, a first BG signal is transmitted to the first signal processing module, a second BG signal is transmitted to the second signal processing module, a third BG signal is transmitted to the third signal processing module, and a fourth BG signal is transmitted to the fourth signal processing module. The control module 401 processes the initial command signal into a target control signal and sends it to a different signal processing module.

For the control module 401, in some embodiments, the control module 401 may include several delay sub-modules, wherein,

The control module 401 is specifically configured to perform delay processing on the initial command signal through a plurality of delay sub-modules, so as to obtain a target control signal.

It should be noted that, the control module 401 may include a plurality of delay sub-modules, and the plurality of delay sub-modules process the initial command signal, so as to obtain a plurality of target control signals, and further transmit the target control signals to the signal processing module.

Illustratively, referring to FIG. 9, a specific structural schematic diagram of a control module 401 provided by an embodiment of the present disclosure is shown. As shown in fig. 9, the control module 401 includes a plurality of Delay units (Delay cells, i.e., delay sub-modules), and processes the initial command signal through the plurality of Delay units to obtain a target control signal, such as a column address decoding control signal, a local data line LIO precharge control signal, or a local data line LIO read enable signal.

The number of nand gates is not unique in each signal processing module, and each nand gate performs a nand operation on the target control signal and the BG signal. In other words, how many target control signals correspond to how many nand gates. Illustratively, one NAND gate (which may be referred to as NAND ₁ ) The first BG signal and the column address decoding control signal can be subjected to NAND operation to obtain a target signal; another is connected withNOT gate (can be described as NAND) ₂ ) The first BG signal and the local data line LIO precharge control signal may be nand-calculated to obtain a target signal, and so on. It can be seen that, for the signal processing module, the type of the target control signal corresponds to the number of nand gates, and each nand gate is responsible for performing a nand operation on one target control signal and the BG signal to obtain the target signal.

In the embodiment of the disclosure, since the signal processing module may be composed of only a plurality of nand gates and not gates, the area of the signal processing module is smaller and the static power consumption is also smaller compared with the central control module in fig. 3.

Referring to fig. 10, which illustrates a specific structural schematic diagram of a signal processing module 402 provided by an embodiment of the present disclosure, as shown in fig. 10, the signal processing module 402 may include a nand gate and a not gate, receive a # BG signal (where "#" is any one of one, two, three, and four values) and a target control signal through two input ends of the nand gate, generate an output signal, and further process the signal output by the nand gate to obtain the target signal. The target control signal does not carry the BG information, but the BG signal carries the BG information, so that the combined target signal has the BG information.

In practical application, part of target signals need to be effective in high level, and part of target signals need to be effective in low level, and high-low level conversion can be performed through a plurality of NOT gates, and high-low level configuration is performed according to practical requirements.

It can be seen that the signal processing module provided by the embodiments of the present disclosure has a smaller area. Briefly, embodiments of the present disclosure provide a circuit architecture design of a control module in a novel memory structure, which can improve the quality of the control module of a chip, reduce the area of the control module, and reduce the deviation between different signal generation and transmission. The scheme provided by the embodiment of the disclosure can be applied to and is not limited to the layout design of the memory structure in the dynamic random access memory (Dynamic Random Access Memory, DRAM).

The embodiment of the present disclosure provides a memory structure, and by describing the foregoing embodiments in detail, it can be seen that, in order to solve the deviation of BG read/write command signals from a decoding module to different central control modules caused by a winding layout in the conventional memory structure (taking fig. 3 as an example), four central control modules are considered to be combined into one control module, and only four signal processing modules are connected to an output portion of the control module, so as to add BG information to a target control signal obtained by the control module. Thus, according to the technical scheme of the embodiment of the disclosure, when the read/write logic control parts of the 4 central control modules are combined into one control module, the parts needing to be distinguished for work of which BG are separately distinguished and symmetrically distributed in the surrounding area of the control module to form four signal processing modules, so that not only can the consistency of time sequences among signals be realized, but also the area of wiring can be reduced, and the static power consumption of a circuit can be reduced after the four central control modules are combined.

In yet another embodiment of the present disclosure, referring to fig. 11, a schematic structural diagram of a semiconductor memory 100 provided by an embodiment of the present disclosure is shown. As shown in fig. 11, the semiconductor memory may include a memory structure 40 as described in any of the previous embodiments.

In some embodiments, semiconductor memory 100 is a DRAM chip.

In the embodiment of the disclosure, for the semiconductor memory 100, since the initial command signal entering the control module does not distinguish BG information, delay processing of the initial command signal can be implemented by only one control module, so as to obtain a target control signal, and the target control signal and the BG signal carrying BG information are combined into the target signal by the signal processing module and then sent to the corresponding BG module for working; therefore, the deviation of signals in the transmission process can be eliminated, so that the signal transmission time sequence is uniform, the circuit area can be reduced, and the static power consumption can be saved.

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure.

It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. The storage structure is characterized by comprising a control module, a plurality of signal processing modules and a plurality of BG modules correspondingly connected with the plurality of signal processing modules; wherein,

2. The memory structure of claim 1, wherein the control module and the plurality of signal processing modules are located at a central location of the memory structure, and the plurality of signal processing modules are distributed around the control module and are in a vertically and laterally symmetric structure.

3. The memory structure of claim 2, wherein the plurality of BG modules are in one-to-one correspondence with the plurality of signal processing modules; the plurality of BG modules are located at peripheral positions of the storage structure, and are in a vertically and laterally symmetrical structure.

4. The storage structure of claim 3, wherein the plurality of BG modules includes a first BG module, a second BG module, a third BG module, and a fourth BG module, and the plurality of signal processing modules includes a first signal processing module, a second signal processing module, a third signal processing module, and a fourth signal processing module; wherein,

5. The memory structure of claim 4, further comprising a first connection line, a second connection line, a third connection line, and a fourth connection line; wherein,

6. The memory structure according to claim 5, wherein the first connection line, the second connection line, the third connection line, and the fourth connection line are in a vertically and laterally symmetrical structure.

7. The storage structure of claim 1 wherein said control module comprises a plurality of delay sub-modules, wherein,

8. The storage structure of claim 7, wherein,

the initial command signal includes at least one of: a write command signal and a read command signal;

9. The storage structure of claim 1 wherein,

the BG module is configured to correspondingly receive the target signal according to the BG information, and perform at least one of the following operations according to the target signal:

10. The memory architecture of claim 1, wherein the signal processing module is comprised of a plurality of nand gates and nor gates.

11. The memory structure according to any one of claims 1 to 10, further comprising a decoding module; wherein,

12. The storage structure of claim 11, wherein the at least one BG signal comprises a first BG signal and a second BG signal, the first BG signal carrying BG information indicative of a first BG module, the second BG signal carrying BG information indicative of a second BG module, and the first BG module being coupled to a first signal processing module and the second BG module being coupled to a second signal processing module; wherein,

13. The storage structure of claim 12 wherein the at least one BG signal further comprises a third BG signal and a fourth BG signal, the third BG signal carrying BG information indicating a third BG module and the fourth BG signal carrying BG information indicating a fourth BG module, the third BG module coupled to a third signal processing module and the fourth BG module coupled to a fourth signal processing module; wherein,

14. A semiconductor memory comprising a memory structure as claimed in any one of claims 1 to 13.

15. The semiconductor memory of claim 14, wherein the semiconductor memory is a dynamic random access memory, DRAM, chip.