CN114420068A

CN114420068A - Display panel and display device

Info

Publication number: CN114420068A
Application number: CN202210112215.7A
Authority: CN
Inventors: 徐姗姗; 陈吉湘; 林剑涛; 朱敬光; 王文超; 刘耀; 徐旭
Original assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Priority date: 2022-01-29
Filing date: 2022-01-29
Publication date: 2022-04-29
Anticipated expiration: 2042-01-29
Also published as: CN114420068B

Abstract

The application provides a display panel and a display device, which relate to the technical field of display, wherein the display panel comprises a plurality of scanning lines and a plurality of data lines, and the scanning lines and the data lines are intersected and insulated; a plurality of sub-pixels arranged in an array; the data lines comprise a first data line and a second data line, in the same row of sub-pixels arranged along the first direction, the 4n +1 th sub-pixel and the 4n +2 th sub-pixel are electrically connected with the first data line, and the 4n +3 th sub-pixel and the 4n +4 th sub-pixel are electrically connected with the second data line; wherein n is equal to zero or a positive integer; the same row of sub-pixels arranged along the second direction are electrically connected with the same scanning line; the first direction is the extending direction of the data lines, and the second direction is the extending direction of the scan lines. The display panel is high in charging rate and good in display effect.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

With the rapid development of display technology, people have higher and higher requirements on the performance of display products. For high-definition display products such as high refresh rate and high resolution, the charging time is shorter and shorter, and it is more and more difficult to satisfy the pixel charging rate standard, and how to improve the charging rate becomes an important issue for the competitiveness of the display products.

At present, a new display panel is needed to solve the above problems.

Disclosure of Invention

The embodiment of the application provides a display panel and a display device, and the display panel is high in charging rate and good in display effect.

The embodiment of the application adopts the following technical scheme:

in a first aspect, an embodiment of the present application provides a display panel, including:

the scanning lines and the data lines are intersected and insulated;

a plurality of sub-pixels arranged in an array;

wherein the data line includes a first data line and a second data line, and in the same row of the sub-pixels arranged along the first direction, the 4n +1 th and 4n +2 th sub-pixels are electrically connected to the first data line, and the 4n +3 th and 4n +4 th sub-pixels are electrically connected to the second data line; wherein n is equal to zero or a positive integer;

the same row of sub-pixels arranged along the second direction are electrically connected with the same scanning line; the first direction is an extending direction of the data line, and the second direction is an extending direction of the scan line.

In some embodiments of the present application, the sub-pixels in the same row arranged along the first direction have the same pixel color.

In some embodiments of the present application, the sub-pixel is located within an area defined by the data line and the scan line, the sub-pixel includes an open area, the open area includes:

a substrate;

a first conductive layer on the substrate;

the patterned second conducting layer is positioned on one side, far away from the substrate, of the first conducting layer and is arranged in an insulating mode with the first conducting layer;

wherein a minimum distance between an orthographic projection of the data line on the substrate to an orthographic projection of the first conductive layer on the substrate is smaller than a minimum distance between an orthographic projection of the data line on the substrate to an orthographic projection of the second conductive layer on the substrate.

In some embodiments of the present application, a minimum distance between an orthographic projection of the data line on the substrate to an orthographic projection of the first conductive layer on the substrate is greater than or equal to a first preset value.

In some embodiments of the present application, the first preset value is greater than or equal to 5.0 μm.

In some embodiments of the present application, an outline of an orthogonal projection of the patterned second conductive layer on the substrate is located within an outline of an orthogonal projection of the first conductive layer on the substrate, and a distance between the outline of the orthogonal projection of the second conductive layer on the substrate and the outline of the orthogonal projection of the first conductive layer on the substrate is greater than or equal to a second preset value.

In some embodiments of the present application, the second preset value is greater than or equal to 4.5 μm.

In some embodiments of the present application, in the same row of the sub-pixels arranged along the first direction, the scan line to which the 4n +1 th sub-pixel is electrically connected and the scan line to which the 4n +2 th sub-pixel is electrically connected are configured to be capable of being turned on simultaneously.

In some embodiments of the present application, the sub-pixel further comprises a non-open area, the open area and the non-open area being connected;

the non-opening area comprises the substrate and at least one switch transistor positioned on the substrate, and the grid electrode of each switch transistor in the same row of sub-pixels arranged along the second direction is electrically connected with the same scanning line;

in the same row of the sub-pixels arranged along the first direction, the first electrodes of the switching transistors in the 4n +1 th and 4n +2 th sub-pixels are electrically connected to the first data line, and the first electrodes of the switching transistors in the 4n +3 th and 4n +4 th sub-pixels are electrically connected to the second data line.

In some embodiments of the present application, the display panel further includes a plurality of GOA units and a clock signal inputs, the clock signal inputs are electrically connected to the GOA units, and outputs of the GOA units are electrically connected to the scan lines;

wherein, the output signal of the nth GOA unit is taken as the enable signal of the (N + a)/2) th GOA unit, the output signal of the (N + 1) th GOA unit is taken as the enable signal of the (N +1+ a)/2) th GOA unit, the output signal of the (N + 2) th GOA unit is taken as the enable signal of the (N +2+ a)/2 th GOA unit, and the output signal of the (N + 3) th GOA unit is taken as the enable signal of the (N +3+ a)/2 th GOA unit;

an output signal of an N +2+ a/2 th GOA unit is used as a reset signal of an Nth GOA unit, an output signal of an N +3+ a/2 th GOA unit is used as a reset signal of an N +1 th GOA unit, an output signal of an N +4+ a/2 th GOA unit is used as a reset signal of an N +2 th GOA unit, and an output signal of an N +5+ a/2 th GOA unit is used as a reset signal of an N +3 th GOA unit, wherein N is a positive integer; a is 8, 12 or 16.

In some embodiments of the present application, in the same row of the sub-pixels arranged along the first direction, the timing of the output signal of the GOA unit received by the scan line electrically connected to the 4n +1 th sub-pixel and the timing of the output signal of the GOA unit received by the scan line electrically connected to the 4n +2 th sub-pixel are the same, and the timing of the output signal of the GOA unit received by the scan line electrically connected to the 4n +3 th sub-pixel and the timing of the output signal of the GOA unit received by the scan line electrically connected to the 4n +4 th sub-pixel are the same.

In some embodiments of the present application, the GOA unit includes a pull-up sub-unit configured to pull up an output signal of the GOA unit;

in the same row of the sub-pixels arranged along the first direction, the timing sequence of the control signal in the pull-up sub-unit electrically connected to the 4n +1 th sub-pixel is the same as the timing sequence of the control signal in the pull-up sub-unit electrically connected to the 4n +2 th sub-pixel, and the timing sequence of the control signal in the pull-up sub-unit electrically connected to the 4n +3 th sub-pixel is the same as the timing sequence of the control signal in the pull-up sub-unit electrically connected to the 4n +4 th sub-pixel.

In a second aspect, embodiments of the present application provide a display device including the display panel as described above.

The embodiment of the application provides a display panel and a display device, wherein the display panel comprises a plurality of scanning lines and a plurality of data lines, and the scanning lines and the data lines are intersected and insulated; a plurality of sub-pixels arranged in an array; the data lines comprise a first data line and a second data line, in the same row of sub-pixels arranged along the first direction, the 4n +1 th sub-pixel and the 4n +2 th sub-pixel are electrically connected with the first data line, and the 4n +3 th sub-pixel and the 4n +4 th sub-pixel are electrically connected with the second data line; wherein n is equal to zero or a positive integer; the same row of sub-pixels arranged along the second direction are electrically connected with the same scanning line; the first direction is the extending direction of the data lines, and the second direction is the extending direction of the scan lines.

Thus, based on such a double Z-inverted display panel, when the scan lines input the scan signals line by line, the data signals input by the data lines can be written into the sub-pixels line by line; when the two scanning lines input scanning signals simultaneously, the data signals can be written into the two rows of sub-pixels simultaneously through the data lines, and the data signals written into the two rows of sub-pixels are the same, so that the charging time of the two rows of sub-pixels through the data lines is doubled, the charging rate of the display panel is improved, the two rows of sub-pixels are prevented from color mixing, and the display effect of the display panel is improved.

The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1-6 are schematic structural diagrams of six display panels provided in the embodiments of the present application;

FIGS. 7-8 are timing diagrams of two scan signals according to embodiments of the present disclosure;

fig. 9 (1) and (2) are schematic diagrams illustrating comparison of display effects of a related art display panel and a display panel of the present application in a case where two rows are simultaneously turned on, according to an embodiment of the present application;

fig. 10 and fig. 12 are schematic diagrams illustrating a cascade relationship of two kinds of GOA units according to an embodiment of the present application;

fig. 11 and fig. 13 are timing signal diagrams of two GOA units according to an embodiment of the present disclosure;

fig. 14 is a schematic circuit structure diagram of a GOA unit according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals denote the same or similar structures in the drawings, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale.

Throughout the specification and claims, the term "comprising" is to be interpreted in an open, inclusive sense, i.e., as "including, but not limited to," unless the context requires otherwise. In the description herein, the terms "one embodiment," "some embodiments," "example," "certain examples," or "some examples" or the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the embodiments of the present application, the terms "first", "second", and the like are used for describing the same or similar items with basically the same functions and actions, only for the purpose of clearly describing technical solutions of the embodiments of the present application, and are not to be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features.

With the rapid development of display technologies, people have higher and higher requirements for the image quality of display products. The charging rate is one of the most important indexes in display product design, and insufficient charging rate causes a series of problems that the display does not reach the standard, such as low transmittance, low contrast, and the like.

At present, for high-performance display products such as high refresh frequency, high resolution and ultra-large size, the difficulty of improving the charging rate is more obvious on the premise of ensuring the high performance of the display products.

An embodiment of the present application provides a display panel, as shown in fig. 1, including:

the scanning lines Gate and the Data lines Data are crossed and insulated;

a plurality of subpixels P arranged in an array;

wherein the Data line Data includes a first Data line D1 and a second Data line D2, and among the same row of subpixels P arranged along the first direction OA, the 4n +1 th and 4n +2 th subpixels P are electrically connected to the first Data line D1, and the 4n +3 th and 4n +4 th subpixels P are electrically connected to the second Data line D2; wherein n is equal to zero or a positive integer;

the same row of sub-pixels P arranged along the second direction OB are electrically connected with the same scanning line Gate; the first direction is the extending direction of the Data lines Data, and the second direction is the extending direction of the scan lines Gate.

In an exemplary embodiment, when n is 0, the 1 st and 2 nd sub-pixels P are electrically connected to the first data line D1 and the 3 rd and 4 th sub-pixels P are electrically connected to the second data line D2 in the same row of sub-pixels P arranged along the first direction OA.

In an exemplary embodiment, when n is 1, in the same row of subpixels P arranged along the first direction OA, the 5 th and 6 th subpixels P are electrically connected to the first data line D1, and the 7 th and 8 th subpixels P are electrically connected to the second data line D2.

When n is other positive integers, the connection mode between each sub-pixel and the data line is similar to that when n is 0 and n is 1, and the description is omitted here.

In practical applications, the specific value of n is related to the number of rows of the designed sub-pixels in the display panel, and may be specifically determined according to practical situations, which is not limited herein.

The specific number of the scan lines Gate and the Data lines Data is not limited, and may be determined according to actual conditions.

Here, the material of the scanning line Gate and the material of the Data line Data are not limited.

Illustratively, the material of the scan line Gate may be at least one of copper (Cu), molybdenum (Mo), and aluminum (Al).

Illustratively, the material of the Data line Data may be at least one of copper (Cu), molybdenum (Mo), and aluminum (Al).

The specific structure of the sub-pixel P is not limited herein, and may be determined according to the design of different display products.

In an exemplary embodiment, each of the subpixels P includes at least one of a red subpixel, a green subpixel, and a blue subpixel.

Illustratively, each of the subpixels P includes a red subpixel P1, a green subpixel P2, and a blue subpixel P3 as shown in fig. 2.

In an exemplary embodiment, the display panel may be adapted to a progressive scanning driving method; alternatively, the display panel may be applied to a driving method of two-line simultaneous scanning.

In an exemplary embodiment, when the scan signal of the scan line Gate is turned on row by row, the Data signal of the Data line Data can be written into the pixel electrode of the sub-pixel, defining the charging time at this time as T; when the scanning signals of the two scanning lines Gate are turned on simultaneously, the Data signals of the Data lines Data can be written into the pixel electrodes of the sub-pixels in the two rows simultaneously, and it can be understood that, at this time, the charging time of the sub-pixels in the two rows is 2T, and the charging time is doubled.

In an exemplary embodiment, when the scan signals of the two scan lines Gate are simultaneously turned on, the sub-pixels of the 4n +1 th row and the 4n +2 th row are simultaneously turned on, and the sub-pixels of the 4n +3 th row and the 4n +4 th row are simultaneously turned on. This drive scheme may be referred to as double Z-Inversion (Dual Z-Inversion).

The embodiment of the application provides a display panel, which comprises a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are intersected and insulated; a plurality of sub-pixels arranged in an array; the data lines comprise a first data line and a second data line, in the same row of sub-pixels arranged along the first direction, the 4n +1 th sub-pixel and the 4n +2 th sub-pixel are electrically connected with the first data line, and the 4n +3 th sub-pixel and the 4n +4 th sub-pixel are electrically connected with the second data line; wherein n is equal to zero or a positive integer; the same row of sub-pixels arranged along the second direction are electrically connected with the same scanning line; the first direction is the extending direction of the data lines, and the second direction is the extending direction of the scan lines.

Thus, based on such a double Z-Inversion (Dual Z-Inversion) display panel, when a scan signal is input to a scan line row by row, a data signal input to a data line can be written to a sub-pixel row by row; when the two scanning lines input scanning signals simultaneously, the data signals can be written into the two rows of sub-pixels simultaneously through the data lines, and the data signals written into the two rows of sub-pixels are the same, so that the charging time of the two rows of sub-pixels through the data lines is doubled, the charging rate of the display panel is improved, the two rows of sub-pixels are prevented from color mixing, and the display effect of the display panel is improved.

In addition, the display panel provided by the embodiment of the application can be suitable for high refresh rate/high PPI products; meanwhile, the driving mode of line-by-line scanning is compatible; the design of the display panel is not changed, and a new Mask is designed without consuming resources (Mask is not changed); the method can also be suitable for low refresh frequency products, and can meet the requirements of different customers.

In some embodiments of the present application, as shown with reference to fig. 2, the pixels of the same row of sub-pixels P arranged along the first direction OA have the same color.

Illustratively, the first row of sub-pixels arranged along the first direction OA is a red sub-pixel P1, the second row of sub-pixels arranged along the first direction OA is a green sub-pixel P2, and the third row of sub-pixels arranged along the first direction OA is a blue sub-pixel P3, i.e., the sub-pixels are arranged in a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B).

For example, the sub-pixels may be arranged in a red sub-pixel (R), a blue sub-pixel (B), and a green sub-pixel (G).

Fig. 5 illustrates a display panel of a Z-Inversion (Z-Inversion) design in the related art, when two rows of sub-pixels are turned on simultaneously, although the charging time of the sub-pixels can be doubled, so as to improve the charging rate of the display panel, as shown in (1) of fig. 9, when two rows of sub-pixels are turned on simultaneously, for example, when a green G picture is displayed, a signal is also written into a red sub-pixel R, so that a color mixing problem occurs in an actual display picture.

In addition, fig. 6 illustrates a display panel with a dual data line design in the related art, two data lines are disposed between two adjacent columns of sub-pixels, wherein one data line is connected to only half of the sub-pixels in the same column; when two rows of sub-pixels are simultaneously started, the display panel can normally display under a pure color picture or a non-pure color picture, the color mixing problem cannot occur, the purposes of doubling the charging time and improving the charging rate can be realized, however, the distance between two data lines between two adjacent rows of sub-pixels is short, and the problem of signal crosstalk is very easy to occur, therefore, the distance between the two data lines is set to be more than 12 mu m, so that the aperture opening rate of the display panel is reduced, the transmittance of the display panel is greatly reduced, and the display effect is poor.

However, in the embodiment of the present application, by setting the same pixel color of the same row of the subpixels P arranged along the first direction OA to be the same, in the same row of the subpixels arranged along the first direction OA, the 4n +1 th and 4n +2 th subpixels are electrically connected to the first data line, and the 4n +3 th and 4n +4 th subpixels are electrically connected to the second data line; thus, when two rows of sub-pixels are simultaneously turned on in the display panel (the 4n +1 th row and the 4n +2 th row), and the second data line inputs a data signal, as shown in (2) of fig. 9, the 4n +1 th and 4n +2 th sub-pixels are turned on to be green, it can be understood that, in the display panel of the double Z-Inversion (Dual Z-Inversion) design, when two rows of sub-pixels are simultaneously turned on, on one hand, the charging time of the sub-pixels is doubled, and the charging rate is improved; on the other hand, the problem of color cross does not occur when two rows of sub-pixels are simultaneously started to display the picture.

In some embodiments of the present application, the sub-pixel P is located within an area defined by the Data line Data and the scan line Gate, and the sub-pixel includes an opening area, as shown with reference to fig. 3 or 4, the opening area including:

a substrate 100;

a first conductive layer 101 on the substrate 100;

the patterned second conductive layer 104 is positioned on one side of the first conductive layer 101, which is far away from the substrate 100, and is insulated from the first conductive layer 101;

wherein, the minimum distance between the orthographic projection of the Data line Data on the substrate 100 to the orthographic projection of the first conductive layer 101 on the substrate 100 is smaller than the minimum distance between the orthographic projection of the Data line Data on the substrate 100 to the orthographic projection of the second conductive layer 104 on the substrate 100.

The minimum distance between the orthographic projection of the Data line Data on the substrate 100 to the orthographic projection of the first conductive layer 101 on the substrate 100 means: the distance between the orthographic projection edge of the Data line Data on the substrate 100 to the nearest orthographic projection edge of the first conductive layer 101 on the substrate 100.

The minimum distance between the orthographic projection of the Data line Data on the substrate 100 to the orthographic projection of the second conductive layer 104 on the substrate 100 refers to the distance between the orthographic projection edge of the Data line Data on the substrate 100 and the nearest orthographic projection edge of the second conductive layer 104 on the substrate 100.

In an exemplary embodiment, the material of each of the first conductive layer 101 and the second conductive layer 104 may be a light-transmitting conductive material.

Illustratively, the materials of the first conductive layer 101 and the second conductive layer 104 are the same, and are both Indium Tin Oxide (ITO).

The specific pattern of the patterned second conductive layer 104 is not limited herein and can be determined according to practical situations.

Wherein a first insulating layer 102 and a second insulating layer 103 are arranged between the first conductive layer 101 and the second conductive layer 104.

The materials of the first conductive layer 101 and the second conductive layer 104 may be each at least one or a combination of silicon oxide, silicon nitride, and silicon oxynitride.

In some embodiments of the present application, as illustrated with reference to fig. 3, a minimum distance between an orthographic projection of the Data line Data on the substrate 100 to an orthographic projection of the first conductive layer 101 on the substrate 100 is greater than or equal to a first preset value.

Illustratively, the first preset value may be 5.0 μm, or the first preset value may be 5.5 μm.

It is understood that the minimum distance between the orthographic projection of the Data line Data on the substrate 100 to the orthographic projection of the first conductive layer 101 on the substrate 100 is greater than or equal to 5.0 μm.

In some embodiments of the present application, referring to fig. 3, an outline of an orthogonal projection of the patterned second conductive layer 104 on the substrate 100 is located within an outline of an orthogonal projection of the first conductive layer 101 on the substrate 100, and a distance between the outline of the orthogonal projection of the second conductive layer 104 on the substrate 100 and the outline of the orthogonal projection of the first conductive layer 101 on the substrate 100 is greater than or equal to a second preset value.

It is understood that the distance between the outer contour of the orthographic projection of the second conductive layer 104 on the substrate 100 and the outer contour of the orthographic projection of the first conductive layer 101 on the substrate 100 is greater than or equal to 4.5 μm.

In an exemplary embodiment, the minimum distance between the orthographic projection of the Data line Data on the substrate 100 to the orthographic projection of the second conductive layer 104 on the substrate 100 is equal to the sum of the minimum distance between the orthographic projection of the Data line Data on the substrate 100 to the orthographic projection of the first conductive layer 101 on the substrate 100 and the distance between the outer contour of the orthographic projection of the second conductive layer 104 on the substrate 100 to the outer contour of the orthographic projection of the first conductive layer 101 on the substrate 100.

In an exemplary embodiment, a minimum distance between an orthographic projection of the Data line Data on the substrate 100 to an orthographic projection of the second conductive layer 104 on the substrate 100 is greater than or equal to a third preset value.

Wherein the third preset value is equal to the sum of the first preset value and the second preset value.

Illustratively, the third preset value may be greater than 9.5 μm.

In the embodiment of the application, by setting that the minimum distance from the orthographic projection of the Data line Data on the substrate 100 to the orthographic projection of the second conductive layer 104 on the substrate 100 is greater than or equal to the third preset value, the phenomenon of horizontal stripes on the display panel can be avoided to a great extent, and the display effect is improved.

In some embodiments of the present application, in the same row of sub-pixels arranged along the first direction, the scan line to which the 4n +1 th sub-pixel is electrically connected and the scan line to which the 4n +2 th sub-pixel is electrically connected are configured to be able to be turned on simultaneously.

In an exemplary embodiment, the display panel shown in fig. 1 can be scanned line by line, and can also be turned on in two lines simultaneously.

Specifically, the display panel shown in fig. 1 may enable the scan line electrically connected to the 4n +1 th sub-pixel and the scan line electrically connected to the 4n +2 th sub-pixel to be simultaneously turned on according to the timing diagram shown in fig. 7. The display panel shown in fig. 1 may have the scan lines scanned line by line according to the timing diagram shown in fig. 8.

In some embodiments of the present application, as illustrated with reference to FIG. 1, the sub-pixel further includes a non-open area, the open area being connected to the non-open area; the non-opening area comprises a substrate 100 and at least one switching transistor FT positioned on the substrate 100, and the grid electrodes of the switching transistors TFT in the same row of sub-pixels arranged along the second direction OB are electrically connected with the same scanning line Gate; in the same row of sub-pixels arranged along the first direction OA, the first electrodes of the switching transistors TFT in the 4n +1 th and 4n +2 th sub-pixels are electrically connected to the first data line D1, and the first electrodes of the switching transistors TFT in the 4n +3 th and 4n +4 th sub-pixels are electrically connected to the second data line D2.

In the sub-pixel, the meaning of the opening area is: a region that is light transmissive; similarly, the non-open area is an area through which light cannot pass. In the display panel, the size of the opening area largely determines the light transmittance of the display panel, and the larger the size of the opening area is, the smaller the size of the non-opening area is, the better the display effect of the display panel is, and the smaller the power consumption is.

Unlike the connection manner of the GOA units in the related art as shown in fig. 12, in some embodiments of the present application, referring to fig. 10, the display panel further includes a plurality of GOA units and a clock signal input terminals, the clock signal input terminals are electrically connected to the GOA units, and the output terminals Gout of the GOA units are electrically connected to the scan lines; to output a scan signal to the scan line.

The output signal of the nth GOA unit is used as the enable signal of the (N + a)/2 th GOA unit, the output signal of the (N + 1) th GOA unit is used as the enable signal of the (N +1+ a)/2 th GOA unit, the output signal of the (N + 2) th GOA unit is used as the enable signal of the (N +2+ a/2) th GOA unit, and the output signal of the (N + 3) th GOA unit is used as the enable signal of the (N +3+ a/2) th GOA unit;

the output signal of the (N +2+ a)/2 th GOA unit is used as the reset signal of the Nth GOA unit, the output signal of the (N +3+ a)/2 th GOA unit is used as the reset signal of the (N + 1) th GOA unit, the output signal of the (N +4+ a/2) th GOA unit is used as the reset signal of the (N + 2) th GOA unit, the output signal of the (N +5+ a/2) th GOA unit is used as the reset signal of the (N + 3) th GOA unit, wherein N is a positive integer; a is 8, 12 or 16.

When a is equal to 8, the output signal of the nth GOA unit (GOA N) is the enable signal of the (N + 4) th GOA unit, the output signal of the (N + 1) th GOA unit is the enable signal of the (N + 5) th GOA unit, the output signal of the (N + 2) th GOA unit is the enable signal of the (N + 6) th GOA unit, and the output signal of the (N + 3) th GOA unit is the enable signal of the (N + 7) th GOA unit;

the output signal of the (N + 6) th GOA unit is used as the reset signal of the nth GOA unit, the output signal of the (N + 7) th GOA unit is used as the reset signal of the (N + 1) th GOA unit, the output signal of the (N + 8) th GOA unit is used as the reset signal of the (N + 2) th GOA unit, and the output signal of the (N + 9) th GOA unit is used as the reset signal of the (N + 3) th GOA unit, where N is a positive integer.

In an exemplary embodiment, when N is 1, the first output terminal (Gout) of the first GOA cell (GOA 1) is electrically connected to the first scan line, and the second output terminal is electrically connected to the fifth GOA cell (GOA 5); the output signal of the second output terminal of the first GOA unit is input into the fifth GOA unit and is used as an enable signal of the fifth GOA unit to control the fifth GOA unit to be turned on. The first output end of the second GOA unit (GOA 2) is electrically connected with the second scanning line, and the second output end of the second GOA unit (GOA 6) is electrically connected with the sixth GOA unit; the output signal of the second output terminal of the second GOA unit (GOA 2) is input into the sixth GOA unit and is used as an enable signal of the sixth GOA unit to control the sixth GOA unit to turn on. The first output end of the third GOA unit is electrically connected with the third scanning line, and the second output end of the third GOA unit is electrically connected with the seventh GOA unit (GOA 7); the output signal of the second output terminal of the third GOA unit is input into the seventh GOA unit and is used as an enable signal of the seventh GOA unit to control the seventh GOA unit to turn on. The first output terminal of the fourth GOA unit is electrically connected to the fourth scan line, and the second output terminal is electrically connected to the eighth GOA unit (GOA 8). The output signal of the second output terminal of the fourth GOA unit is input into the eighth GOA unit and is used as an enable signal of the eighth GOA unit to control the eighth GOA unit to be turned on.

The case of a-12 or 16 is similar to the case of a-8 and will not be described herein.

Note that fig. 10 and 12 provided in the embodiments of the present application are both drawn with a being 8.

In an exemplary embodiment, the number a of the clock signal input terminals may also include other numbers, which may be determined according to actual situations, and only three cases, i.e., 8, 12, and 16, are provided for explanation.

In some embodiments of the present application, in the same row of sub-pixels P arranged along the first direction OA, the timing of the output signal of the GOA unit received by the scan line Gate electrically connected to the 4n +1 th sub-pixel P and the timing of the output signal of the GOA unit received by the scan line Gate electrically connected to the 4n +2 th sub-pixel P are the same, and the timing of the output signal of the GOA unit received by the scan line Gate electrically connected to the 4n +3 th sub-pixel P and the timing of the output signal of the GOA unit received by the scan line Gate electrically connected to the 4n +4 th sub-pixel P are the same.

For example, when N is 1, referring to fig. 11, the timing of the output signal of the first scan line G1 is the same as the timing of the output signal of the second scan line G2, the timing of the output signal of the third scan line G3 is the same as the timing of the output signal of the fourth scan line G4, the timing of the output signal of the fifth scan line G5 is the same as the timing of the output signal of the sixth scan line G6, and the timing of the output signal of the seventh scan line G7 is the same as the timing of the output signal of the eighth scan line G8. Therefore, the first row of sub-pixels and the second row of sub-pixels are controlled to be simultaneously started, the third row of sub-pixels and the fourth row of sub-pixels are controlled to be simultaneously started, the fifth row of sub-pixels and the sixth row of sub-pixels are simultaneously started, and the seventh row of sub-pixels and the eighth row of sub-pixels are simultaneously started, so that the charging rate of the display panel is improved.

In some embodiments of the present application, the GOA unit includes a pull-up subunit configured to pull up an output signal of the GOA unit;

in the related art, when two rows are simultaneously turned on, in the same row of sub-pixels arranged along a first direction, the timing sequence of a control signal PU signal in a pull-up sub-unit electrically connected to a 4n +1 th sub-pixel is different from the timing sequence of a control signal PU signal in a pull-up sub-unit electrically connected to a 4n +2 th sub-pixel, and one of the timing sequences is directly decreased from a first level to a second level, wherein the first level is greater than the second level; the other time sequence is reduced from the first level to a third level and then to the second level, and the third level is larger than the second level and smaller than the first level. Thus, the output signals of the odd-numbered rows and the even-numbered rows are different, and the output of the Gout signal of the odd-numbered rows is abnormal, so that abnormal discharge is caused; the timing of the output signals of the GOA cells in the odd rows goes from high level to low level with the tailing problem indicated by the arrow position in fig. 13, and signal delay occurs, thereby degrading the display effect.

However, in the embodiment of the present application, when two rows are simultaneously turned on, referring to fig. 11, in the same row of sub-pixels arranged along the first direction, the timing sequence of the control signal PU signal in the pull-up sub-unit to which the 4n +1 th sub-pixel is electrically connected is the same as the timing sequence of the control signal PU signal in the pull-up sub-unit to which the 4n +2 th sub-pixel is electrically connected, and the timing sequence of the control signal PU signal in the pull-up sub-unit to which the 4n +3 th sub-pixel is electrically connected is the same as the timing sequence of the control signal PU signal in the pull-up sub-unit to which the 4n +4 th sub-pixel is electrically connected.

It should be noted that, the two rows being simultaneously turned on means that, in the same row of the sub-pixels arranged along the first direction, the scan line electrically connected to the 4n +1 th sub-pixel and the scan line electrically connected to the 4n +2 th sub-pixel can be simultaneously turned on, and the scan line electrically connected to the 4n +3 th sub-pixel and the scan line electrically connected to the 4n +4 th sub-pixel can be simultaneously turned on.

In an exemplary embodiment, when the PU signal returns from the low level to the high level, the PU signal first decreases from the first level to a third level, and then decreases to the second level, the third level is greater than the second level and less than the first level, and the timing of the PU signal in the GOA unit electrically connected to the scan lines in the 4n +1 th row and the 4n +2 th row is the same, and the timing of the PU signal in the GOA unit electrically connected to the scan lines in the 4n +3 th row and the 4n +4 th row is the same.

In an exemplary embodiment, a simple structure of the GOA unit may be as shown in fig. 14, the Gout end is electrically connected to one scan line in the display area, an output signal of the GOA unit may be pulled up by a point location of the PU point, a Reset unit (Reset PU) may assist the PU point to Reset (return to a low level), and a specific circuit of the GOA unit may refer to related technologies, which is not described herein again.

In the embodiment of the present application, as shown in fig. 10 and 11, when two rows are simultaneously turned on, the odd row carries the odd row, the odd row resets the odd row, the even row carries the even row, the even row resets the even row, and the PU signals have the same waveform; no matter the odd-even lines are opened line by line or simultaneously, the GOA can be normally output, the display effect is good, and the problem of picture color mixing can not occur. It should be noted that, the carry indicates that the output signal of the previous-stage GOA unit serves as an enable signal of the subsequent cascaded GOA unit, and controls the start of the subsequent cascaded GOA unit; reset refers to the restoration of the signal to the initial state.

The display panel provided In the embodiment of the present application may be a liquid crystal display panel, and the liquid crystal display panel may be a liquid crystal display screen such as a TN (Twisted Nematic) type, a VA (Vertical Alignment) type, an IPS (In-Plane Switching) type, or an ADS (Advanced Super Dimension Switching) type. The liquid crystal display screen can comprise an array substrate, a color film substrate and liquid crystal positioned between the array substrate and the color film substrate; other structures such as a driver circuit may be included. Only the structures related to the aspects of the invention will be described herein, and other structures included in the display panel may be obtained according to the related art or the common general knowledge, and will not be described herein.

Embodiments of the present application provide a display device including the display panel as described above.

An embodiment of the present application provides a display device, including: the scanning lines and the data lines are intersected and insulated; a plurality of sub-pixels arranged in an array; the data lines comprise a first data line and a second data line, in the same row of sub-pixels arranged along the first direction, the 4n +1 th sub-pixel and the 4n +2 th sub-pixel are electrically connected with the first data line, and the 4n +3 th sub-pixel and the 4n +4 th sub-pixel are electrically connected with the second data line; wherein n is equal to zero or a positive integer; the same row of sub-pixels arranged along the second direction are electrically connected with the same scanning line; the first direction is the extending direction of the data lines, and the second direction is the extending direction of the scan lines. Thus, according to such a display device of double Z-Inversion (Dual Z-Inversion), when a scan signal is input to a scan line row by row, a data signal input to a data line can be written to a sub-pixel row by row; when scanning signals are simultaneously input into the two scanning lines, the data signals can be simultaneously written into the two rows of sub-pixels by the data lines, and the data signals written into the two rows of sub-pixels are the same, so that the charging time of the two rows of sub-pixels by the data lines is doubled, the charging rate of the display device is improved, the two rows of sub-pixels are ensured not to be subjected to color mixing, and the display effect of the display device is improved. In addition, the display device provided by the embodiment of the application can be suitable for high refresh rate/high PPI products; meanwhile, the driving mode of line-by-line scanning is compatible; the design of a display panel in the display device is not changed, and a new Mask plate is designed without consuming resources (Mask is not changed); the method can also be suitable for low refresh frequency products, and can meet the requirements of different customers.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A display panel, comprising:

the scanning lines and the data lines are intersected and insulated;

a plurality of sub-pixels arranged in an array;

2. The display panel according to claim 1, wherein the pixels of the same row of the sub-pixels arranged along the first direction have the same color.

3. The display panel of claim 2, wherein the sub-pixel is located in an area defined by the data line and the scan line, the sub-pixel comprising an open area, the open area comprising:

a substrate;

a first conductive layer on the substrate;

4. The display panel according to claim 3, wherein a minimum distance between an orthographic projection of the data line on the substrate to an orthographic projection of the first conductive layer on the substrate is greater than or equal to a first preset value.

5. The display panel according to claim 4, wherein the first preset value is greater than or equal to 5.0 μm.

6. The display panel according to claim 3, wherein an outline of an orthographic projection of the patterned second conductive layer on the substrate is located within an outline of an orthographic projection of the first conductive layer on the substrate, and a distance from the outline of the orthographic projection of the second conductive layer on the substrate to the outline of the orthographic projection of the first conductive layer on the substrate is greater than or equal to a second preset value.

7. The display panel according to claim 6, wherein the second preset value is greater than or equal to 4.5 μm.

8. The display panel according to claim 1, wherein in the same row of the sub-pixels arranged along the first direction, the scan line to which the 4n +1 th sub-pixel is electrically connected and the scan line to which the 4n +2 th sub-pixel is electrically connected are configured to be turned on simultaneously.

9. The display panel according to claim 3, wherein the sub-pixel further comprises a non-open area, the open area being connected to the non-open area;

10. The display panel according to claim 8, further comprising a plurality of GOA units and a clock signal inputs, wherein the clock signal inputs are electrically connected to the GOA units, and wherein the outputs of the GOA units are electrically connected to the scan lines;

11. The display panel according to claim 10, wherein in the same row of the sub-pixels arranged along the first direction, the timing of the output signal of the GOA unit received by the scan line to which the 4n +1 th sub-pixel is electrically connected and the timing of the output signal of the GOA unit received by the scan line to which the 4n +2 th sub-pixel is electrically connected are the same, and the timing of the output signal of the GOA unit received by the scan line to which the 4n +3 th sub-pixel is electrically connected and the timing of the output signal of the GOA unit received by the scan line to which the 4n +4 th sub-pixel is electrically connected are the same.

12. The display panel of claim 10, wherein the GOA unit comprises a pull-up sub-unit configured to pull up an output signal of the GOA unit;

13. A display device characterized by comprising the display panel according to any one of claims 1 to 12.