CN114420034B - Display panel, driving method thereof and display device - Google Patents
Display panel, driving method thereof and display device Download PDFInfo
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- CN114420034B CN114420034B CN202210216458.5A CN202210216458A CN114420034B CN 114420034 B CN114420034 B CN 114420034B CN 202210216458 A CN202210216458 A CN 202210216458A CN 114420034 B CN114420034 B CN 114420034B
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
Abstract
The invention discloses a display panel, a driving method thereof and a display device, wherein the display panel comprises a pixel circuit, the pixel circuit comprises a switch module, a driving module and a light emitting module, and the driving module comprises a driving transistor; the display frame of the display panel includes a write frame and a hold frame; the switching module is configured to transmit a first data voltage to the driving module in a data writing phase in a writing frame and a holding frame; and transmitting the second data voltage to the drain of the driving transistor before and/or after the data writing phase. The display panel of the embodiment transmits the second data voltage to the drain electrode of the driving transistor before and/or after the data writing stage so as to raise the voltage of the drain electrode of the driving transistor, improve the initialization degree of the driving transistor, improve the capability of the driving transistor for releasing electrons, reduce the difference of the capability of writing frames and maintaining frames for releasing electrons before light emission, and improve the display effect of the screen body.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel, a driving method thereof and a display device.
Background
The organic light emitting diode (Organic Light Emitting Diode, OLED) has the characteristics of self-luminescence, fast response, wide color gamut, large viewing angle, high brightness and the like, and can be used for manufacturing thin display devices and flexible display devices, so that the organic light emitting diode (Organic Light Emitting Diode, OLED) gradually becomes an important point of research in the current display technology field. The organic light emitting diode needs current driving, and when the organic light emitting diode is applied to the display field, the driving transistor in the pixel circuit is controlled to provide driving current to the organic light emitting diode so that the organic light emitting diode emits light.
Along with the increase of the requirement of longer standby time of display products, low-frequency display tends to be large, and the existing display panel has the problem of flickering during low-frequency driving, so that the display effect of a low-frequency lower screen body is affected.
Disclosure of Invention
The invention provides a display panel, a driving method thereof and a display device, which are used for improving the capability of releasing electrons of a writing frame and a holding frame of the display panel, reducing the difference of the capability of releasing electrons of the writing frame and the holding frame before light emission and improving the display effect under low frequency.
According to an aspect of the present invention, there is provided a display panel including a pixel circuit including a switching module, a driving module including a driving transistor, and a light emitting module; the display frame of the display panel comprises a writing frame and a holding frame;
The switching module is configured to transmit a first data voltage to the driving module during a data writing phase in the writing frame and the holding frame; and transmitting a second data voltage to the drain of the driving transistor before and/or after the data writing phase; the driving module is used for driving the light emitting module to emit light according to the first data voltage.
Optionally, the writing frame includes an initialization phase, a data writing phase and a light emitting phase; the hold frame includes a data writing stage and a light emitting stage.
Optionally, the switch module comprises a data writing module and an initializing module;
in an initialization phase of the write frame, the initialization module is configured to be turned on, and the initialization module transmits an initialization voltage to a gate of the driving transistor; at the hold frame, the initialization module is configured to turn off;
the data writing module is configured to transmit a first data voltage to the driving transistor during a data writing phase and transmit a second data voltage to a drain of the driving transistor at least once after the data writing phase, in the writing frame and the holding frame.
Optionally, the switch module comprises a data writing module and an initializing module; in an initialization phase of the write frame, the initialization module is configured to be turned on, and the initialization module transmits an initialization voltage to a gate of the driving transistor; at the hold frame, the initialization module is configured to turn off;
The data writing module is configured to transmit a first data voltage to the driving transistor during a data writing phase and transmit a second data voltage to a drain of the driving transistor at least once before the data writing phase, in the writing frame and the holding frame.
Optionally, in the writing frame, the data writing module is configured to transmit a second data voltage to the drain of the driving transistor in an initialization phase;
the timing of the driving signals arranged in the data writing module is the same in the writing frame and the holding frame.
Optionally, the switching module further includes a compensation module, the write frame further includes a compensation phase, the compensation module is configured to be turned on during the compensation phase of the write frame, and the compensation module is configured to be turned off during the hold frame;
the data writing module is further configured to transmit a second data voltage to the drain of the driving transistor after the initialization phase and before the compensation phase.
Optionally, the data writing module is configured to transmit a second data voltage to the drain of the driving transistor at the beginning of the initialization phase.
Optionally, the first data voltage includes a gray scale voltage corresponding to the display of the present row, and the second data voltage includes a gray scale voltage corresponding to the display of the other rows.
According to another aspect of the present invention, there is provided a driving method of a display panel including a pixel circuit including a switching module, a driving module including a driving transistor, and a light emitting module; the display frame of the display panel comprises a writing frame and a holding frame; the driving method includes:
controlling the switch module to transmit a first data voltage to the driving module in a data writing stage in the writing frame and the holding frame; and controlling the switching module to transmit the second data voltage to the drain of the driving transistor before and/or after the data writing phase.
According to another aspect of the present invention, there is provided a display device comprising the display panel of any one of the first aspects.
The embodiment of the invention provides a display panel, a driving method thereof and a display device, wherein the display panel comprises a pixel circuit, the pixel circuit comprises a switch module, a driving module and a light emitting module, and the driving module comprises a driving transistor; the display frame of the display panel includes a write frame and a hold frame; the switching module is configured to transmit a first data voltage to the driving module in a data writing phase in a writing frame and a holding frame; and transmitting a second data voltage to the drain of the driving transistor before and/or after the data writing phase; the driving module is used for driving the light emitting module to emit light according to the first data voltage. The initialization degree of the driving transistor in the writing frame and the holding frame is greatly different due to the difference of the driving time sequence in the pixel circuit, so that the capability difference of the driving transistor for releasing electrons in the writing frame and the holding frame is larger. The display panel of the embodiment transmits the second data voltage to the drain electrode of the driving transistor before and/or after the data writing stage so as to raise the voltage of the drain electrode of the driving transistor, improve the initialization degree of the driving transistor, improve the capability of the driving transistor for releasing electrons, reduce the difference of the capability of writing frames and maintaining frames for releasing electrons before light emission, and improve the display effect of the screen body.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a timing diagram of a display frame of a display panel;
FIG. 2 is a diagram showing the operation of the driving transistor during the initialization phase of the pixel circuit;
FIG. 3 is a graph of the number of electrons captured by the drain of the driving transistor versus time during an initialization phase of the pixel circuit;
FIG. 4 is a diagram showing the operation of the driving transistor during the light-emitting phase of the pixel circuit;
FIG. 5 is a graph of the number of electrons captured by the drain of the driving transistor versus time during the light-emitting phase of the pixel circuit;
FIG. 6 is a graph of driving current versus time generated by the driving transistor during the light-emitting phase of the pixel circuit;
FIG. 7 is a simulation diagram of the driving current of the pixel circuit in the light emitting stage;
fig. 8 is a schematic structural view of a display panel according to an embodiment of the present invention;
fig. 9 is a schematic structural view of another display panel according to an embodiment of the present invention;
fig. 10 is a driving timing diagram of a pixel circuit of a display panel according to an embodiment of the present invention;
fig. 11 is a schematic structural view of another display panel according to an embodiment of the present invention;
fig. 12 is a driving timing diagram of a pixel circuit of another display panel according to an embodiment of the present invention;
fig. 13 is a driving timing diagram of a pixel circuit of another display panel according to an embodiment of the present invention;
fig. 14 is a driving timing diagram of a pixel circuit of another display panel according to an embodiment of the present invention;
fig. 15 is a driving timing diagram of a pixel circuit of another display panel according to an embodiment of the present invention;
fig. 16 is a driving timing diagram of a pixel circuit of another display panel according to an embodiment of the present invention;
fig. 17 is a flowchart of a driving method of a display panel according to an embodiment of the present invention;
fig. 18 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Description of the embodiments
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background art, the existing display panel easily causes a problem of flickering of the screen. The inventors have found that the reason for the occurrence of the above problem is that, generally at the time of low frequency display, a display frame of a display panel includes a write frame and a hold frame, and drive timings of pixel circuits corresponding to the write frame and the hold frame are different. Fig. 1 is a timing chart of a display frame of a display panel, fig. 2 is a diagram of an operating state of a driving transistor of a pixel circuit in an initialization stage, fig. 3 is a diagram of a relationship between the number of electrons captured by a drain of the driving transistor and time in the initialization stage, fig. 4 is a diagram of an operating state of the driving transistor of the pixel circuit in a light-emitting stage, fig. 5 is a diagram of a relationship between the number of electrons captured by a drain of the driving transistor of the pixel circuit and time in the light-emitting stage, fig. 6 is a diagram of a relationship between a driving current generated by the driving transistor of the pixel circuit in the light-emitting stage and time, fig. 7 is a simulation diagram of a driving current of the pixel circuit in the light-emitting stage, an abscissa is time (unit: s), an ordinate is a charge amount of electrons TQ (unit: C) captured by a drain D in fig. 6 and 7, and an ordinate is a driving current Id (unit mA) generated by the driving transistor T0. Referring to fig. 1 to 7, the display frame of the display panel includes a write frame A1 and a plurality of hold frames A2, and the operating frequency of the pixel circuit of the display panel is 10hz in fig. 1 as an example. The driving timings of the write frame A1 and the hold frame A2 are different, the write frame A1 includes an initialization phase, and the hold frame A2 does not include the initialization phase. In the initialization phase, the written initialization voltage controls the driving transistor to release the trapped electron e so that the electron e can be recaptured in the light emitting phase, the charge TQ of the trapped electron e is released continuously as the initialization proceeds, and the charge TQ eventually approaches zero, by way of example, the gate voltage vg= -3V of the gate G of the driving transistor, the source voltage vs=1.1V of the source S, and the drain voltage vd=1.1V of the drain. In the light-emitting stage of the writing frame A1 and the holding frame A2, the gate voltage vg=2.3v of the gate G of the driving transistor, the source voltage vs=4.6v of the source S, the drain voltage vd= -0.4V of the drain D, and in the light-emitting stage, the drain D of the driving transistor T0 continuously captures electrons until the driving transistor TO generates a stable driving current Id, thereby ensuring stable light emission. In summary, in the writing frame and the holding frame, the initialization degrees of the driving transistors are different, and the capability of the drains of the driving transistors to release electrons is different, which may cause uneven light emission in the light emitting stage, and further cause a problem that the screen body flickers during light emission.
In view of the above, the present embodiment provides a display panel, fig. 8 is a schematic structural diagram of the display panel provided in the embodiment of the present invention, referring to fig. 8, a display panel 01 includes a pixel circuit 011, the pixel circuit 011 includes a switch module 10, a driving module 11 and a light emitting module 12, and the driving module 11 includes a driving transistor T0; the display frame of the display panel 01 includes a write frame and a hold frame;
the switching module 10 is configured to transmit the first data voltage to the driving module 11 in the data writing phase in the writing frame and the holding frame; and transmitting a second data voltage to the drain D of the driving transistor T0 before and/or after the data writing phase; the driving module 11 is used for driving the light emitting module 12 to emit light according to the first data voltage.
The switching module 10 in the pixel circuit 011 is a module that performs a switching function, and may include a plurality of switching modules 10, and may be connected to the driving module 11, and transmit a corresponding voltage to the driving module 11, so as to control the driving module 11 to generate a required driving signal, for example, generate a required driving current to drive the light emitting module 12 to emit light. The switching module 10 may be one or more of a data writing module transmitting a data voltage, an initializing module transmitting an initializing signal, a compensating module compensating for threshold voltage compensation of the driving transistor, and a light emission control module for light emission control, which are well known to those skilled in the art. The switching module 10 may be turned on or off in response to a signal on the scan line to control transmission or off transmission of the signal.
In the write frame and the sustain frame, the switching module 10 may transmit the second data voltage to the drain D of the driving transistor T0 before the data writing period, or transmit the second data voltage to the drain D of the driving transistor T0 after the data writing period, and further, or transmit the second data voltage to the drain D of the driving transistor T0 after the data writing period, both before and after the data writing period. The present embodiment transmits the second data voltage to the drain D of the driving transistor T0 after the data writing period, and drives after the data writing period is completedThe voltage vg=v1- |vth| of the gate G of the transistor T0, where V1 is the first data voltage, and the voltages vd=v1, VG and VD of the drain D of the driving transistor T0 are both greater than zero, and thus the absolute value of the gate-drain voltage difference |vgd|= |vg-vd|= |vth| of the driving transistor T0. After writing the second data voltage, the voltage VD at the drain of the driving transistor T0 increases to V2, V2>V1, at this time, absolute value |VGD of voltage difference between gate and drain of driving transistor T0 ， I= |vg-vd|=v2-v1+|vth| according to which i VGD is known ， >VGD. Therefore, the voltage of the drain D of the driving transistor T0 increases, which increases the initialization degree of the driving transistor T0, increases the absolute value of the voltage difference between the gate and the drain of the driving transistor T0, and increases the ability of the driving transistor T0 to release electrons. The display panel of the embodiment improves the voltage of the drain electrode of the driving transistor by transmitting the second data voltage to the drain electrode of the driving transistor before and/or after the data writing stage, thereby improving the capability of the driving transistor to release electrons, reducing the difference of the capability of writing frames and maintaining frames to release electrons before light emission, and improving the display effect of the screen body.
With continued reference to fig. 8, optionally, the first data voltage includes a gray scale voltage corresponding to the display of the present row, and the second data voltage includes a gray scale voltage corresponding to the display of the other rows.
Specifically, when the switching module 10 transmits the second data voltage to the driving transistor T0 before the data writing phase of the writing frame and the holding frame, the second data voltage may display the corresponding gray scale voltage for the previous row of the current row. When the switching module 10 transmits the second data voltage to the driving transistor T0 after the data writing period of the writing frame and the holding frame and before the light emitting period, the second data voltage may display the corresponding gray scale voltage for the subsequent line of the current line. In other words, the second data voltage can be transmitted to the drain electrode of the driving transistor T0 of the pixel circuit of the current row during the writing process of the data voltage of the pixel circuit of the current row relative to the preceding and/or following pixel circuits of the current row, so as to enhance the initialization degree of the pixel circuit of the current row, further enhance the capability of the driving transistor T0 to release electrons, further reduce the difference between the capability of writing frames and the capability of maintaining frames to release electrons before light emission, and enhance the display effect of the screen.
Fig. 9 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 9, optionally, a switch module includes a data writing module 101 and an initializing module 102;
In the initialization phase of the write frame, the initialization module 102 is configured to be turned on, and the initialization module 102 transmits an initialization voltage to the gate G of the driving transistor T0; at the hold frame, the initialization module 102 is configured to turn off;
in the write frame and the hold frame, the data writing module 101 is configured to transfer the first data voltage to the driving transistor T0 in the data writing phase, and transfer the second data voltage to the drain D of the driving transistor T0 at least once after the data writing phase.
The pixel circuit 011 further includes a first light emission control module 14 and a second light emission control module 15, the first light emission control module 14 is connected between the first power supply Vdd and the source S of the driving transistor T0, the second light emission control module 15 is connected between the drain D of the driving transistor T0 and the first terminal of the light emitting module 12, and the second terminal of the light emitting module 12 is connected to the second power supply Vss. The first control module 14 and the second control module 15 are configured to be turned on in response to a signal on the light emission control signal line EM during the light emission phase of the write frame and the sustain frame. The data writing module 101 is connected to the first scan line S1, and is turned on or off according to a signal on the first scan line S1. The initialization module 102 is connected to the second scan line S2, and is turned on or off according to a signal on the second scan line S2.
Optionally, the switching module further comprises a compensation module 13, the write frame further comprising a compensation phase, the compensation module 13 being configured to be on during the compensation phase of the write frame and the compensation module 13 being configured to be off during the hold frame. The compensation module 13 is connected between the gate G and the drain D of the driving transistor T0, and is used for compensating the threshold voltage of the driving transistor T0. The compensation module 13 is connected to the third scan line S3, and is turned on or off according to a signal on the third scan line S3.
Fig. 10 is a driving timing chart of a pixel circuit of a display panel according to an embodiment of the present invention, where the driving timing chart shown in fig. 10 is applicable to the pixel circuit shown in fig. 9, and referring to fig. 9 and 10, optionally, a writing frame A1 includes an initialization phase t11, a data writing phase t12 and a light emitting phase t15; the hold frame A2 includes a data writing period t16 and a light emitting period t18. In the present embodiment, the data writing module 101 is illustratively turned on when the signal on the first scan line S1 is at a low potential, the initializing module 102 is turned on when the signal on the second scan line S2 is at a high potential, the compensating module 13 is turned on when the signal on the third scan line S3 is at a high potential, and the first light emission control module 14 and the second light emission control module 15 are turned on when the signal on the light emission control signal line EM is at a low potential.
In the initialization stage T11 of the writing frame A1, the signal on the first scan line S1 is at a high potential, so that the data writing module 101 is turned off, the signal on the third scan line S3 is at a low potential, so that the compensation module 13 is turned off, the signal on the emission control signal line EM is at a high potential, so that the first emission control module 14 and the second emission control module 15 are turned off, the signal on the second scan line S2 is at a high potential, so that the initialization module 102 is turned on, and the initialization voltage is written into the gate G of the driving transistor T0 via the initialization module 102, thereby completing the initialization of the gate G of the driving transistor T0.
In the data writing stage T12 of the writing frame, the signal on the second scan line S2 is at a low potential, so that the initialization module 102 is turned off, the signal on the light emission control signal line EM is at a high potential, so that the first light emission control module 14 and the second light emission control module 15 are turned off, the signal on the first scan line S1 is at a low potential, so that the data writing module 101 is turned on, the signal on the third scan line S3 is at a high potential, so that the compensation module 13 is turned on, and the first data voltage is written into the gate G of the driving transistor T0 via the data writing module 101, the driving transistor T0 and the compensation module 13.
Optionally, the write frame A1 further includes a compensation phase t13, and during the compensation phase t13 of the write frame A1, the compensation module 13 is configured to be turned on, and during the hold frame A2, the compensation module 13 is configured to be turned off. In the compensation phase t13 of the write frame A1, the on states of the compensation module 13, the initialization module 102, the first light emitting control module 14 and the second light emitting control module are the same as the data write phase t12 of the write frame A1, the signal on the first scan line S1 jumps to the high potential after the low potential is maintained for the set time, and the data write module 101 is turned off after the set time is led. In the compensation phase T13 of the write frame A1, the compensation module 13 is in an on state, and compensation of the threshold voltage of the driving transistor T0 is achieved by the compensation module 13.
In the drain potential adjustment stage T14 of the writing frame A1 (i.e., a stage of writing the second data voltage into the drain D of the driving transistor T0), the signal on the second scan line S2 is at a low potential, so that the initialization module 102 is turned off, the signal on the third scan line S3 is at a low potential, so that the compensation module 13 is turned off, the signal on the emission control signal line EM is at a high potential, so that the first emission control module 14 and the second emission control module 15 are turned off, the signal on the first scan line S1 is at a low potential, so that the data writing module 101 is turned on, the second data voltage is transmitted to the source S of the driving transistor T0 through the turned-on data writing module 101, the driving transistor T0 is turned on, the second data voltage is written into the drain D of the driving transistor T0 through the driving transistor T0, and by writing the second data voltage into the drain D of the driving transistor T0 in the drain potential adjustment stage T14, the voltage of the drain D can be increased, and thus the capability of the driving transistor T0 to release electrons can be improved, and the difference of the writing frame A1 and the holding frame A2 can be reduced.
In the light emitting stage T15 of the write frame A1, the signal on the second scan line S2 is at a low potential, so that the initialization module 102 is turned off, the signal on the third scan line S3 is at a low potential, so that the compensation module 13 is turned off, the signal on the first scan line S1 is at a high potential, so that the data writing module 101 is turned off, the signal on the light emission control signal line EM is at a low potential, so that the first light emission control module 14 and the second light emission control module 15 are turned on, the first power voltage supplied by the first power supply Vdd is transmitted to the source S of the driving transistor T0, and the driving transistor T0 generates a driving current according to the voltages of the gate G and the source S thereof, so as to drive the light emitting module 12 to emit light.
In the hold frame A2, the signal on the second scan line S2 is continuously low, so that the initialization module 102 is in the off state, and the signal on the third scan line S3 is continuously low, so that the compensation module 13 is in the off state. In the data writing stage T16 of the holding frame A2, the signal on the light emission control signal line EM is at a high potential, so that the first light emission control module 14 and the second light emission control module 15 are turned off, the signal on the first scan line S1 is at a low potential, so that the data writing module 101 is turned on, and the first data voltage is written into the source S and the drain D of the driving transistor T0 through the data writing module 101. After the end of the data writing period t16 of the hold frame A2, the signal on the first scanning line S1 is at a high potential, so that the data writing module 101 is turned off. In the drain potential adjustment stage T17 of the holding frame A2, the signal on the first scan line S1 is at a low potential, so that the data writing module 101 is turned on again, and the second data voltage is written into the drain of the driving transistor T0 through the source S of the driving transistor T0. In the light emission period t18 of the hold frame A2, the signal on the first scanning line S1 is at a high potential, so that the data writing module 101 is turned off. The signal on the emission control signal line EM is at a low potential, so that the first emission control module 14 and the second emission control module 15 are turned on, the first power voltage provided by the first power supply Vdd is transmitted to the source S of the driving transistor T0, and the driving transistor T0 generates a driving current according to the voltages of the gate G and the source S thereof, so as to drive the light emitting module 12 to emit light.
Fig. 11 is a schematic diagram of another display panel according to an embodiment of the invention, referring to fig. 11, optionally, the data writing module 101 includes a first transistor T1, a first pole of the first transistor T1 is connected to a data signal line Vdata, a second pole of the first transistor T1 is connected to a source S of the driving transistor T0, a gate of the first transistor T1 is connected to a first scan line S1, and the data signal line Vdata is used for providing a first data voltage and a second data voltage. The initialization module 102 includes a second transistor T2, a first pole of the second transistor T2 is connected to an initialization signal line Vref, a second pole of the second transistor T2 is connected to a gate G of the driving transistor T0, a gate of the second transistor T2 is connected to a second scan line S2, and the initialization signal line Vref is used for providing an initialization voltage. The compensation module 13 includes a third transistor T3, a first pole of the third transistor T3 is connected to the drain D of the driving transistor T0, a second pole of the third transistor T3 is connected to the gate G of the driving transistor T0, and a gate of the third transistor T3 is connected to the third scan line S3. The first light emitting control module 14 includes a fourth transistor T4, a first pole of the fourth transistor T4 is connected to the first power supply Vdd, a second pole of the fourth transistor T4 is connected to the source S of the driving module T0, and a gate of the fourth transistor T4 is connected to the light emitting control signal line EM. The second light-emitting control module 15 includes a fifth transistor T5, a first electrode of the fifth transistor T5 is connected to the drain D of the driving transistor T0, a second electrode of the fifth transistor T5 is connected to the first end of the light-emitting module 12, and a gate electrode of the fifth transistor T5 is connected to the light-emitting control signal line EM. The driving transistor T0, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be N-type transistors or P-type transistors.
The driving timing chart shown in fig. 10 is applicable to the pixel circuit shown in fig. 11, and referring to fig. 10 and 11, the driving transistor T0, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 are all P-type transistors, and the second transistor T2 and the third transistor T3 are N-type transistors.
In the initialization stage T11 of the write frame A1, the signal on the first scan line S1 is at a high potential, so that the first transistor T1 is turned off, the signal on the third scan line S3 is at a low potential, so that the third transistor T3 is turned off, the signal on the emission control signal line EM is at a high potential, so that the fourth transistor T4 and the fifth transistor T5 are turned off, the signal on the second scan line S2 is at a high potential, so that the second transistor T2 is turned on, the initialization voltage provided by the initialization signal line Vref is written into the gate G of the driving transistor T0, and the initialization of the gate G of the driving transistor T0 is completed. In the data writing stage T12 of the writing frame A1, the signal on the second scan line S2 is at a low potential, so that the second transistor T2 is turned off, the signal on the light emission control signal line EM is at a high potential, so that the fourth transistor T4 and the fifth transistor T5 are turned off, the signal on the first scan line S1 is at a low potential, so that the first transistor T1 is turned on, the signal on the third scan line S3 is at a high potential, so that the third transistor T3 is turned on, and the first data voltage is written to the gate G of the driving transistor T0 via the first transistor T1, the driving transistor T0, and the third transistor T3. In the compensation phase T13 of the write frame A1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the fifth transistor T5 have the same on states as the data write phase T12, the signal on the first scan line S1 jumps to a high potential after a low potential maintaining set time, the first transistor T1 is turned off after a pilot set time, the third transistor T3 is in an on state in the compensation phase T13, and compensation of the threshold voltage of the driving transistor T0 is achieved through the third transistor T3. In the drain potential adjustment stage T14 of the write frame A1 (i.e., a stage in which the second data voltage is written into the drain D of the driving transistor T0), the signal on the second scan line S2 is low, so that the second transistor T2 is turned off, the signal on the third scan line S3 is low, so that the third transistor T3 is turned off, the signal on the emission control signal line EM is high, so that the fourth transistor T4 and the fifth transistor T5 are turned off, the signal on the first scan line S1 is low, so that the first transistor T1 is turned on, the second data voltage is transmitted to the source S of the driving transistor T0 via the turned-on first transistor T1, the driving transistor T0 is turned on, and the second data voltage is written into the drain of the driving transistor T0 via the driving transistor T0. By writing the second data voltage to the drain D of the driving transistor T0 in the drain potential adjustment stage T14, the number of electrons released from the drain D can be increased, thereby improving the ability of the driving transistor T0 to release electrons, and reducing the difference between the ability of writing the frame A1 and the ability of holding the frame A2 to release electrons. In the light emitting stage T15 of the write frame A1, the signal on the second scan line S2 is at a low potential, so that the second transistor T2 is turned off, the signal on the third scan line S3 is at a low potential, so that the third transistor T3 is turned off, the signal on the first scan line S1 is at a high potential, so that the first transistor T1 is turned off, the signal on the light emission control signal line EM is at a low potential, so that the fourth transistor T4 and the fifth transistor T5 are turned on, the first power voltage supplied by the first power supply Vdd is transmitted to the source S of the driving transistor T0, and the driving transistor T0 generates a driving current according to the voltages of the gate G and the source S thereof, so as to drive the light emitting module 12 to emit light.
In the hold frame A2, the signal on the second scan line S2 is continuously low, so that the second transistor T2 is in an off state, and the signal on the third scan line S3 is continuously low, so that the third transistor T3 is in an off state. In the data writing stage T16 of the holding frame A2, the signal on the light emission control signal line EM is at a high potential, so that the fourth transistor T4 and the fifth transistor T5 are turned off, the signal on the first scanning line S1 is at a low potential, so that the first transistor T1 is turned on, and the first data voltage is written to the source S and the drain D of the driving transistor T0 via the first transistor T1. After the end of the data writing period T16 of the holding frame A2, the signal on the first scan line S1 is at a high potential, so that the first transistor T1 is turned off. In the drain potential adjustment stage T17 of the holding frame A2, the signal on the first scan line S1 is at a low potential, so that the first transistor T1 is turned on, and the second data voltage is written into the drain of the driving transistor T0 through the source S of the driving transistor T0. In the light emission period T18 of the frame A2, the signal on the first scan line S1 is at a high potential, so that the first transistor T1 is turned off. The signal on the emission control signal line EM is at a low potential, so that the fourth transistor T4 and the fifth transistor T5 are turned on, the first power voltage provided by the first power supply Vdd is transmitted to the source S of the driving transistor T0, and the driving transistor T0 generates a driving current according to the voltages of the gate G and the source S thereof, so as to drive the light emitting module 12 to emit light.
From the above analysis, in the drain potential adjustment stage T14 of the writing frame A1, the second data voltage is written into the drain D of the driving transistor T0, so that the voltage of the drain D can be increased, the initialization degree of the driving transistor T0 can be improved, the capability of the driving transistor T0 to release electrons can be further improved, the difference between the capability of releasing electrons before the writing frame A1 and the capability of maintaining the frame A2 to emit light can be reduced, and the display effect of the screen can be improved.
Fig. 12 is a driving timing chart of a pixel circuit of another display panel according to an embodiment of the present invention, where the driving timing chart shown in fig. 12 is applicable to the pixel circuit shown in fig. 11, and the driving timing chart shown in fig. 12 is different from that shown in fig. 10 in that the driving timing chart shown in fig. 12 includes two drain potential adjustment stages, namely, a first drain potential adjustment stage t19 and a second drain potential adjustment stage t20 after writing the data writing stage t12 of the frame A1, and the holding frame A2 includes two drain potential adjustment stages, namely, a first drain potential adjustment stage t21 and a second drain potential adjustment stage t22 after writing the data writing stage t 16. Referring to fig. 11 and 12, the operation of the pixel circuit corresponding to the driving timing shown in fig. 12 is similar to that of the driving timing shown in fig. 10, and the description of this embodiment is omitted here. The present embodiment is configured such that the data writing module 101 transmits the second data voltage to the drain D of the driving transistor T0 twice after the data writing period in the writing frame A1 and the holding frame A2, i.e., the second data voltage is written in the first drain potential adjustment period T19 and the second drain potential adjustment period T20 of the writing frame A1, and the second data voltage is written in the first drain potential adjustment period T21 and the second drain potential adjustment period T22 of the holding frame A2. The data writing module 101 is configured to transmit the second data voltage to the drain D of the driving transistor T0 twice after the data writing period T12 of the writing frame A1, and transmit the second data voltage to the drain D of the driving transistor T0 twice after the data writing period T16 of the holding frame A2, increasing the number of times the drain of the driving transistor T0 writes the second data voltage, further increasing the voltage of the drain D of the driving transistor T0, increasing the initializing degree of the driving transistor T0, increasing the ability of the drain D of the driving transistor T0 to release electrons, and being beneficial to further reducing the difference in the ability of the writing frame A1 and the holding frame A2 to release electrons.
Fig. 13 is a driving timing diagram of a pixel circuit of another display panel according to an embodiment of the present invention, where the driving timing diagram shown in fig. 13 is applicable to the pixel circuit of the display panel shown in fig. 11, and referring to fig. 11 and fig. 13, the switch module 10 includes a data writing module 101 and an initializing module 102; in the initialization phase T11 of the write frame A1, the initialization module 102 is configured to be turned on, and the initialization module 102 transmits an initialization voltage to the gate G of the driving transistor T0; at hold frame A2, initialization module 102 is configured to turn off;
in the write frame A1 and the hold frame A2, the data write module 101 is configured to transmit a first data voltage to the driving transistor T0 during a data write phase and transmit a second data voltage to the drain D of the driving transistor T0 at least once before the data write phase.
Optionally, in the write frame A1, the data write module 101 is configured to transmit the second data voltage to the drain D of the driving transistor T0 in the initialization phase T11;
the timings of the driving signals disposed in the data writing module 101 are the same in the writing frame A1 and the holding frame A2.
In this embodiment, the second scan line S2, the third scan line S3, and the emission control signal line EM when writing the frame A1 are the same as the timing chart shown in fig. 10, and therefore, the conduction conditions of the corresponding transistors are the same as the case of writing the frame A1 shown in fig. 10, and the second scan line S2, the third scan line S3, and the emission control signal line EM when holding the frame A2 are the same as the timing chart shown in fig. 10, and therefore, the conduction conditions of the corresponding transistors are the same as the case of holding the frame A2 shown in fig. 10. The difference between the pixel circuits in fig. 13 and the pixel circuits in the driving timing shown in fig. 10 is that the drain potential adjustment stage t14 is advanced to the initialization stage t11 in the writing frame A1, and the drain potential adjustment stage t17 in the holding frame A2 is advanced accordingly.
In the embodiment, the writing frame A1 includes only one drain potential adjustment stage T14, and the drain potential adjustment stage T14 of the writing frame A1 is located in the initialization stage T11, and the data writing module 101 transmits the second data voltage to the drain D of the driving transistor T0 in the drain potential adjustment stage T14. Optionally, the data writing module 101 is configured to transmit the second data voltage to the drain D of the driving transistor T0 at the beginning of the initialization phase T11. Compared with the writing frame A1, the drain potential adjusting stage T14 is located after the data writing stage T12, and the embodiment advances the drain potential adjusting stage T14 to the initializing stage T11, so that the time for the drain D and the gate G of the driving transistor T0 to have a larger voltage difference can be prolonged, the time for the driving transistor T0 to have a larger electron releasing capability can be prolonged, and the difference between the electron releasing capability of the writing frame A1 and the holding frame A2 can be further reduced. Meanwhile, the write frame A1 and the hold frame A2 have the same timing sequence of the driving signals configured in the data write module 101, so that the drain potential adjustment stage t17 of the hold frame A2 is correspondingly advanced, and the timing sequences are the same, so that the scanning circuit structure for providing the signals on the first scanning line S1 is simpler, and the layout of the display panel is simplified.
Fig. 14 is a driving timing chart of a pixel circuit of another display panel according to an embodiment of the present invention, where the timing chart shown in fig. 14 is applicable to the pixel circuit of the display panel shown in fig. 11, referring to fig. 11 and 14, alternatively, in the writing frame A1 and the holding frame A2, the data writing module 101 is configured to transmit a first data voltage to the driving transistor T0 in a data writing phase, transmit a second data voltage to the drain D of the driving transistor T0 at least once before the data writing phase, and transmit the second data voltage to the drain D of the driving transistor T0 at least once after the data writing phase.
In this embodiment, it is exemplarily shown that the writing frame A1 and the holding frame A2 each include two drain potential adjustment phases, the first drain potential adjustment phase t19 of the writing frame A1 is located in the initialization phase t11, and the second drain potential adjustment phase t20 is located after the compensation phase t13 and before the light-emitting phase t 15. In the write frame A1 and the hold frame A2, the timings of the driving signals disposed in the data write module 101 are the same, that is, the first drain potential adjustment stage t21 of the hold frame A2 is located before the data write stage t16 of the hold frame A2, and the second drain potential adjustment stage t22 is located after the data write stage t16 of the hold frame A2 and before the light emission stage t 18. After the initialization period T11 of the writing frame A1 is completed, the signal on the second scan line S2 changes from high to low, and the potential of the gate G of the driving transistor T0 is reduced due to the coupling effect of the coupling capacitor of the second transistor T2, so as to reduce the potential of the drain D of the driving transistor T0. Therefore, by writing the second data voltage again through the data writing module 101 in the second drain potential adjustment stage T20, by writing the second data voltage to the drain D of the driving transistor T0 a plurality of times, it is possible to ensure that the voltage of the drain D of the driving transistor T0 increases, to increase the initialization degree of the driving transistor T0, and to further increase the capability of the drain D to release electrons.
Fig. 15 is a driving timing chart of a pixel circuit of another display panel according to an embodiment of the present invention, where the timing chart shown in fig. 15 is applicable to the pixel circuit of the display panel shown in fig. 11, and referring to fig. 11 and 15, the data writing module 101 is optionally further configured to transmit the second data voltage to the drain D of the driving transistor T0 after the initialization stage T11 and before the compensation stage T13. It is also exemplarily shown in the present embodiment that the data writing module 101 is further configured to transmit the second data voltage to the drain D of the driving transistor T0 at least once after the data writing phase.
In this embodiment, it is exemplarily shown that the writing frame A1 and the holding frame A2 each include two drain potential adjustment phases, the first drain potential adjustment phase t19 of the writing frame A1 is located after the initialization phase t11 and before the compensation phase t13, and the second drain potential adjustment phase t20 is located after the compensation phase t13 and before the light emission phase t 15. In the write frame A1 and the hold frame A2, the timings of the driving signals disposed in the data write module 101 are the same, that is, the first drain potential adjustment stage t21 of the hold frame A2 is located before the data write stage t16 of the hold frame A2, and the second drain potential adjustment stage t22 is located after the data write stage t16 of the hold frame A2 and before the light emission stage t 18. In the writing frame A1 and the holding frame A2, the second data voltage is written to the drain D of the driving transistor T0 twice to further raise the voltage of the drain D of the driving transistor T0, raise the initialization degree of the driving transistor T0, raise the capability of the drain D of the driving transistor T0 to release electrons, and further reduce the difference of the capability of the writing frame A1 and the holding frame A2 to release electrons.
Fig. 16 is a driving timing chart of a pixel circuit of another display panel according to an embodiment of the present invention, where the timing chart shown in fig. 16 is applicable to the pixel circuit shown in fig. 11, and referring to fig. 11 and 16, optionally, the data writing module 101 is further configured to transmit the second data voltage to the drain D of the driving transistor T0 during the initialization period T11, after the initialization period T11, and before the compensation period T13, after the compensation period T13, and before the light-emitting period T15, in the writing frame A1. The timings of the driving signals disposed in the data writing module 101 are the same in the writing frame A1 and the holding frame A2.
In the present embodiment, the writing frame A1 includes a first drain potential adjustment stage t19, a second drain potential adjustment stage t20, and a third drain potential adjustment stage t23, wherein the first drain potential adjustment stage t19 is located in the initialization stage t11, the second drain potential adjustment stage t20 is located after the initialization stage t11 and before the compensation stage t13, and the third drain potential adjustment stage t23 is located after the compensation stage t13 and before the light emitting stage t15 of the writing frame A1. Since the write frame A1 and the hold frame A2 have the same timing of the drive signals arranged in the data write module 101, the hold frame A2 also includes a first drain potential adjustment stage t21, a second drain potential adjustment stage t22, and a third drain potential adjustment stage t24. In the writing frame A1 and the holding frame A2, the voltage of the drain D of the driving transistor T0 is continuously raised by writing the second data voltage to the drain D of the driving transistor T0 three times, so as to increase the initialization degree of the driving transistor T0, further increase the capability of the drain D of the driving transistor T0 to release electrons, and further reduce the difference of the capability of the writing frame A1 and the holding frame A2 to release electrons.
The embodiment of the invention also provides a driving method of a display panel, referring to fig. 9, optionally, the display panel 01 includes a pixel circuit 011, the pixel circuit 011 includes a switch module 10, a driving module 11 and a light emitting module 12, and the driving module 11 includes a driving transistor T0; the display frame of the display panel 01 includes a write frame and a hold frame; fig. 17 is a flowchart of a driving method of a display panel according to an embodiment of the present invention, and referring to fig. 17, the driving method includes:
s101: in the writing frame and the holding frame, the control switch module transmits a first data voltage to the driving module in a data writing stage; and controls the switching module to transmit the second data voltage to the drain of the driving transistor before and/or after the data writing phase.
The driving method of the display panel in this embodiment has the same advantages as those of the display panel, and the description of this embodiment is omitted here.
The embodiment of the invention also provides a display device, fig. 18 is a schematic structural diagram of the display device provided by the embodiment of the invention, and referring to fig. 18, the display device 02 includes the display panel 01 described above. The display device 02 may be a mobile phone as shown in fig. 18, or may be a computer, a television, an intelligent wearable display device, etc., which is not particularly limited in the embodiment of the present invention.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (8)
1. A display panel, characterized in that the display panel comprises a pixel circuit, the pixel circuit comprises a switch module, a driving module and a light emitting module, and the driving module comprises a driving transistor; the display frame of the display panel comprises a writing frame and a holding frame; the writing frame comprises an initialization stage, a data writing stage and a light emitting stage; the holding frame includes a data writing stage and a light emitting stage;
The switching module is configured to transmit a first data voltage to the driving module during a data writing phase in the writing frame and the holding frame; and transmitting a second data voltage to the drain of the driving transistor before and/or after the data writing phase; the driving module is used for driving the light emitting module to emit light according to the first data voltage;
the first data voltage comprises a gray scale voltage corresponding to the display of the line, and the second data voltage comprises a gray scale voltage corresponding to the display of other lines.
2. The display panel of claim 1, wherein the switching module comprises a data writing module and an initializing module;
in an initialization phase of the write frame, the initialization module is configured to be turned on, and the initialization module transmits an initialization voltage to a gate of the driving transistor; at the hold frame, the initialization module is configured to turn off;
the data writing module is configured to transmit a first data voltage to the driving transistor during a data writing phase and transmit a second data voltage to a drain of the driving transistor at least once after the data writing phase, in the writing frame and the holding frame.
3. The display panel according to claim 1 or 2, wherein the switching module includes a data writing module and an initializing module; in an initialization phase of the write frame, the initialization module is configured to be turned on, and the initialization module transmits an initialization voltage to a gate of the driving transistor; at the hold frame, the initialization module is configured to turn off;
the data writing module is configured to transmit a first data voltage to the driving transistor during a data writing phase and transmit a second data voltage to a drain of the driving transistor at least once before the data writing phase, in the writing frame and the holding frame.
4. The display panel of claim 3, wherein, in the write frame, the data write module is configured to transmit a second data voltage to the drain of the drive transistor during an initialization phase;
the timing of the driving signals arranged in the data writing module is the same in the writing frame and the holding frame.
5. The display panel of claim 3, wherein the switching module further comprises a compensation module, the write frame further comprising a compensation phase, the compensation module configured to be on during the compensation phase of the write frame, the compensation module configured to be off during the hold frame;
The data writing module is further configured to transmit a second data voltage to the drain of the driving transistor after the initialization phase and before the compensation phase.
6. The display panel of claim 3, wherein the data writing module is configured to transmit a second data voltage to the drain of the driving transistor at the beginning of the initialization phase.
7. The driving method of the display panel is characterized in that the display panel comprises a pixel circuit, the pixel circuit comprises a switch module, a driving module and a light emitting module, and the driving module comprises a driving transistor; the display frame of the display panel comprises a writing frame and a holding frame; the writing frame comprises an initialization stage, a data writing stage and a light emitting stage; the holding frame includes a data writing stage and a light emitting stage; the driving method includes:
controlling the switch module to transmit a first data voltage to the driving module in a data writing stage in the writing frame and the holding frame; and controlling the switching module to transmit a second data voltage to the drain of the driving transistor before and/or after the data writing phase;
The first data voltage comprises a gray scale voltage corresponding to the display of the line, and the second data voltage comprises a gray scale voltage corresponding to the display of other lines.
8. A display device comprising the display panel of any one of claims 1-6.
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| CN112150967A (en) * | 2020-10-20 | 2020-12-29 | 厦门天马微电子有限公司 | Display panel, driving method and display device |
| CN113012643A (en) * | 2021-03-01 | 2021-06-22 | 上海天马微电子有限公司 | Display panel, driving method thereof and display device |
| CN113763888A (en) * | 2021-09-13 | 2021-12-07 | 厦门天马显示科技有限公司 | Display panel and display device |
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| CN114420034A (en) | 2022-04-29 |
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