CN114414882A - Quadratic fitting processing method, system, device, processor and storage medium for reducing detection power error of RF detection module - Google Patents
Quadratic fitting processing method, system, device, processor and storage medium for reducing detection power error of RF detection module Download PDFInfo
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Abstract
The invention relates to a quadratic fitting processing method for reducing detection power error aiming at an RF detection module, which comprises the following steps: performing linear fitting on the power data of the calibration voltage points, and eliminating power errors of adjacent voltage points of the same calibration frequency point; and performing fitting calculation on two adjacent calibration point values of the non-calibration frequency points to obtain power data. By adopting the quadratic fitting processing method, the system, the device, the processor and the computer readable storage medium for reducing the detection power error aiming at the RF detection module, the errors generated in calibration and caused by non-calibrated frequency points are eliminated in the detection of the power of different frequency points, and the accuracy of the fitted power in the input detection of the RF detection is improved through the quadratic fitting algorithm.
Description
Technical Field
The invention relates to the field of radio frequency instruments, in particular to the field of signal source power calibration, and specifically relates to a quadratic fitting processing method, a system, a device, a processor and a computer readable storage medium for reducing detection power errors aiming at an RF detection module.
Background
The measured RF signal is applied to a detector. In the measurement mode, the output voltage is in a linear dB relationship with the input signal level (nominal values should be based on the log-choice detector manual), with typical output voltages ranging from a V to f V (a and f values should be based on the log-choice detector manual). The measurement results are provided as digital codes at the output of a 12-bit ADC, and the output of the RF detector can be seamlessly interfaced with the ADC.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a quadratic fitting processing method, a system, a device, a processor and a computer readable storage medium for reducing detection power errors aiming at an RF detection module, which have the advantages of high accuracy, small error and wider application range.
In order to achieve the above object, the present invention provides a quadratic fit processing method, system, apparatus, processor and computer readable storage medium for reducing detection power error for an RF detection module, comprising:
the quadratic fitting processing method for reducing the detection power error aiming at the RF detection module is mainly characterized by comprising the following steps of:
(1) performing linear fitting on the power data of the calibration voltage points, and eliminating power errors of adjacent voltage points of the same calibration frequency point;
(2) and performing fitting calculation on two adjacent calibration point values of the non-calibration frequency points to obtain power data.
Preferably, the step (1) specifically comprises the following steps:
(1.1) judging whether the current voltage PowInV is in a voltage range of the detector, namely judging whether a is more than the current voltage PowInV and less than f, wherein the voltage range of the detector is [ a, f ], and if so, continuing the step (1.2); otherwise, calculating corresponding power values under the conditions that the current voltage PowInV is less than a and the current voltage PowInV is greater than f;
(1.2) calculating a calibration table position interval and a voltage amount RemaindenInV exceeding a calibration voltage point;
(1.3) calculating a power value PowIndBmSim for obtaining the current voltage fitting.
Preferably, the step (1.2) of calculating the calibration table position interval includes:
the calibration table position interval is calculated according to the following formula:
wherein PowInV is the current voltage, StartPowInV is the starting voltage falling within the range, Step is the interval of the voltage range, and add is the cumulative number.
Preferably, the step (1.2) of calculating the voltage amount RemainderInV exceeding the calibration voltage point includes:
calculating the voltage amount RemainderInV beyond the calibration voltage point according to the following formula:
RemainderInV＝PowInV-StartPowInV-(interval-add)×Step；
wherein PowInV is the current voltage, StartPowInV is the initial voltage falling in the range, Step is the interval of the voltage range, add is the cumulative number, and interval is the position of the calibration table.
Preferably, the step (1.3) of calculating the power value powdnbmsim for obtaining the current voltage fitting specifically includes:
calculating a power value PowIndBmSim for obtaining current voltage fitting according to the following formula:
PowIndBm1＝CaliForm[freqLocation][interval－1]；
PowIndBm2＝CaliForm[freqLocation][interval]；
wherein Freqlocation is a calibration frequency point, interval is a voltage interval, RemainderInV is a voltage amount exceeding the calibration voltage point, Step is an interval of a voltage range, and PowIndBm1 and PowIndBm2 are power values obtained according to the two-dimensional array respectively.
Preferably, the step (2) specifically comprises the following steps:
(2.1) if the set frequency point is a calibration frequency point, calculating a power value PowIndBmSim corresponding to the voltage; if the set frequency point is not on the calibration frequency point and the frequency point is between the calibration points F0 and F1, wherein F0 < F1, continuing the step (2.2);
(2.2) obtaining a voltage power value PowIndBmSim1 corresponding to the frequency point F0 and a voltage power value PowIndBmSim2 corresponding to the frequency point F1;
and (2.3) carrying out linear fitting to obtain a power value corresponding to the voltage under the current frequency.
Preferably, the step (2.3) of calculating the power value corresponding to the voltage specifically includes:
and calculating the power value corresponding to the voltage according to the following formula:
the PowIndBmSim1 is a voltage power value corresponding to the frequency point F0, the PowIndBmSim2 is a voltage power value corresponding to the frequency point F1, and Freq is a frequency value.
The quadratic fitting processing system for reducing the detection power error aiming at the RF detection module is mainly characterized by comprising a power divider, a detection module and a power meter, wherein the input end of the power divider is connected with a signal source, one end of the output end of the power divider is connected with the detection module, the other end of the output end of the power divider is connected with the power meter, and the detection module calibrates signals output by the signal source.
The quadratic fit processing device for reducing the detection power error aiming at the RF detection module is mainly characterized by comprising:
a processor configured to execute computer-executable instructions;
a memory storing one or more computer-executable instructions that, when executed by the processor, perform the steps of the above-described quadratic fit processing method for an RF detection module that reduces detection power errors.
The processor for implementing the quadratic fit process for reducing the detection power error of the RF detection module is mainly characterized in that the processor is configured to execute computer executable instructions, and the computer executable instructions, when executed by the processor, implement the steps of the quadratic fit process for reducing the detection power error of the RF detection module.
The computer readable storage medium is primarily characterized by having stored thereon a computer program executable by a processor to perform the steps of the above-described quadratic fit processing method for reducing detection power errors for an RF detection module.
By adopting the quadratic fitting processing method, the system, the device, the processor and the computer readable storage medium for reducing the detection power error aiming at the RF detection module, the errors generated in calibration and caused by non-calibrated frequency points are eliminated in the detection of the power of different frequency points, and the accuracy of the fitted power in the input detection of the RF detection is improved through the quadratic fitting algorithm. Compared with the prior art, the error brought by the power meter is eliminated through the first fitting, more accurate power is provided for the second fitting of the non-calibration frequency point, the redundancy rate cannot be increased through inquiring the calibration table, and the response time cannot be increased too much.
Drawings
FIG. 1 is a schematic diagram of calibration of a detection module of a quadratic fitting processing system for reducing detection power error for an RF detection module according to the present invention.
FIG. 2 is a schematic flow chart of a quadratic fitting processing method for reducing the detection power error of the RF detection module according to the present invention.
Detailed Description
In order to more clearly describe the technical contents of the present invention, the following further description is given in conjunction with specific embodiments.
The quadratic fitting processing method for reducing the detection power error aiming at the RF detection module comprises the following steps:
(1) performing linear fitting on the power data of the calibration voltage points, and eliminating power errors of adjacent voltage points of the same calibration frequency point;
(2) and performing fitting calculation on two adjacent calibration point values of the non-calibration frequency points to obtain power data.
As a preferred embodiment of the present invention, the step (1) specifically comprises the following steps:
(1.1) judging whether the current voltage PowInV is in a voltage range of the detector, namely judging whether a is more than the current voltage PowInV and less than f, wherein the voltage range of the detector is [ a, f ], and if so, continuing the step (1.2); otherwise, calculating corresponding power values under the conditions that the current voltage PowInV is less than a and the current voltage PowInV is greater than f;
(1.2) calculating a calibration table position interval and a voltage amount RemaindenInV exceeding a calibration voltage point;
(1.3) calculating a power value PowIndBmSim for obtaining the current voltage fitting.
As a preferred embodiment of the present invention, the step (1.2) of calculating the calibration table position interval specifically includes:
the calibration table position interval is calculated according to the following formula:
wherein PowInV is the current voltage, StartPowInV is the starting voltage falling within the range, Step is the interval of the voltage range, and add is the cumulative number.
As a preferred embodiment of the present invention, the step (1.2) of calculating the voltage amount RemainderInV exceeding the calibration voltage point specifically includes:
calculating the voltage amount RemainderInV beyond the calibration voltage point according to the following formula:
RemainderInV＝PowInV-StartPowInV-(interval-add)×Step；
wherein PowInV is the current voltage, StartPowInV is the initial voltage falling in the range, Step is the interval of the voltage range, add is the cumulative number, and interval is the position of the calibration table.
As a preferred embodiment of the present invention, the step (1.3) of calculating the power value powdndbmsmim for obtaining the current voltage fitting specifically includes:
calculating a power value PowIndBmSim for obtaining current voltage fitting according to the following formula:
PowIndBm1＝CaliForm[freqLocation][interval－1]；
PowIndBm2＝CaliForm[freqLocation][interval]；
wherein Freqlocation is a calibration frequency point, interval is a voltage interval, RemainderInV is a voltage amount exceeding the calibration voltage point, Step is an interval of a voltage range, and PowIndBm1 and PowIndBm2 are power values obtained according to the two-dimensional array respectively.
As a preferred embodiment of the present invention, the step (2) specifically comprises the following steps:
(2.1) if the set frequency point is a calibration frequency point, calculating a power value PowIndBmSim corresponding to the voltage; if the set frequency point is not on the calibration frequency point and the frequency point is between the calibration points F0 and F1, wherein F0 < F1, continuing the step (2.2);
(2.2) obtaining a voltage power value PowIndBmSim1 corresponding to the frequency point F0 and a voltage power value PowIndBmSim2 corresponding to the frequency point F1;
and (2.3) carrying out linear fitting to obtain a power value corresponding to the voltage under the current frequency.
As a preferred embodiment of the present invention, the step (2.3) of calculating the power value corresponding to the voltage specifically includes:
and calculating the power value corresponding to the voltage according to the following formula:
the PowIndBmSim1 is a voltage power value corresponding to the frequency point F0, the PowIndBmSim2 is a voltage power value corresponding to the frequency point F1, and Freq is a frequency value.
The quadratic fitting processing system for reducing the detection power error aiming at the RF detection module comprises a power divider, a detection module and a power meter, wherein the input end of the power divider is connected with a signal source, one end of the output end of the power divider is connected with the detection module, the other end of the output end of the power divider is connected with the power meter, and the detection module calibrates signals output by the signal source.
The quadratic fit processing device for reducing detection power error for the RF detection module of the invention comprises:
a processor configured to execute computer-executable instructions;
a memory storing one or more computer-executable instructions that, when executed by the processor, perform the steps of the above-described quadratic fit processing method for an RF detection module that reduces detection power errors.
The processor for implementing the quadratic fit process for reducing the detection power error for the RF detection module of the present invention is configured to execute computer executable instructions, and when the computer executable instructions are executed by the processor, the processor implements the steps of the quadratic fit process for reducing the detection power error for the RF detection module as described above.
The computer readable storage medium of the present invention has stored therein a computer program executable by a processor to implement the steps of the above-described quadratic fit processing method for reducing detection power error for an RF detection module.
In an embodiment of the present invention, a quadratic fit algorithm for reducing detection power error by an RF detection module is provided. The technical scheme adopted by the scheme is that linear fitting is firstly carried out on power data of a calibration voltage point, power errors of adjacent voltage points of the same calibration frequency point are eliminated, then secondary utilization is carried out on the data of the calibration frequency point, fitting calculation is carried out on values of two adjacent calibration points of non-calibration points, and therefore ideal power is obtained.
As shown in fig. 1, the detection module uses the signal source output signal for calibration, and after passing through the power divider, one end is connected to the power meter, and the other end is connected to the detection module. As shown in Table 1, the frequencies to be calibrated are x-y MHz, and the intervals of the calibration frequency points are z MHz. As shown in table 2, the voltage range of the detector in the detection module is [ a, f ], and the interval of each voltage calibration range is Kn.
TABLE 1 calibration frequency points and intervals
| Calibration frequency range (Unit: MHz) | Frequency point interval (Unit: MHz) |
| [x,y] | z |
TABLE 2 calibration Voltage Range and Interval
| Voltage Range (Unit: V) | Interval (Unit: V) |
| [a,b) | K1 |
| [b,c) | K2 |
| [c,d) | K3 |
| [d,e) | K4 |
| [e,f] | K5 |
After calibration, data was recorded in a two-dimensional array with CaliForm [ Freqlocation ] [ interval ] float type array [ cal1] [ cal2 ].
Wherein the content of the first and second substances,
FreqLocation＝(y－x)/z+1＝cal1；
interval＝(b－a)/K1+(c－b)/K2+(d－c)/K3+(e－d)/K4+(f－e)/K5+1＝cal2；
wherein Freqlocation is a calibration frequency point, interval is a voltage interval, and corresponding parameters in the two-dimensional array represent power values in dBm.
Step 1: fitting of calibration voltage points:
and judging the voltage range, recording the current voltage as PowInV, recording the starting voltage falling into the range as StartPowInV, and recording the interval of the range as Step.
When PowInV < a,
PowIndBm＝CaliForm[freqLocation][0]；
when the PowInV > f is present,
PowIndBm＝CaliForm[freqLocation][cal2]；
when a is less than PowInV and less than f, the calculation formula of the calibration table position interval is as follows:
the voltage amount exceeding the calibration voltage point is recorded as RemaindenInV, and the calculation formula is as follows:
RemainderInV＝PowInV-StartPowInV-(interval-add)×Step；
wherein, the floor in the interval calculation formula is the floor function in the C language; add is the cumulative number, with specific values obtained according to table 3 below.
TABLE 3 Add value Table
Two power values are obtained according to the above:
PowIndBm1＝CaliForm[freqLocation][interval－1]；
PowIndBm2＝CaliForm[freqLocation][interval]；
obtaining a power value fitted by the current voltage:
step 2: fitting of non-calibrated frequency points:
when the set frequency point is a calibration frequency point, the power value corresponding to the voltage is PowIndBmSim;
when the frequency is not on the calibration frequency point, suppose the frequency point is between calibration points F0 and F1 (F0 < F1);
taking out a power value PowIndBmSim1 of a corresponding calibration table, wherein the frequency point is F0 and the voltage is; taking out a power value PowIndBmSim2 of a corresponding calibration table, wherein the frequency point is F1 and the voltage is;
the calculation formula for linearly fitting the power corresponding to the voltage at the current frequency is as follows:
the secondary fitting of the RF detection module for reducing the detection error power is realized through the above mode.
For a specific implementation of this embodiment, reference may be made to the relevant description in the above embodiments, which is not described herein again.
It is understood that the same or similar parts in the above embodiments may be mutually referred to, and the same or similar parts in other embodiments may be referred to for the content which is not described in detail in some embodiments.
It should be noted that the terms "first," "second," and the like in the description of the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Further, in the description of the present invention, the meaning of "a plurality" means at least two unless otherwise specified.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by suitable instruction execution devices. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, and the corresponding program may be stored in a computer readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a separate product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
By adopting the quadratic fitting processing method, the system, the device, the processor and the computer readable storage medium for reducing the detection power error aiming at the RF detection module, the errors generated in calibration and caused by non-calibrated frequency points are eliminated in the detection of the power of different frequency points, and the accuracy of the fitted power in the input detection of the RF detection is improved through the quadratic fitting algorithm. Compared with the prior art, the error brought by the power meter is eliminated through the first fitting, more accurate power is provided for the second fitting of the non-calibration frequency point, the redundancy rate cannot be increased through inquiring the calibration table, and the response time cannot be increased too much.
In this specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (11)
1. A quadratic fit processing method for reducing detection power error aiming at an RF detection module is characterized by comprising the following steps:
(1) performing linear fitting on the power data of the calibration voltage points, and eliminating power errors of adjacent voltage points of the same calibration frequency point;
(2) and performing fitting calculation on two adjacent calibration point values of the non-calibration frequency points to obtain power data.
2. The method according to claim 1, wherein the step (1) specifically comprises the following steps:
(1.1) judging whether the current voltage PowInV is in a voltage range of the detector, namely judging whether a is more than the current voltage PowInV and less than f, wherein the voltage range of the detector is [ a, f ], and if so, continuing the step (1.2); otherwise, calculating corresponding power values under the conditions that the current voltage PowInV is less than a and the current voltage PowInV is greater than f;
(1.2) calculating a calibration table position interval and a voltage amount RemaindenInV exceeding a calibration voltage point;
(1.3) calculating a power value PowIndBmSim for obtaining the current voltage fitting.
3. The method of claim 2, wherein the step (1.2) of calculating the inter-calibration value is specifically:
the calibration table position interval is calculated according to the following formula:
wherein PowInV is the current voltage, StartPowInV is the starting voltage falling within the range, Step is the interval of the voltage range, and add is the cumulative number.
4. The method of claim 2, wherein the step (1.2) of calculating the amount of voltage beyond the calibration voltage point, RemainderInV, is performed by:
calculating the voltage amount RemainderInV beyond the calibration voltage point according to the following formula:
RemainderInV＝PowInV-StartPowInV-(interval-add)×Step；
wherein PowInV is the current voltage, StartPowInV is the initial voltage falling in the range, Step is the interval of the voltage range, add is the cumulative number, and interval is the position of the calibration table.
5. The method according to claim 2, wherein the step (1.3) of calculating the power value powdndbmsmim for obtaining the current voltage fit includes:
calculating a power value PowIndBmSim for obtaining current voltage fitting according to the following formula:
PowIndBm1＝CaliForm[freqLocation][interval－1]；
PowIndBm2＝CaliForm[freqLocation][interval]；
wherein Freqlocation is a calibration frequency point, interval is a voltage interval, RemainderInV is a voltage amount exceeding the calibration voltage point, Step is an interval of a voltage range, and PowIndBm1 and PowIndBm2 are power values obtained according to the two-dimensional array respectively.
6. The method according to claim 1, wherein the step (2) specifically comprises the following steps:
(2.1) if the set frequency point is a calibration frequency point, calculating a power value PowIndBmSim corresponding to the voltage; if the set frequency point is not on the calibration frequency point and the frequency point is between the calibration points F0 and F1, wherein F0 < F1, continuing the step (2.2);
(2.2) obtaining a voltage power value PowIndBmSim1 corresponding to the frequency point F0 and a voltage power value PowIndBmSim2 corresponding to the frequency point F1;
and (2.3) carrying out linear fitting to obtain a power value corresponding to the voltage under the current frequency.
7. The method according to claim 6, wherein the step (2.3) of calculating the power value corresponding to the voltage includes:
and calculating the power value corresponding to the voltage according to the following formula:
the PowIndBmSim1 is a voltage power value corresponding to the frequency point F0, the PowIndBmSim2 is a voltage power value corresponding to the frequency point F1, and Freq is a frequency value.
8. The quadratic fitting processing system for reducing the detection power error aiming at the RF detection module is characterized by comprising a power divider, a detection module and a power meter, wherein the input end of the power divider is connected with a signal source, one end of the output end of the power divider is connected with the detection module, the other end of the output end of the power divider is connected with the power meter, and the detection module calibrates a signal output by the signal source.
9. A quadratic fit processing apparatus for reducing detection power error for an RF detection module, the apparatus comprising:
a processor configured to execute computer-executable instructions;
a memory storing one or more computer-executable instructions that, when executed by the processor, perform the steps of any of claims 1 to 7 for a method of implementing a quadratic fit process for an RF detection module that reduces detection power errors.
10. A processor for implementing a quadratic fit process for reducing detection power errors for an RF detection module, wherein the processor is configured to execute computer executable instructions which, when executed by the processor, implement the steps of the quadratic fit process for reducing detection power errors for an RF detection module of any of claims 1 to 7.
11. A computer-readable storage medium having stored thereon a computer program executable by a processor to perform the steps of the method for RF detection module quadratic fit reduction of detected power error of any of claims 1 to 7.
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