CN114400252A - A Cold Metal-Based Negative Differential Resistance MOSFET - Google Patents

Abstract

The present invention relates to a negative differential resistance MOSFET tube based on cold metal, which comprises an upper gate dielectric layer, a lower gate dielectric layer, an upper layer electrode and a lower layer electrode arranged on the gate dielectric layer, and a source electrode, a drain electrode and a channel are arranged Between the upper gate dielectric layer and the lower gate dielectric layer, the source is a cold metal material. Therefore, the present invention has the following advantages: 1. The present invention uses "cold" metal as the source of the MOSFET, and the unique band gap structure of the "cold" metal source enables it to achieve excellent NDR performance. At the same time, high mobility semiconductors ensure that they can generate large peak currents. In addition, adjusting the gate voltage of the MOSFET can also effectively control the peak current and the current peak-to-valley ratio of the MOSFET. 2. The present invention can improve the noise tolerance of the device and the output power of the NDR device, thereby improving the stability of the negative resistance oscillator.

Description

A Cold Metal-Based Negative Differential Resistance MOSFET

technical field

The invention relates to a negative differential resistance MOSFET, in particular to a cold metal-based negative differential resistance MOSFET.

Background technique

Existing NDR devices, such as tunnel diodes and resonant tunnel diodes, conduct conduction based on the electron tunneling effect, so the peak current is small. When it is applied to an oscillation circuit, it is difficult to maintain the stability of the oscillation circuit. In addition, the small peak current and current peak-to-valley ratio also limit the noise tolerance of NDR devices, and it is difficult for NDR devices to continue to maintain their negative resistance characteristics when the noise is large.

SUMMARY OF THE INVENTION

The invention mainly solves the technical problems existing in the prior art, and provides a "cold" metal with a band gap near the Fermi level as the source of the MOSFET to realize the NDR effect. The unique bandgap structure of the "cold" metal source enables excellent NDR performance. At the same time, the high mobility of the semiconductor material also ensures that the MOSFET can generate extremely high peak currents. In addition, the peak current and current peak-to-valley ratio of the MOSFET can also be effectively regulated by adjusting the gate voltage V _GS of the MOSFET.

Aiming at the defects of small peak current and output power of the tunnel diode, the invention adopts a MOSFET with a "cold" metal source to realize the NDR effect. The unique bandgap structure of the "cold" metal source enables excellent NDR performance. At the same time, the high mobility of the semiconductor ensures that the MOSFET can generate extremely high peak currents. In negative resistance oscillators, the larger peak current enables the MOSFET to provide greater output power, ensuring that the oscillator circuit starts and continues to oscillate. In addition, in the presence of noise in the circuit, the larger peak current and current peak-to-valley ratio also have a higher noise margin, thus maintaining the negative resistance characteristics of the device.

The above-mentioned technical problems of the present invention are mainly solved by the following technical solutions:

A negative differential resistance MOSFET tube based on cold metal, which is characterized in that it comprises an upper gate dielectric layer, a lower gate dielectric layer, an upper layer electrode and a lower layer electrode disposed on the gate dielectric layer, a source electrode, a drain electrode and a channel. It is arranged between the upper gate dielectric layer and the lower gate dielectric layer, and the source is made of a cold metal material.

In the above-mentioned cold metal-based negative differential resistance MOSFET, the channel is an intrinsic semiconductor material, and the drain is a p-type doped semiconductor material.

In the above-mentioned cold metal-based negative differential resistance MOSFET, the drain is p-type heavily doped monolayer MoS ₂ .

In the above-mentioned cold metal-based negative differential resistance MOSFET, the channel is a single-layer MoS ₂ .

In the above-mentioned cold metal-based negative differential resistance MOSFET, the drain is a single material, and any one of NbSe ₂ or TaSe ₂ is used.

In the above-mentioned cold metal-based negative differential resistance MOSFET tube, the upper layer electrode and the lower layer electrode are both copper electrodes.

In the above-mentioned cold metal-based negative differential resistance MOSFET, the upper gate dielectric layer and the lower gate dielectric layer are both SiO ₂ material substrates.

Therefore, the present invention has the following advantages: (1) The present invention is different from the existing NDR devices based on semiconductor materials, but uses "cold" metal as the source of the MOSFET, and the unique bandgap structure of the "cold" metal source makes the It can achieve excellent NDR performance. At the same time, high mobility semiconductors ensure that they can generate large peak currents. In addition, adjusting the gate voltage V _GS of the MOSFET can also effectively control the peak current and the current peak-to-valley ratio of the MOSFET.

(2) The "cold" metal source MOSFETs of the present invention are capable of generating extremely large current peak-to-valley ratios and peak currents simultaneously. On the one hand, the larger current peak-to-valley ratio and peak current can improve the noise tolerance of the device, and on the other hand, the higher peak current improves the output power of the NDR device, thereby improving the stability of the negative resistance oscillator.

Description of drawings

Accompanying drawing 1 is a kind of principle diagram of the present invention;

Figure 2a is a current-voltage curve diagram of a typical negative differential resistance device.

Figure 2b is a band alignment diagram at bias voltage V _b =V ₀ .

Figure 2c is a band alignment diagram at bias voltage V _b =V ₁ .

Figure 2d is a band alignment diagram at bias voltage V _b =V ₂ .

Figure 2e is a band alignment diagram at bias voltage _Vb = _V3 .

Where V _DS corresponds to V ₀ to V ₃ , as shown in (a). The dotted line and the corresponding _εS and _εD represent the Fermi levels of the source and drain, respectively. The white area in ₍ be) corresponds to the band gap of the "cold" metal and MoS2 material, the size of the black arrow represents the magnitude of the current at this bias voltage, and the gray area under the dashed line represents the energy level below the Fermi level that is completely filled by electrons filling. The solid spheres represent electrons and the hollow spheres represent holes. The number of carriers represents the change in carrier concentration for different bias voltages.

Detailed ways

The technical solutions of the present invention will be further described in detail below through examples and in conjunction with the accompanying drawings.

Example:

The "cold" metals used in the present invention are distinct from ordinary metallic materials possessing a continuous density of states. "Cold" metals have a conduction band gap ( _{ECG) above the Fermi level or a valence band gap (EVG )} below the Fermi level. Therefore, the present invention realizes a type III band-aligned heterojunction NDR device through the heterojunction of "cold" metal and high mobility semiconductor.

In Figure 1, a "cold" metal-semiconductor-constructed heterojunction with E _VG is used as an example to analyze its NDR mechanism. The source in Figure 1 is a "cold" metallic material with E _VG , and the channel and drain are intrinsic and p-type doped semiconductor materials, respectively. The bandgap of the semiconductor is moved above the Fermi level by the modulation of _VGS . I-IV represent band alignment diagrams at various bias voltages (V _DS ). Different from the traditional type III energy band-aligned semiconductor heterojunction, the "cold" metal heterojunction MOSFET of the present invention has a wider carrier transmission path in the channel, which is beneficial to achieve larger peak current and current peak-to-valley ratio . When the bias voltage V _DS =V ₁ , the transport width of carriers between the Fermi level (ε _D ) of the drain and the valence band top (VBM) of the semiconductor reaches the maximum value, and the current reaches the peak value. When the bias voltage V _DS = V ₂ , the current decreases and reaches the valley point due to the band gap overlap of the "cold" metal and semiconductor hindering carrier transport. When the bias voltage V _DS = V ₃ , a transport path for holes appears under the VBM of the semiconductor, and the current starts to rise again. The results show that the width of the carrier transport path between ε _D and VBM is the key factor determining the magnitude of the peak current. Since _VGS is inversely proportional to the width of the transmission path, the peak current is inversely proportional to _VGS . For the current peak-to-valley ratio, as _VGS decreases, a larger _VDS is required to move the semiconductor's bandgap so that it overlaps the source's bandgap. This results in that the ε _D at the current valley point is closer to the VBM of the source, which makes the hole transport efficiency through the semiconductor VBM higher, and the valley current and current peak-to-valley ratio become larger. Therefore, the current peak-to-valley ratio is proportional to _VGS .

Figure 1. Band alignment plots at different bias voltages (V _DS ). _εS and _εD are the Fermi levels of the source and drain, respectively. The width of the red arrow indicates the magnitude of the current. The pink part of the figure is the band gap of "cold" metal and semiconductor materials.

Unlike existing heavily doped tunnel diodes or semiconductor heterojunctions with band-aligned type III, the present invention uses a "cold" metal with a band gap near the Fermi level to construct a "cold" metal source MOSFET. Due to the unique bandgap structure of the "cold" metal source, it can achieve excellent NDR performance. At the same time, high mobility semiconductors ensure that they can generate large peak currents. In addition, adjusting the V _GS of the MOSFET can also effectively control the peak current and the current peak-to-valley ratio of the MOSFET.

The specific embodiments described herein are merely illustrative of the spirit of the invention. Those skilled in the art to which the present invention pertains can make various modifications or additions to the described specific embodiments or substitute in similar manners, but will not deviate from the spirit of the present invention or go beyond the definition of the appended claims range.

Claims (7)

1. A negative differential resistance MOSFET based on cold metal is characterized by comprising an upper gate dielectric layer, a lower gate dielectric layer, an upper grid electrode and a lower grid electrode, wherein the upper grid electrode and the lower grid electrode are arranged on the gate dielectric layer, a source electrode, a drain electrode and a channel are arranged between the upper grid dielectric layer and the lower grid dielectric layer, and the source electrode is made of cold metal.

2. The cold metal based negative differential resistance MOSFET of claim 1 wherein the channel is intrinsic semiconductor material and the drain is p-type doped semiconductor material.

3. The cold metal based negative differential resistance MOSFET of claim 1, wherein the drain is a heavily p-doped single layer MoS₂。

4. The cold metal based NDR MOSFET of claim 1, wherein said trench is a single layer MoS₂。

5. The cold metal-based NDR MOSFET of claim 1, wherein the drain is made of elemental material (NbSe)₂Or TaSe₂Any one of them.

6. The cold metal-based negative differential resistance MOSFET of claim 1, wherein the upper and lower gate electrodes are copper electrodes.

7. The cold metal-based negative differential resistance MOSFET of claim 1, wherein the upper gate dielectric layer and the lower gate dielectric layer are both SiO₂A material substrate.

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