CN114398013B - NAND memory security code generation module, generation method and NAND memory - Google Patents

NAND memory security code generation module, generation method and NAND memory Download PDF

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Publication number
CN114398013B
CN114398013B CN202210093628.5A CN202210093628A CN114398013B CN 114398013 B CN114398013 B CN 114398013B CN 202210093628 A CN202210093628 A CN 202210093628A CN 114398013 B CN114398013 B CN 114398013B
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information
nand memory
crc code
cam
register value
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CN114398013A (en
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李炯尚
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Dongxin Semiconductor Co ltd
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Dongxin Semiconductor Co ltd
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Priority to PCT/CN2022/124444 priority patent/WO2023142523A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

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  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Storage Device Security (AREA)

Abstract

The invention provides a NAND memory security code generation module and a generation method, and a NAND memory with the NAND memory security code generation module, wherein the NAND memory security code generation module comprises: a CAM information reading unit that reads CAM information in the NAND memory; a register value updating unit that updates register values corresponding to the respective CAM information with respect to the CAM information read by the CAM information reading unit; a CRC code generation unit that generates a CRC code using the register value updated by the register value update unit; and a security code storage unit that updates and stores the CRC code generated by the CRC code generation unit.

Description

NAND memory security code generation module, generation method and NAND memory
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a NAND memory security code generation module and method, and a NAND memory incorporating the NAND memory security code generation module.
Background
The NAND memory is a memory chip with large capacity, and is characterized by large capacity density, low manufacturing cost and high access speed, and is usually used as a memory chip on a U disk, a solid state disk, a memory card and other devices.
For NAND memories, security of user data is a very important topic. In order to avoid illegal user access and illegal copying, the written data is usually encrypted, while a security code for the specific user access may also be set.
In the prior art, with the continuous development of semiconductor technology, in order to make such security codes, suppliers often place special IPs with the disadvantage of a large area, for example, adopting RPMC (Replay-Protected Monotonic Counter: response protection monotonic calculator) embedded security technology.
Currently, when designing a NAND memory including an RPMC, a large-capacity NAND memory and the RPMC are generally integrated on one chip, i.e., an RPMC circuit and a NAND memory chip are designed together. However, this design method has the disadvantages that the area of a single chip is large and the packaging area is large, resulting in higher design cost, because the NAND memory and RPMC need to be integrated on one chip; and the RPMC circuit and the NAND memory are designed together, resulting in high complexity of chip design and long design period, especially when the RPMC performs an operation requiring a large number of registers (e.g., HMAC (Hash-based MessageAuthentication Code, hash operation message authentication code) operation), the large number of registers are required, which inevitably results in an excessive chip area.
Therefore, this places a great burden on manufacturing a small-sized chip and obtaining profits.
In order to solve the above problems, the present invention provides a NAND memory security code generation module and generation method, and a NAND memory incorporating the NAND memory security code generation module. By using the CAM information data in the NAND memories to generate the unique security code, each NAND memory can obtain the unique security code using the CAM information data different from each other without placing any special IP or increasing the chip size, thereby avoiding any illegal access and illegal copying of the memory, improving the data security of the NAND memories, and realizing the miniaturization of the NAND memory chip.
Disclosure of Invention
A first aspect of the present invention provides a NAND memory security code generating module, comprising:
a CAM information reading unit that reads CAM information in the NAND memory;
A register value updating unit that updates register values corresponding to the respective CAM information with respect to the CAM information read by the CAM information reading unit;
A CRC code generation unit that generates a CRC code using the register value updated by the register value update unit; and
And a security code storage unit that updates and stores the CRC code generated by the CRC code generation unit.
A second aspect of the present invention is that, in the NAND memory security code generating module related to the first aspect, the CAM information includes configuration information, repair column information, bad block information, and repair block information.
A third aspect of the present invention is the NAND memory security code generating module according to the second aspect, wherein the CAM information reading unit reads the configuration information, the repair column information, the bad block information, and the repair block information, respectively, and the CRC code generating unit finally generates the CRC code including the configuration information, the repair column information, the bad block information, and the repair block information, and sets the CRC code as a unique security code of the NAND memory.
A fourth aspect of the present invention is that, in the NAND memory security code generating module related to the second aspect, the register value updating unit updates register values corresponding to the configuration information, the repair column information, the bad block information, and the repair block information, respectively.
A fifth aspect of the present invention is the NAND memory security code generating module according to the fourth aspect, wherein the CRC code generating unit performs the following operations:
generating a first CRC code based on the register value corresponding to the configuration information updated by the register value updating unit;
Generating a second CRC code based on the register value corresponding to the repair column information updated by the register value updating unit and the first CRC code;
Generating a third CRC code based on the register value corresponding to the bad block information updated by the register value updating unit and the second CRC code;
Generating a fourth CRC code based on the register value corresponding to the repair block information updated by the register value updating unit and the third CRC code,
The fourth CRC code is set to be a unique security code of the NAND memory.
A sixth aspect of the present invention is the NAND memory security code generating module related to the second aspect, wherein the CAM information further includes OPT protection information and block protection information.
A seventh aspect of the present invention is the NAND memory security code generating module related to the first aspect, wherein the CAM information reading unit performs the CAM information reading every time the NAND memory is reset.
An eighth aspect of the present invention is to provide a NAND memory security code generating method, wherein the following steps are performed every time the NAND memory is reset by power on:
A CAM information data reading step of reading a plurality of CAM information data in the NAND memory, respectively;
A register value updating step of updating register values corresponding to the read CAM information data, respectively;
A CRC code generation step of generating a CRC code using the updated register value; and
And a CRC code storage step of updating and storing the generated CRC code.
A ninth aspect of the present invention is that, in the NAND memory security code generating method relating to the eighth aspect, the plurality of CAM information data are configuration information, repair column information, bad block information, and repair block information.
A tenth aspect of the present invention is the NAND memory security code generating method according to the ninth aspect, wherein in the CRC code generating step, the CRC code including the configuration information, the repair column information, the bad block information, and the repair block information is finally generated and set as a unique security code of the NAND memory.
An eleventh aspect of the present invention is to provide a NAND memory characterized by comprising the NAND memory security code generating module of any one of the first to seventh aspects.
Drawings
Fig. 1 is a block diagram showing a NAND memory security code generation module according to embodiment 1 of the present invention.
Fig. 2 is a flowchart showing an operation of the CAM information reading unit according to embodiment 1 of the present invention for reading various CAM information in the NAND memory.
Fig. 3 is a flowchart showing an operation of the CRC code generation unit according to embodiment 1 of the present invention to generate a unique security code.
Fig. 4 is a flowchart showing a NAND memory security code generation method according to embodiment 2 of the present invention.
Fig. 5 is a flowchart showing a method for unlocking a NAND memory having a NAND memory security code generating module incorporated therein according to embodiment 3 of the present invention.
Detailed Description
The invention will be described in more detail hereinafter with reference to specific embodiments shown in the drawings. The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods according to embodiments of the present invention. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures.
Furthermore, various advantages and benefits of the present invention will become apparent to those of ordinary skill in the art upon reading the following detailed description of the specific embodiments. It should be understood, however, that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. The following embodiments are provided to enable a more thorough understanding of the present invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.
Embodiment 1
Inside the NAND, there is unique information called "CAM information". The CAM information includes configuration information (Configuration information), repair column information (Repair column information), bad block information (Bad block information), and repair block information (Repair block information).
Wherein the configuration information includes: special trimming data such as band gap trimming (BandGap trim), OSC trimming, PUMP OSC trimming, etc.; P/E enable voltage, VPASS voltage, VREAD voltage, program verify voltage (Program verify voltage), selected read voltage (SELECTED READ voltage), etc.; as well as other configuration register data. The repair column information includes repair column address information for the failed column. The bad block information includes bad block address information for the failed block. The repair block information includes repair block address information for the failed block.
The CAM information includes other specific information such as OPT protection, block protection, and the like.
The inventors have found that CAM information data are different from each other in each of different NAND memory chips. Specifically, regarding the configuration information, the specific trimming data such as the band gap trimming, the OSC trimming, the PUMP OSC trimming, etc. may be different for each different NAND memory chip, and the P/E start-up voltage may be different. Regarding repair column information, bad block information, and repair block information, these information are necessarily different for each different NAND memory chip. This is because the different NAND memory chips have different defects and are unlikely to be identical to each other.
In case of using CAM information data different in each NAND memory chip, a unique security code can be generated on each NAND memory chip without placing a special IP having a disadvantage of a large area to avoid illegal access and illegal copying.
In view of this, in embodiment 1 of the present invention, there is provided a NAND memory security code generating module that generates a unique security code by using CAM information data in a NAND memory. The NAND memory security code generation module according to embodiment 1 of the present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a block diagram showing a NAND memory security code generation module 100 according to embodiment 1 of the present invention.
As shown in fig. 1, the NAND memory security code generation module 100 according to embodiment 1 includes a CAM information reading unit 101, a register value updating unit 102, a CRC code generation unit 103, and a security code storage unit 104.
The CAM information reading unit 101 reads various CAM information in the NAND memory, such as configuration information, repair column information, bad block information, repair block information, and the like. In some embodiments, the CAM information further includes OPT protection, block protection, etc. information.
The register value updating unit 102 updates each register value corresponding to the CAM information read by the CAM information reading unit 101. For example, after reading the configuration information, the register value updating unit 102 updates the CNF register value for the configuration information; after the repair column information is read, updating the repair column register value according to the repair column information; after the bad block information is read, updating a bad block register value according to the bad block information; and updating the repair block register value for the repair block information after reading the repair block information. In addition, in some embodiments, the register value updating unit 102 may also update the register value related to the information such as OPT protection, block protection, and the like.
The CRC code generation unit generates a CRC code based on a CRC (cyclic redundancy code) algorithm using the register value updated by the register value update unit 102.
The CRC code generated by the CRC code generation unit is finally updated and stored in the security code storage unit 104, which is a 32-bit register, for example, for access only by a specific user.
When the CAM information reading unit 101 has completed reading all the CAM information, the CRC code stored in the security code storage unit 104 at this time is set as the unique security code of the NAND memory.
The operation of each of the above units will be described in detail in order.
Fig. 2 is a flowchart showing an operation of the CAM information reading unit 101 according to embodiment 1 of the present invention for reading various CAM information in the NAND memory.
As shown in fig. 2, after the NAND memory is power-on reset (POR), in step S101, the CAM information reading unit 101 is activated to start reading of various CAM information data.
In step S102, the CAM information reading unit 101 first reads configuration information in CAM information data. Then in step S103, the CNF register value is updated by the register value updating unit 102 for the configuration information obtained by reading.
After the update of the CNF register value is completed, in step S104, the CAM information reading unit 101 reads the repair column information in the CAM information data. Then in step S105, the repair column register value is updated by the register value updating unit 102 for the repair column information obtained by reading.
After the completion of updating the repair column register value, in step S106, the CAM information reading unit 101 reads bad block information in the CAM information data. Then in step S107, the bad block register value is updated by the register value updating unit 102 for the read obtained bad block information.
After the update of the bad block register value is completed, in step S108, the CAM information reading unit 101 reads the repair block information in the CAM information data. Then in step S109, the repair block register value is updated by the register value updating unit 102 for the repair block information obtained by reading.
To this end, the CAM information data reading by the CAM information reading unit 101 is completed.
In some embodiments, in the case where information such as OPT protection and block protection is also included in the CAM information, the CAM information reading unit 101 reads these information data as well, and the register value updating unit 102 updates the relevant register value with respect to the read CAM information data.
Fig. 3 is a flowchart showing an operation of CRC code generation section 103 according to embodiment 1 of the present invention to generate a unique security code.
In step S201, the CRC Code generation unit 103 generates a first CRC Code, which is denoted as crc_code_0<31:0>, using a CRC algorithm based on the configuration information read by the CAM information reading unit 101.
Specifically, after the update of the CNF register values is completed by the register value updating unit 102 for the configuration information obtained in step S102 in step S103, the CRC code generating unit 103 generates a first CRC code based on the first reading of the CAM information data, that is, the reading of the configuration information, using all the CNF register values. The first CRC code contains the result of the first reading of the CAM information data, i.e., contains the configuration information data in the CAM information data. Then, the generated first CRC Code crc_code_0<31:0> is stored in the security Code storage unit 104.
Next, in step S202, the CRC Code generation unit 103 generates a second CRC Code, which is denoted as crc_code_1<31:0>, using a CRC algorithm based on the repair column information read by the CAM information reading unit 101 and the first CRC Code generated in step S201.
Specifically, after the update of the repair column register value is completed by the register value updating unit 102 for the repair column information read in step S104 in step S105, the CRC code generating unit 103 generates a second CRC code based on the first read and the second read of the CAM information data using all the repair column register values and the first CRC code generated in step S201. The second CRC code includes configuration information data, which is a result of first reading CAM information data, and repair column information data, which is a result of second reading CAM information data. Then, the generated second CRC Code crc_code_1<31:0> is updated and stored in the security Code storage unit 104.
Next, in step S203, the CRC Code generation unit 103 generates a third CRC Code, which is denoted as crc_code_2<31:0>, using a CRC algorithm based on the bad block information read by the CAM information reading unit 101 and the second CRC Code generated in step S202.
Specifically, after the update of the bad block register value is completed by the register value updating unit 102 for the bad block information obtained in step S106 in step S107, the CRC code generating unit 103 generates a third CRC code based on the first, second, and third reads of the CAM information data using all the bad block register values and the second CRC code generated in step S202. The third CRC code comprises configuration information data which is the result of first reading CAM information data; the result of the second reading of the CAM information data, i.e. repair column information data; and bad block information data, which is the result of the third reading of CAM information data. Then, the generated third CRC Code crc_code_2<31:0> is updated and stored in the security Code storage unit 104.
Finally, in step S204, similarly, the CRC Code generation unit 103 generates a fourth CRC Code, which is denoted as crc_code_3<31:0>, using the CRC algorithm based on the repair block information read by the CAM information reading unit 101 and the third CRC Code generated in step S203.
Specifically, after the update of the repair block register value is completed by the register value updating unit 102 for the repair block information obtained in step S108 in step S109, the CRC code generating unit 103 generates a fourth CRC code based on the first, second, third, and fourth reads of the CAM information data using all the repair block register values and the third CRC code generated in step S203. The fourth CRC code contains configuration information data which is the result of first reading of CAM information data; the result of the second reading of the CAM information data, i.e. repair column information data; the result of the third reading of the CAM information data, namely bad block information data; and repair block information, which is the result of the fourth reading of CAM information data. Then, the generated fourth CRC Code crc_code_3 is updated and stored in the security Code storage unit 104. The fourth CRC Code CRC_Code_3<31:0> is the final and unique CRC Code generated based on all CAM information data.
Regarding the generated CRC code, for example, CRC-32-IEEE 802.3 based implementation is performed in the following manner:
polynomials (Polynomial) x32+ x26+ x23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x1
Data input (Data input) 8bits
Initial value (Initial value) 0xA5A5A5A5 (failure of capture, even if the data is all "1" or all "0")
Convention that the first serial data bit is D (7) (MSB)
The above-described CRC code implementation is merely an example, and other methods known in the art may be employed as long as the CRC code can be generated based on the CAM information data.
After all CAM information data are read, the fourth CRC Code crc_code_3<31:0> finally generated by the CRC Code generation unit 103 is updated and stored in the security Code storage unit 104, and the fourth CRC Code crc_code_3<31:0> is set as the final unique security Code for access by a special user. The security code storage unit 104 is set to, for example, a 32-bit register, but is not limited thereto.
In some embodiments, when information such as OPT protection and block protection is further included in the CAM information, the CRC code generation section 103 may similarly generate a final CRC code and update and store the final CRC code in the security code storage section 104 in the same manner as described above. The CRC code here is a final and unique CRC code generated based on all CAM information data including information such as OPT protection and block protection.
So far, after a power-on reset (POR) phase, the NAND memory can obtain a unique security code of 32 bits through a series of processes. The unique security code is accessible to the particular user.
In addition, the above embodiment 1 shows an example in which the configuration information, the repair column information, the bad block information, the repair block information, and the like in the CAM information data are sequentially read, but the order of reading is not limited thereto. All CAM information data may be read in any manner and order as long as it can be read and a unique CRC code containing the CAM information data is generated.
By adopting the NAND memory security code generation module according to embodiment 1, the unique security code is generated by using the CAM information data in the NAND memory, so that each NAND memory can obtain the unique security code using the CAM information data different from each other, without placing any special IP, without increasing the chip size, and further, the memory can be prevented from being illegally accessed and illegally copied. The miniaturization of the NAND memory chip is realized while improving the data security of the NAND memory.
Embodiment 2
Fig. 4 is a flowchart showing a NAND memory security code generation method according to embodiment 2 of the present invention. Next, a NAND memory security code generation method according to embodiment 2 of the present invention will be described with reference to fig. 4. In the following description, the same parts as those of embodiment 1 are omitted, and the description thereof will be omitted.
As shown in fig. 4, first the NAND memory chip is powered up reset (POR).
Next, in step S301, CAM information data including, but not limited to, configuration information, repair column information, bad block information, and repair block information is read by the CAM information reading unit 101, and then proceeds to step S302.
In step S302, the register value updating unit 102 updates the register value corresponding to the read CAM information data, and then proceeds to step S303.
In step S303, the CRC code generation unit 103 generates a CRC code using the updated register value, and then proceeds to step S304.
In step S304, the generated CRC code is updated and stored in the security code storage unit 104.
Next, in step S305, it is determined whether all CAM information data has been read. If it is determined that all the CAM information data has been read, the CRC code stored in the security code storage unit 104 is set as the final unique security code. If it is determined that all the CAM information data has not been read, the routine returns to step S301, and steps S301 to S305 are repeated until all the CAM information data has been read.
In embodiment 2, by generating a unique security code using CAM information data in NAND memories, each NAND memory can obtain a unique security code using CAM information data different from each other, without placing any special IP and without increasing the chip size, and thus can avoid any illegal access and illegal copying of the memory, and can realize miniaturization of the NAND memory chip while improving the data security of the NAND memory.
Embodiment 3
Fig. 5 is a flowchart showing a method for unlocking a NAND memory in which the NAND memory security code generating module 100 according to embodiment 3 of the present invention is incorporated.
The NAND memory according to embodiment 3 has a NAND memory security code generation module 100 incorporated therein. Next, a method of unlocking a NAND memory in which the NAND memory security code generating module 100 is built by a user will be described with reference to fig. 5.
As shown in fig. 5, first, after the NAND memory is powered on, the NAND memory security code generation module 100 incorporated in the NAND memory reads CAM information data and generates a unique security code as described in the above-described embodiments 1 and 2.
Next, in step S401, it is determined whether the user inquires of the NAND memory about a 32-bit security code using a special command provided by the NAND memory vendor. Here, the generated unique security code is set to 32 bits, but is not limited thereto.
When it is determined in step S401 that the user has interrogated the NAND memory for a 32-bit security code using a special command provided by the NAND memory provider (yes in step S401), the flow proceeds to step S402, where the 32-bit security code is acquired from the NAND memory.
Next, in step S403, it is determined whether the user has entered a 32-bit security code. When it is determined in step S403 that the 32-bit security code is input by the user (yes in step S403), the process proceeds to step S404.
Next, in step S404, it is determined whether or not the 32-bit security code input by the user coincides with the 32-bit security code stored inside the NAND memory. When it is determined in step S404 that the 32-bit security code input by the user matches the 32-bit security code stored in the NAND memory (yes in step S404), the flow advances to step S405, and the user is granted access to the NAND memory.
When it is determined in step S401 that the user has not interrogated the NAND memory using the special command provided by the NAND memory vendor (no in step S401), or when it is determined in step S403 that the user has not entered the 32-bit security code (no in step S403), or when it is determined in step S404 that the 32-bit security code entered by the user does not coincide with the 32-bit security code stored inside the NAND memory (no in step S404), the process proceeds to step S406, the user is denied access to the NAND memory, and the NAND memory is locked regardless of any sequence subsequent to the user.
According to embodiment 3, by using the NAND memory security code generation module 100 built in the NAND memory, a unique security code can be generated using CAM information data in the NAND memory, and thus, without placing any special IP and without increasing the chip size, the memory can be prevented from being subjected to any illegal access and illegal copy, and the NAND memory chip can be miniaturized while improving the NAND memory data security.

Claims (9)

1. A NAND memory security code generation module, comprising:
a CAM information reading unit that reads CAM information in the NAND memory;
A register value updating unit that updates register values corresponding to the respective CAM information with respect to the CAM information read by the CAM information reading unit;
A CRC code generation unit that generates a CRC code using the register value updated by the register value update unit; and
A security code storage unit that updates and stores the CRC code generated by the CRC code generation unit,
Wherein the CAM information includes configuration information, repair column information, bad block information, and repair block information.
2. The NAND memory security code generation module as recited in claim 1, wherein,
The CAM information reading unit reads the configuration information, the repair column information, the bad block information, and the repair block information, respectively,
The CRC code generation unit finally generates the CRC code including the configuration information, the repair column information, the bad block information, and the repair block information, and sets the CRC code as a unique security code of the NAND memory.
3. The NAND memory security code generation module as recited in claim 1, wherein,
The register value updating unit updates register values corresponding to the configuration information, the repair column information, the bad block information, and the repair block information, respectively.
4. The NAND memory security code generation module as recited in claim 3, wherein,
The CRC code generating unit performs the following actions:
generating a first CRC code based on the register value corresponding to the configuration information updated by the register value updating unit;
Generating a second CRC code based on the register value corresponding to the repair column information updated by the register value updating unit and the first CRC code;
Generating a third CRC code based on the register value corresponding to the bad block information updated by the register value updating unit and the second CRC code;
Generating a fourth CRC code based on the register value corresponding to the repair block information updated by the register value updating unit and the third CRC code,
The fourth CRC code is set to be a unique security code of the NAND memory.
5. The NAND memory security code generation module as recited in claim 1, wherein,
The CAM information also includes OPT protection information and block protection information.
6. The NAND memory security code generation module as recited in claim 1, wherein,
The CAM information reading unit performs the CAM information reading every time the NAND memory is reset.
7. A NAND memory security code generation method, characterized in that the following steps are performed every time a NAND memory is reset by power on:
A CAM information data reading step of reading a plurality of CAM information data in the NAND memory, respectively;
A register value updating step of updating register values corresponding to the read CAM information data, respectively;
a CRC code generation step of generating a CRC code using the updated register value; and
A CRC code storage step of updating and storing the generated CRC code,
Wherein the plurality of CAM information data are configuration information data, repair column information data, bad block information data, and repair block information data.
8. The method for generating a NAND memory security code as recited in claim 7, wherein,
In the CRC code generation step, the CRC code including the configuration information, the repair column information, the bad block information, and the repair block information is finally generated and set as a unique security code of the NAND memory.
9. A NAND memory is characterized in that,
Comprising the NAND memory security code generating module of any one of claims 1 to 6.
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