CN114398013A - NAND memory security code generation module and generation method, and NAND memory - Google Patents

NAND memory security code generation module and generation method, and NAND memory Download PDF

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Publication number
CN114398013A
CN114398013A CN202210093628.5A CN202210093628A CN114398013A CN 114398013 A CN114398013 A CN 114398013A CN 202210093628 A CN202210093628 A CN 202210093628A CN 114398013 A CN114398013 A CN 114398013A
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China
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information
crc code
cam
register value
nand memory
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李炯尚
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Dongxin Semiconductor Co ltd
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Dongxin Semiconductor Co ltd
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Priority to CN202210093628.5A priority Critical patent/CN114398013A/en
Publication of CN114398013A publication Critical patent/CN114398013A/en
Priority to PCT/CN2022/124444 priority patent/WO2023142523A1/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device

Abstract

The invention provides a NAND memory security code generation module and a generation method, and a NAND memory with the NAND memory security code generation module, wherein the NAND memory security code generation module comprises: a CAM information reading unit that reads CAM information in the NAND memory; a register value updating unit that updates a register value corresponding to each of the CAM information with respect to the CAM information read by the CAM information reading unit; a CRC code generation unit that generates a CRC code using the register value updated by the register value update unit; and a security code storage unit that updates and stores the CRC code generated by the CRC code generation unit.

Description

NAND memory security code generation module and generation method, and NAND memory
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a NAND memory security code generation module, a NAND memory security code generation method, and a NAND memory having the NAND memory security code generation module built therein.
Background
The NAND memory is a large-capacity memory chip, and is characterized by large capacity density, low manufacturing cost, and fast access speed, and is usually used as a memory chip on devices such as a usb disk, a solid-state disk, and a memory card.
For NAND memories, the security of user data is an important topic. In order to avoid illegal user access and illegal copying, the written data is usually encrypted, and a security code for specific user access can be set.
In the prior art, with the continuous development of semiconductor technology, in order to make such security codes, suppliers usually place special IPs with large area defects, for example, using RPMC (relay-Protected bootnic Counter) embedded security technology.
At present, when a NAND memory containing RPMC is designed, a large-capacity NAND memory and RPMC are usually integrated on one chip, namely, an RPMC circuit and a NAND memory chip are designed together. However, the design method has the following defects that the design cost is high due to the fact that the NAND memory and the RPMC need to be integrated on one chip, and the area of the single chip is large, the packaging area is large; moreover, the RPMC circuit and the NAND memory are designed together, which results in high complexity of chip design and long design period, and especially when the RPMC performs an operation requiring a large number of registers (such as a Hash-based message authentication Code (HMAC)) operation, a large number of registers are required, which inevitably results in an excessively large chip area.
Therefore, it brings a great burden to make a small-sized chip and to obtain a profit.
In order to solve the above problems, the present invention provides a NAND memory security code generation module and generation method, and a NAND memory having the NAND memory security code generation module built therein. The unique security code is generated by using the CAM information data in the NAND memories, so that each NAND memory can obtain the unique security code by using different CAM information data without placing any special IP and increasing the chip size, the memory can be prevented from being subjected to any illegal access and illegal copy, the data security of the NAND memory is improved, and the NAND memory chip is miniaturized.
Disclosure of Invention
A first aspect of the present invention provides a NAND memory security code generation module, including:
a CAM information reading unit that reads CAM information in the NAND memory;
a register value updating unit that updates a register value corresponding to each of the CAM information with respect to the CAM information read by the CAM information reading unit;
a CRC code generation unit that generates a CRC code using the register value updated by the register value update unit; and
a security code storage unit that updates and stores the CRC code generated by the CRC code generation unit.
A second aspect of the present invention is the NAND memory security code generation module according to the first aspect, wherein the CAM information includes configuration information, repair column information, bad block information, and repair block information.
A third aspect of the present invention is the NAND memory security code generation module according to the second aspect, wherein the CAM information reading means reads the arrangement information, the repair column information, the bad block information, and the repair block information, and the CRC code generation means finally generates the CRC code including the arrangement information, the repair column information, the bad block information, and the repair block information and sets the CRC code as a unique security code of the NAND memory.
A fourth aspect of the present invention is the NAND-memory security code generation module according to the second aspect, wherein the register value update unit updates the register values corresponding to the configuration information, the repair column information, the bad block information, and the repair block information, respectively.
A fifth aspect of the present invention is the NAND memory security code generation module according to the fourth aspect, wherein the CRC code generation means performs the following operations:
generating a first CRC code based on the register value corresponding to the configuration information updated by the register value updating unit;
generating a second CRC code based on the first CRC code and the register value corresponding to the repair column information updated by the register value updating unit;
generating a third CRC code based on the register value corresponding to the bad block information updated by the register value updating unit and the second CRC code;
generating a fourth CRC code based on the register value corresponding to the repair block information updated by the register value updating unit and the third CRC code,
setting the fourth CRC code to a unique security code of the NAND memory.
A sixth aspect of the present invention is the NAND memory security code generation module according to the second aspect, wherein the CAM information further includes OPT protection information and block protection information.
A seventh aspect of the present invention is the NAND memory security code generation module according to the first aspect, wherein the CAM information reading unit reads the CAM information each time the NAND memory is powered on and reset.
An eighth aspect of the present invention is to provide a NAND memory security code generation method, wherein the following steps are performed each time the NAND memory is powered on and reset:
a CAM information data reading step of reading a plurality of CAM information data in the NAND memories, respectively;
a register value updating step of updating register values corresponding to the plurality of read CAM information data, respectively;
a CRC code generation step of generating a CRC code using the updated register value; and
and a CRC code storage step of updating and storing the generated CRC code.
A ninth aspect of the present invention is the NAND memory security code generating method according to the eighth aspect, wherein the plurality of CAM information data is arrangement information, repair column information, bad block information, and repair block information.
A tenth aspect of the present invention is the NAND-memory security code generation method according to the ninth aspect, wherein the CRC code generation step finally generates the CRC code including the arrangement information, the repair column information, the bad block information, and the repair block information, and sets the CRC code as a unique security code of the NAND memory.
An eleventh aspect of the present invention is to provide a NAND memory characterized by comprising the NAND memory security code generation module of any one of the first to seventh aspects.
Drawings
Fig. 1 is a block diagram showing a NAND memory security code generation module according to embodiment 1 of the present invention.
Fig. 2 is a flowchart showing an operation of the CAM information reading unit according to embodiment 1 of the present invention to read various kinds of CAM information in the NAND memory.
Fig. 3 is a flowchart showing an operation of the CRC code generation unit according to embodiment 1 of the present invention to generate a unique security code.
Fig. 4 is a flowchart showing a NAND memory security code generation method according to embodiment 2 of the present invention.
Fig. 5 is a flowchart showing a method for unlocking a NAND memory having a NAND memory security code generation module incorporated therein according to embodiment 3 of the present invention.
Detailed Description
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which specific embodiments of the invention are shown. The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present invention. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.
Furthermore, various advantages and benefits of the present invention will become apparent to those of ordinary skill in the art upon reading the following detailed description of the specific embodiments. It should be understood, however, that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. The following embodiments are provided so that the invention may be more fully understood. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.
Embodiment mode 1
Inside the NAND, there is unique information called "CAM information". The CAM information includes Configuration information (Configuration information), Repair column information (Repair column information), Bad block information (Bad block information), and Repair block information (Repair block information).
Wherein the configuration information includes: band gap trimming (BandGap trim), OSC trimming, PUMP OSC trimming, and other special trimming data; operating target voltages such as a P/E start voltage, a VPASS voltage, a VREAD voltage, a Program verify voltage (Program verify voltage), a Selected read voltage (Selected read voltage), etc.; and other configuration register data. The repair column information includes repair column address information for the failed column. The bad block information includes bad block address information for the failed block. The repair block information includes repair block address information for the failed block.
The CAM information also includes other specific information, such as OPT protection, block protection, and the like.
The inventors have studied to find that CAM information data are different from each other in respective different NAND memory chips. Specifically, the configuration information may be different for each different NAND memory chip in terms of the special trimming data such as the band gap trimming, the OSC trimming, and the PUMP OSC trimming, and the P/E activation voltage may be different. Regarding the repair column information, the bad block information, and the repair block information, these pieces of information are necessarily different for the respective different NAND memory chips. This is because the various NAND memory chips have different defects and cannot be identical to each other.
In case of using different CAM information data in the respective NAND memory chips, it is possible to generate unique security codes on the respective NAND memory chips without placing a special IP having a disadvantage of a large area to avoid illegal access and illegal copying.
In view of this, in embodiment 1 of the present invention, there is provided a NAND memory security code generation block that generates a unique security code by using CAM information data in a NAND memory. Hereinafter, a NAND memory security code generation module according to embodiment 1 of the present invention will be described in detail with reference to the drawings.
Fig. 1 is a block diagram showing a NAND memory security code generation module 100 according to embodiment 1 of the present invention.
As shown in fig. 1, NAND memory security code generation block 100 according to embodiment 1 includes CAM information reading section 101, register value updating section 102, CRC code generation section 103, and security code storage section 104.
The CAM information reading unit 101 reads various CAM information in the NAND memory, such as configuration information, repair column information, bad block information, and repair block information. In some embodiments, the CAM information also includes OPT protection, block protection, etc. information.
The register value update unit 102 updates each register value corresponding to the CAM information read by the CAM information reading unit 101. For example, after reading the configuration information, the register value updating unit 102 updates the CNF register value with respect to the configuration information; after the repair column information is read, updating the register value of the repair column aiming at the repair column information; after the bad block information is read, updating the register value of the bad block aiming at the bad block information; and after the repair block information is read, updating the repair block register value according to the repair block information. In addition, in some embodiments, the register value updating unit 102 may also update register values related to OPT protection, block protection, and other information.
The CRC code generation unit generates a CRC code based on a CRC (cyclic redundancy code) algorithm using the register value updated by the register value update unit 102.
The CRC code generated by the CRC code generation unit is finally updated and stored to the secure code storage unit 104, which is, for example, a 32-bit register, only for access by a particular user.
When the CAM information reading section 101 finishes reading all the CAM information, the CRC code stored in the security code storage section 104 at this time is set as the unique security code of the NAND memory.
Hereinafter, the operation of each unit will be described in detail in turn.
Fig. 2 is a flowchart showing an operation of the CAM information reading unit 101 according to embodiment 1 of the present invention to read various kinds of CAM information in the NAND memory.
As shown in fig. 2, after power-on reset (POR) of the NAND memory, in step S101, the CAM information reading unit 101 starts up, and reading of various kinds of CAM information data is started.
In step S102, the CAM information reading unit 101 first reads the configuration information in the CAM information data. Then, in step S103, the CNF register value is updated for the configuration information obtained by the reading by the register value updating unit 102.
After the update of the CNF register value is completed, in step S104, the CAM information reading unit 101 reads the repair column information in the CAM information data. Then, in step S105, the repair column register value is updated for the repair column information obtained by the read by the register value updating unit 102.
After the update of the repair column register value is completed, the CAM information reading unit 101 reads bad block information in the CAM information data in step S106. Then, in step S107, the bad block register value is updated for the read obtained bad block information by the register value updating unit 102.
After the update of the bad block register value is completed, in step S108, the CAM information reading unit 101 reads the repair block information in the CAM information data. Then, in step S109, the repair block register value is updated for the repair block information obtained by the read by the register value updating unit 102.
At this point, the CAM information data reading by the CAM information reading unit 101 is completed.
In some embodiments, in the case where information such as OPT protection and block protection is also included in the CAM information, the CAM information reading unit 101 also reads the information data, and the register value updating unit 102 updates the relevant register value for the read CAM information data.
Fig. 3 is a flowchart showing an operation of CRC code generation section 103 according to embodiment 1 of the present invention to generate a unique security code.
In step S201, the CRC Code generation unit 103 generates a first CRC Code, which is written as CRC _ Code _0<31:0>, using a CRC algorithm based on the configuration information read by the CAM information reading unit 101.
Specifically, after the CNF register values are completely updated by the register value updating unit 102 for the configuration information read in step S102 in step S103, the CRC code generating unit 103 generates a first CRC code based on the first reading of the CAM information data, that is, the reading of the configuration information, using all the CNF register values. The first CRC code includes a result of a first read of the CAM information data, i.e., includes configuration information data in the CAM information data. Then, the generated first CRC Code CRC _ Code _0<31:0> is stored in the security Code storage unit 104.
Next, in step S202, the CRC Code generation unit 103 generates a second CRC Code, which is denoted as CRC _ Code _1<31:0>, using a CRC algorithm based on the repair column information read by the CAM information reading unit 101 and the first CRC Code generated in step S201.
Specifically, after the repair column register values are completely updated by the register value updating unit 102 for the repair column information read in step S104 in step S105, the CRC code generating unit 103 generates the second CRC code based on the first read and the second read of the CAM information data using all the repair column register values and the first CRC code generated in step S201. The second CRC code includes configuration information data, which is a result of first reading the CAM information data, and repair column information data, which is a result of second reading the CAM information data. Then, the generated second CRC Code CRC _ Code _1<31:0> is updated and stored in the security Code storage unit 104.
Next, in step S203, CRC Code generation section 103 generates a third CRC Code, which is expressed as CRC _ Code _2<31:0>, using a CRC algorithm based on the bad block information read by CAM information reading section 101 and the second CRC Code generated in step S202.
Specifically, after the updating of the bad block register value is completed by the register value updating unit 102 for the bad block information read in step S106 in step S107, the CRC code generating unit 103 generates the third CRC code based on the first reading, the second reading, and the third reading of the CAM information data, using all the bad block register values and the second CRC code generated in step S202. The third CRC code includes configuration information data that is a result of first reading the CAM information data; the result of the second reading of the CAM information data, i.e., the repair column information data; and the result of the third read of the CAM information data, i.e., the bad block information data. Then, the generated third CRC Code CRC _ Code _2<31:0> is updated and stored in the security Code storage unit 104.
Finally, in step S204, similarly, the CRC Code generation unit 103 generates a fourth CRC Code, which is denoted as CRC _ Code _3<31:0>, using a CRC algorithm based on the repair block information read by the CAM information reading unit 101 and the third CRC Code generated in step S203.
Specifically, after the update of the repair block register values is completed by the register value update unit 102 for the repair block information read in step S108 in step S109, the CRC code generation unit 103 generates the fourth CRC code based on the first read, the second read, the third read, and the fourth read of the CAM information data, using all the repair block register values and the third CRC code generated in step S203. The fourth CRC code includes configuration information data that is a result of first reading of the CAM information data; the result of the second reading of the CAM information data, i.e., the repair column information data; the result of the third reading of the CAM information data, namely the bad block information data; and the result of the fourth read of the CAM information data, i.e., the repair block information. Then, the generated fourth CRC Code CRC _ Code _3 is updated and stored in the security Code storage unit 104. The fourth CRC Code CRC _ Code _3<31:0> is the final and unique CRC Code generated based on all CAM information data.
With regard to the generated CRC code, it is realized, for example, based on CRC-32-IEEE 802.3 in the following manner:
polynomial (Polynomial) x32+ x26+ x23+ x22+ x16+ x12+ x11+ x10+ x8+ x7+ x5+ x4+ x2+ x +1
Data input (Data input) 8bits
Initial value 0xA5A5A5A5 (Capture failure, even if the data are all "1" or all "0")
Convention (Convention) that the first serial data bit is D (7) (MSB)
The CRC code implementation is merely an example, and other known methods in the art may be used as long as the CRC code can be generated based on the CAM information data.
After all the CAM information data are read, the above-described fourth CRC Code CRC _ Code _3<31:0> finally generated by the CRC Code generation unit 103 is updated and stored in the security Code storage unit 104, and the fourth CRC Code CRC _ Code _3<31:0> is set as a final unique security Code for access by a special user. The secure code storage unit 104 is, for example, a 32-bit register, but is not limited thereto.
In some embodiments, when the CAM information further includes information such as OPT protection and block protection, the CRC code generation unit 103 may generate a final CRC code and update and store the final CRC code in the security code storage unit 104 in the same manner as described above. The CRC code here is a final and unique CRC code generated based on all CAM information data including information such as OPT protection and block protection.
To this end, after a power-on reset (POR) phase, the NAND memory can obtain a 32-bit unique security code through a series of processes. The unique security code is accessible to a particular user.
In addition, although embodiment 1 described above shows an example in which the arrangement information, the repair column information, the bad block information, the repair block information, and the like in the CAM information data are sequentially read, the order of reading is not limited to this. The CAM information data may be read in any manner and order as long as it can be read and generate a unique CRC code containing the CAM information data.
By using the NAND memory security code generation module according to embodiment 1 and generating a unique security code using CAM information data in the NAND memory, each NAND memory can obtain a unique security code using different CAM information data without placing any special IP and without increasing the chip size, and the memory can be prevented from being subjected to any unauthorized access and unauthorized copying. The data security of the NAND memory is improved, and meanwhile, the miniaturization of the NAND memory chip is achieved.
Embodiment mode 2
Fig. 4 is a flowchart showing a NAND memory security code generation method according to embodiment 2 of the present invention. Next, a method for generating a security code of a NAND memory according to embodiment 2 of the present invention will be described with reference to fig. 4. In the following description, the same portions as those in embodiment 1 are omitted and will not be described again.
As shown in FIG. 4, first the NAND memory chip is Power On Reset (POR).
Next, in step S301, CAM information data including, but not limited to, configuration information, repair column information, bad block information, and repair block information is read by the CAM information reading unit 101, and then proceeds to step S302.
In step S302, the register value updating unit 102 updates the register value corresponding to the read CAM information data, and then proceeds to step S303.
In step S303, the CRC code generation unit 103 generates a CRC code with the updated register value, and then proceeds to step S304.
In step S304, the generated CRC code is updated and stored in the security code storage unit 104.
Next, in step S305, it is determined whether all the CAM information data have been read. If it is determined that all the CAM information data have been read, the CRC code stored in the security code storage section 104 is set as the final unique security code. If it is determined that all the CAM information data is not read, the process returns to step S301, and steps S301 to S305 are repeatedly executed until all the CAM information data is completely read.
In embodiment 2, by generating a unique security code using CAM information data in a NAND memory, each NAND memory can obtain a unique security code using different CAM information data without placing any special IP and without increasing the chip size, and further, the memory can be prevented from being subjected to any unauthorized access and unauthorized copying, and the NAND memory chip can be miniaturized while improving the data security.
Embodiment 3
Fig. 5 is a flowchart showing a method for unlocking a NAND memory having the NAND memory security code generation module 100 incorporated therein according to embodiment 3 of the present invention.
The NAND memory according to embodiment 3 incorporates the NAND memory security code generation module 100. Hereinafter, a method for a user to unlock a NAND memory having the NAND memory security code generation module 100 built therein will be described with reference to fig. 5.
As shown in fig. 5, first, after the NAND memory is powered on, the NAND-memory security code generation block 100 incorporated in the NAND memory reads the CAM information data and generates the unique security code as described in embodiments 1 and 2.
Next, in step S401, it is determined whether the user inquires the NAND memory for a 32-bit security code using a special command provided by the NAND memory vendor. Here, the generated unique security code is set to 32 bits, but is not limited thereto.
If it is determined in step S401 that the user inquires the NAND memory about the 32-bit security code using the special command provided by the NAND memory vendor (yes in step S401), the process proceeds to step S402, and the 32-bit security code is acquired from the NAND memory.
Next, in step S403, it is determined whether the user has input a 32-bit security code. If it is determined in step S403 that the user has input the 32-bit security code (yes in step S403), the process proceeds to step S404.
Next, in step S404, it is determined whether or not the 32-bit security code input by the user matches the 32-bit security code stored inside the NAND memory. If it is determined in step S404 that the 32-bit security code input by the user matches the 32-bit security code stored in the NAND memory (yes in step S404), the process proceeds to step S405, where the user is granted access to the NAND memory.
If it is determined in step S401 that the user has not made an inquiry to the NAND memory using a special command provided by the NAND memory vendor (no in step S401), or if it is determined in step S403 that the user has not input a 32-bit security code (no in step S403), or if it is determined in step S404 that the 32-bit security code input by the user does not match the 32-bit security code stored inside the NAND memory (no in step S404), the process proceeds to step S406, where the user is denied access to the NAND memory, and the NAND memory is locked regardless of any subsequent sequence of the user.
According to embodiment 3, by using the NAND memory security code generation module 100 built in the NAND memory, it is possible to generate a unique security code using CAM information data in the NAND memory, and thus it is possible to prevent the memory from being subjected to any unauthorized access and unauthorized copy without placing any special IP and without increasing the chip size, and to improve the data security of the NAND memory and to miniaturize the NAND memory chip.

Claims (11)

1. A NAND memory security code generation module, comprising:
a CAM information reading unit that reads CAM information in the NAND memory;
a register value updating unit that updates a register value corresponding to each of the CAM information with respect to the CAM information read by the CAM information reading unit;
a CRC code generation unit that generates a CRC code using the register value updated by the register value update unit; and
a security code storage unit that updates and stores the CRC code generated by the CRC code generation unit.
2. The NAND-memory security code generation module of claim 1,
the CAM information includes configuration information, repair column information, bad block information, and repair block information.
3. The NAND-memory security code generation module of claim 2,
the CAM information reading unit reads the configuration information, the repair column information, the bad block information, and the repair block information, respectively,
the CRC code generation unit finally generates the CRC code including the configuration information, the repair column information, the bad block information, and the repair block information, and sets the CRC code as a unique security code of the NAND memory.
4. The NAND-memory security code generation module of claim 2,
the register value updating unit updates register values corresponding to the configuration information, the repair column information, the bad block information, and the repair block information, respectively.
5. The NAND-memory security code generation module of claim 4,
the CRC code generation unit performs the following operations:
generating a first CRC code based on the register value corresponding to the configuration information updated by the register value updating unit;
generating a second CRC code based on the first CRC code and the register value corresponding to the repair column information updated by the register value updating unit;
generating a third CRC code based on the register value corresponding to the bad block information updated by the register value updating unit and the second CRC code;
generating a fourth CRC code based on the register value corresponding to the repair block information updated by the register value updating unit and the third CRC code,
setting the fourth CRC code to a unique security code of the NAND memory.
6. The NAND-memory security code generation module of claim 2,
the CAM information also includes OPT protection information and block protection information.
7. The NAND-memory security code generation module of claim 1,
the CAM information reading unit reads the CAM information each time the NAND memory is powered on and reset.
8. A NAND memory security code generation method is characterized in that the following steps are carried out at each power-on reset of a NAND memory:
a CAM information data reading step of reading a plurality of CAM information data in the NAND memories, respectively;
a register value updating step of updating register values corresponding to the plurality of read CAM information data, respectively;
a CRC code generation step of generating a CRC code using the updated register value; and
and a CRC code storage step of updating and storing the generated CRC code.
9. The NAND-memory security code generation method of claim 8,
the plurality of CAM information data are configuration information data, repair column information data, bad block information data, and repair block information data.
10. The NAND-memory security code generation method of claim 9,
in the CRC code generation step, the CRC code including the configuration information, the repair column information, the bad block information, and the repair block information is finally generated and set as a unique security code of the NAND memory.
11. A NAND memory, characterized in that,
comprising the NAND-memory security code generation module of any one of claims 1 to 7.
CN202210093628.5A 2022-01-26 2022-01-26 NAND memory security code generation module and generation method, and NAND memory Pending CN114398013A (en)

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