CN114388607A - 半导体器件及其制造方法和晶体管结构 - Google Patents
半导体器件及其制造方法和晶体管结构 Download PDFInfo
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- CN114388607A CN114388607A CN202110504821.9A CN202110504821A CN114388607A CN 114388607 A CN114388607 A CN 114388607A CN 202110504821 A CN202110504821 A CN 202110504821A CN 114388607 A CN114388607 A CN 114388607A
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Abstract
本公开提供了半导体器件及其制造方法和晶体管结构。一种半导体器件包括:基板;第一晶体管,形成在基板之上并具有第一晶体管堆叠,该第一晶体管堆叠包括多个第一沟道结构、围绕第一沟道结构的第一栅极结构以及在第一晶体管堆叠的在第一沟道长度方向上的两端处的第一源极/漏极区和第二源极/漏极区;以及第二晶体管,在垂直方向上形成在第一晶体管之上并具有第二晶体管堆叠,该第二晶体管堆叠包括多个第二沟道结构、围绕第二沟道结构的第二栅极结构以及在第二晶体管堆叠的在第二沟道长度方向上的两端处的第三源极/漏极区和第四源极/漏极区,其中第三源极/漏极区不与第一源极/漏极区或第二源极/漏极区垂直地重叠,并且第四源极/漏极区不与第一源极/漏极区或第二源极/漏极区垂直地重叠。
Description
技术领域
与本发明构思的示例实施方式一致的装置和方法涉及半导体器件结构,更具体地,涉及具有交叉的多堆叠(multi-stack)纳米片结构的半导体器件结构。
背景技术
对半导体器件的小型化的日益增长的需求已经引入纳米片晶体管,纳米片晶体管的特征在于:多个纳米片层,桥接形成在其两端处的源极/漏极区;以及栅极结构,完全地环绕纳米片层的所有侧面。这些纳米片层用作电流在纳米片晶体管的源极/漏极区之间流动的多个沟道。由于这种结构,除了在包括纳米片晶体管的半导体器件中更高的器件密度之外,还能够改善对流过所述多个沟道的电流的控制。纳米片晶体管也被称为各种不同的名称,诸如多桥沟道FET(MBCFET)、纳米束、纳米带、叠加沟道器件等。
图1示出用于半导体器件的相关技术的纳米片结构。图1所示的纳米片结构100包括两个或更多个纳米片层110,该两个或更多个纳米片层110在D3方向上以重叠的方式垂直地堆叠在基板105之上。用作由纳米片结构100形成的晶体管的沟道的纳米片层110被栅极结构115完全围绕,除了在其形成在栅极结构115的相反两侧的敞开端部之外,源极/漏极区将生长在所述敞开端部处以完成作为单个晶体管的纳米片结构100,诸如纳米片金属氧化物半导体FET(MOSFET)。也就是,与具有单层或单鳍沟道结构的常规平面FET或finFET不同,图1的纳米片结构使在源极/漏极区之间具有多个沟道的单个晶体管成为可能。在图1中,源极/漏极区从纳米片结构100有意地省略,仅是为了示出纳米片层110如何采取在作为纳米片结构100的沟道长度方向的D2方向上分别穿透栅极结构115的形式。
基板105可以是半导体材料的块体基板,例如硅(Si)或绝缘体上硅(SOI)基板,纳米片层110也可以由Si形成,栅极结构115可以由导体金属和栅极电介质层形成。导体金属可以是钨(W)或铝(Al),并且栅极电介质层可以包括用于与纳米片层110电绝缘的硅氧化物(SiO)或金属硅酸盐。
然而,即使晶体管由像纳米片层110一样的多个沟道层形成,用于减小单个晶体管的尺寸的技术也受到限制。
在本背景技术部分中公开的信息在实现本申请的实施方式之前已经为发明人知晓,或者是在实现实施方式的过程中获取的技术信息。因此,它可能包含不构成公众已知的现有技术的信息。
发明内容
本公开提供具有拥有不同沟道方向的两个或更多个纳米片堆叠的多堆叠纳米片结构以及制造该多堆叠纳米片结构的方法。
根据实施方式,提供一种半导体器件,该半导体器件可以包括:基板;第一晶体管,形成在基板之上并具有第一晶体管堆叠,该第一晶体管堆叠包括多个第一沟道结构、围绕所述多个第一沟道结构的第一栅极结构以及在第一晶体管堆叠的在第一沟道长度方向上的两端处的第一源极/漏极区和第二源极/漏极区;以及第二晶体管,在垂直方向上形成在第一晶体管之上并具有第二晶体管堆叠,该第二晶体管堆叠包括多个第二沟道结构、围绕所述多个第二沟道结构的第二栅极结构以及在第二晶体管堆叠的在第二沟道长度方向上的两端处的第三源极/漏极区和第四源极/漏极区,其中第三源极/漏极区不与第一源极/漏极区或第二源极/漏极区垂直地重叠,并且第四源极/漏极区不与第一源极/漏极区或第二源极/漏极区垂直地重叠。
根据实施方式,提供一种晶体管结构,该晶体管结构可以包括:第一晶体管堆叠和形成在第一晶体管堆叠之上的第二晶体管堆叠,其中第一晶体管堆叠包括被第一栅极结构围绕的多个第一沟道结构,并且第二晶体管堆叠包括被第二栅极结构围绕的多个第二沟道结构,其中第一沟道结构配置为形成用于第一电流在第一沟道长度方向上流动的第一沟道,第二沟道结构配置为形成用于第二电流在第二沟道长度方向上流动的第二沟道,其中第一沟道长度方向和第二沟道长度方向彼此不同。
根据实施方式,提供一种制造半导体器件的方法。该方法可以包括以下操作:(a)提供半导体器件结构,该半导体器件结构包括基板、形成在基板上的第一晶体管堆叠和形成在第一晶体管堆叠上的第二晶体管堆叠,其中第一晶体管堆叠和第二晶体管堆叠分别包括多个第一沟道结构和多个第二沟道结构;(b)形成第一虚设栅极以围绕第一晶体管堆叠,并在第一虚设栅极上形成第二虚设栅极以围绕第二晶体管堆叠和第二晶体管堆叠的顶表面;(c)去除在第一晶体管堆叠的四个侧面当中的至少第一侧面和第二侧面的至少部分上的第一虚设栅极,并分别在第一晶体管堆叠的其中去除第一虚设栅极的第一侧面和第二侧面上形成第一源极/漏极区和第二源极/漏极区;(d)去除在第二晶体管堆叠的四个侧面当中的至少第三侧面和第四侧面的至少部分上的第二虚设栅极,并分别在第二晶体管堆叠的其中去除第二虚设栅极的第三侧面和第四侧面上形成第三源极/漏极区和第四源极/漏极区;以及(e)去除剩余的第一虚设栅极和剩余的第二虚设栅极并分别用第一置换金属栅极和第二置换金属替代剩余的第一虚设栅极和剩余的第二虚设栅极,以形成分别围绕第一沟道结构和第二沟道结构的第一栅极结构和第二栅极结构,其中第一源极/漏极区至第四源极/漏极区被形成为使得第三源极/漏极区不与第一源极/漏极区或第二源极/漏极区重叠,并且第四源极/漏极区不与第一源极/漏极区或第二源极/漏极区重叠。
所公开的交叉的多堆叠纳米片结构可以使源极/漏极接触结构能够着落在下纳米片堆叠的源极/漏极区的顶表面上而不是其侧表面上,并减小在源极/漏极接触结构与上纳米片堆叠的源极/漏极区之间的寄生电容。
附图说明
从以下结合附图的详细描述,本发明构思的示例实施方式将被更清楚地理解,附图中:
图1示出用于半导体器件的相关技术的纳米片结构;
图2A示出根据一实施方式的由多个纳米片层形成的半导体器件的透视图;
图2B示出在源极/漏极区形成在图2A的半导体器件200A处之后的半导体器件的透视图;
图3A示出根据一实施方式的由多个纳米片层形成的半导体器件的透视图;
图3B示出在源极/漏极区形成在图3A的半导体器件300A上之后的半导体器件的透视图;
图4A至图4C分别示出根据一实施方式的在多个纳米片堆叠形成在基板上的状态下的半导体器件的两个剖视图和平面图;
图5A至图5C分别示出根据一实施方式的具有形成在其上的虚设栅极的半导体器件的两个剖视图和平面图;
图6A至图6C分别示出根据一实施方式的半导体器件的两个剖视图和平面图,在该半导体器件中围绕上纳米片堆叠的虚设栅极的部分被图案化;
图7A至图7C分别示出根据一实施方式的半导体器件的两个剖视图和俯视平面图,在该半导体器件中源极/漏极区生长在下纳米片堆叠上;
图8A至图8C分别示出根据一实施方式的半导体器件的两个剖视图和俯视平面图,在该半导体器件中源极/漏极区生长在上纳米片堆叠上;
图9A至图9C分别示出根据一实施方式的半导体器件的两个剖视图和俯视平面图,在该半导体器件中附加的ILD层形成在上纳米片堆叠之上;
图10A至图10C分别示出根据一实施方式的半导体器件的两个剖视图和俯视平面图,在该半导体器件中置换金属栅极被形成为围绕下纳米片堆叠的纳米片层;
图11A至图11C分别示出根据一实施方式的半导体器件的两个剖视图和俯视平面图,在该半导体器件中置换金属栅极被形成为围绕上纳米片堆叠的纳米片层;
图12A至图12C分别示出根据一实施方式的其中形成有源极/漏极接触结构的半导体器件的两个剖视图和俯视平面图;
图13示出描述根据一实施方式的制造参照图4A-图4C至图12A-图12C的具有多堆叠晶体管结构的半导体器件的方法的流程图;
图14A示出根据一实施方式的半导体模块的示意平面图;以及
图14B示出根据一实施方式的电子系统的示意框图。
具体实施方式
这里描述的实施方式都是示例实施方式,因此本发明构思不限于此,并可以以各种其它形式实现。在以下描述中提供的每个实施方式不排除与这里也提供或这里未提供但与本发明构思一致的另一示例或另一实施方式的一个或更多个特征相关联。例如,即使在特定示例或实施方式中描述的内容没有在与其不同的示例或实施方式中描述,该内容也可以被理解为与所述不同的示例或实施方式相关或与其组合,除非在其描述中另外地提及。此外,应当理解,对本发明构思的原理、方面、示例和实施方式的所有描述旨在涵盖其结构和功能上的等同物。此外,这些等同物应当被理解为不仅包括当前公知的等同物,而且包括将在未来开发的等同物,也就是,被发明来执行相同功能的所有器件,无论其结构如何。例如,这里描述的MOSFET可以采用不同类型或形式的晶体管,只要本发明构思能够应用于其。
将理解,当半导体器件的一元件、部件、层、图案、结构、区域等(在下文统称为“元件”)被称为在半导体器件的另一元件“之上”、“上方”、“上”、“下方”、“之下”、“下面”,“连接到”或“联接到”半导体器件的另一元件时,它可以直接在该另一元件之上、上方、上、下方、之下、下面,连接到或联接到该另一元件,或者可以存在居间的元件。相反,当半导体器件的一元件被称为“直接在”半导体器件的另一元件“之上”、“上方”、“上”、“下方”、“之下”、“下面”,“直接连接到”或“直接联接到”半导体器件的另一元件时,不存在居间的元件。在整个本公开中,相同的标记表示相同的元件。
为了描述的方便,这里可以使用空间关系术语诸如“在......之上”、“在......上方”、“在......上”、“上”、“在......下方”、“在......之下”、“在......下面”、“下”等来描述如附图所示的一个元件和另一个(些)元件的关系。将理解,空间关系术语旨在涵盖除了附图中绘出的取向之外半导体器件在使用或操作中的不同取向。例如,如果附图中的半导体器件被翻转,被描述为在其它元件“下方”或“下面”的元件将于是取向在所述其它元件“之上”。因此,术语“下方”可以涵盖之上和之下两种取向。半导体器件可以另外地取向(旋转90度或处于其它取向),这里使用的空间关系描述语被相应地解释。
如这里所用的,诸如“......中的至少一个”的表述,当在一列元件之后时,修饰整个列表的元件而不是修饰该列表中的各个元件。例如,表述“a、b和c中的至少一个”应当被理解为包括仅a、仅b、仅c、a和b两者、a和c两者、b和c两者、或a、b和c的全部。这里,当术语“相同”用于比较两个或更多个元件的尺寸时,该术语可以涵盖“基本上相同”的尺寸。
将理解,尽管这里可以使用术语“第一”、“第二”、“第三”、“第四”等来描述不同元件,但是这些元件不应受到这些术语的限制。这些术语仅用于将一个元件与另一元件区别开。因此,下面讨论的第一元件可以被称为第二元件,而没有脱离本发明构思的教导。
还将理解,即使制造发明的装置或结构的某个步骤或操作被描述为晚于另一步骤或操作,该步骤或操作也可以早于该另一步骤或操作来执行,除非该另一步骤或操作被描述为在该步骤或操作之后执行。
这里参照剖视图描述了许多实施方式,该剖视图是实施方式(和中间结构)的示意图。因而,由例如制造技术和/或公差引起的图示形状的变化是可预期的。因此,实施方式不应被解释为限于这里示出的区域的特定形状,而是包括例如由制造引起的形状偏差。例如,示出为矩形的注入区域将通常在其边缘处具有圆化或弯曲的特征和/或注入浓度的梯度,而不是从注入区域到非注入区域的二元变化。同样地,通过注入形成的掩埋区域可以导致在掩埋区域与通过其发生注入的表面之间的区域中的一些注入。因此,附图中示出的区域在本质上是示意性的,它们的形状不旨在示出器件的区域的实际形状,也不旨在限制本发明构思的范围。此外,在附图中,为了清楚起见,层和区域的尺寸和相对尺寸可以被夸大。
为了简洁起见,这里可以详细描述或可以不详细描述对于包括纳米片晶体管的半导体器件的常规元件。
根据一实施方式,图1所示的纳米片结构100也可以被垂直堆叠以构成多堆叠纳米片结构,从而实现增大的器件密度。
图2A示出根据一实施方式的由多个纳米片层形成的半导体器件的透视图。
图2A所示的半导体器件200A处于在半导体器件200A形成为两个纳米片晶体管之前的状态。半导体器件200A具有多个第一纳米片层210的第一沟道组和多个第二纳米片层220的第二沟道组。第一沟道组和第二沟道组在D3方向上以垂直地重叠的方式堆叠在基板205之上,以构成多堆叠纳米片结构。隔离层230插设在第一沟道组和第二沟道组之间。
图2A还示出第一栅极结构215和第二栅极结构225分别完全地围绕第一纳米片层210和第二纳米片层220的沟道区(不可见),除了它们的在第一栅极结构215和第二栅极结构225的相反两侧处的敞开端部之外,源极/漏极区可以外延生长在所述敞开端部处以构成如图2B所示的两个纳米片晶体管。因此,第一纳米片层210和第二纳米片层220采取在D2方向(其是沟道长度方向)上分别穿透第一栅极结构215和第二栅极结构225的形式。
图2B示出在源极/漏极区形成在图2A的半导体器件200A处之后的半导体器件的透视图。
参照图2B,半导体器件200B包括具有在第一纳米片层210的沟道区(不可见)的两端处的第一源极/漏极区211和第二源极/漏极区212的下晶体管201以及具有在第二纳米片层220的沟道区(不可见)的两端处的第三源极/漏极区213和第四源极/漏极区214的上晶体管202。这些源极/漏极区211至214将分别通过第一源极/漏极接触结构221至第四源极/漏极接触结构224连接到电源或用于进行内部布线的其它电路元件(未示出)。此外,第二栅极结构225配置为通过栅极接触结构226接收栅极输入信号。
然而,要注意,由于上晶体管202的第三源极/漏极区213和第四源极/漏极区214分别与下晶体管201的第一源极/漏极区211和第二源极/漏极区212垂直地重叠,所以根据一实施方式,从上金属图案(未示出)笔直向下延伸的第一源极/漏极接触结构221和第二源极/漏极接触结构222被弯曲以分别与下晶体管201的第一源极/漏极区211和第二源极/漏极区212的侧表面进行侧向接触。以另外的方式,根据一实施方式,第一源极/漏极接触结构221和第二源极/漏极接触结构222可以从下方连接,在这种情况下,连接到第一源极/漏极接触结构221和第二源极/漏极接触结构222的对应的下金属图案可以被掩埋在基板205中。
然而,在基于纳米片的半导体器件的制造工艺期间,非常难以实现利用弯曲形状的源极/漏极接触结构的与源极/漏极区的前述侧向连接、以及使用基板掩埋的金属图案的向上连接。
因此,根据一实施方式,由多个纳米片层形成的半导体器件的新结构及其制造方法被提供如下。
图3A示出根据一实施方式的由交叉的多堆叠纳米片结构形成的半导体器件的透视图。
像图2A的半导体器件200A,根据一实施方式的图3A所示的半导体器件300A处于在半导体器件300A形成为两个纳米片晶体管之前的状态。类似于图2A的半导体器件200A,图3A所示的半导体器件300A具有多个第一纳米片层310的第一沟道组和多个第二纳米片层320的第二沟道组。第一沟道组和第二沟道组在D3方向上以垂直地重叠的方式堆叠在基板305之上,以构成多堆叠纳米片结构。隔离层330插设在第一沟道组和第二沟道组之间。
此外,第一栅极结构315和第二栅极结构325分别完全地围绕第一纳米片层和第二纳米片层的沟道区(不可见),除了它们的在第一栅极结构315和第二栅极结构325的相反两侧处的敞开端部之外,源极/漏极区可以外延生长在所述敞开端部处以构成如图3B所示的两个纳米片晶体管。
然而,半导体器件300A与半导体器件200A的不同之处在于,第二纳米片层320在D1方向上延伸而第一纳米片层310在D2方向上延伸。也就是,第一纳米片层310的沟道长度方向和沟道宽度方向分别与第二纳米片层320的沟道长度方向和沟道宽度方向成一角度,诸如分别垂直于第二纳米片层320的沟道长度方向和沟道宽度方向。半导体器件300A与半导体器件200A的这种结构差异旨在使得从第二纳米片层320形成的源极/漏极区不与从第一纳米片层310形成的源极/漏极区垂直地重叠,如下面参照图3B所述。
图3B示出在源极/漏极区形成在图3A的半导体器件300A上之后的半导体器件的透视图。
参照图3B,根据一实施方式的半导体器件300B包括下晶体管301和上晶体管302,该下晶体管301具有在第一纳米片层310的其沟道区(不可见)的两端处的第一源极/漏极区311和第二源极/漏极区312,该上晶体管302具有在第二纳米片层320的沟道区(不可见)的两端处的第三源极/漏极区313和第四源极/漏极区314。这些源极/漏极区311至314将通过第一源极/漏极接触结构321至第四源极/漏极接触结构324分别连接到电源或用于进行内部布线的其它电路元件(未示出)。此外,第二栅极结构325配置为通过栅极接触结构326接收栅极输入信号。
半导体器件300B的上述结构方面类似于图2B的半导体器件200B的那些,除了形成在第二纳米片层320的沟道端部上的第三源极/漏极区313和第四源极/漏极区314不与形成在第一纳米片层310的沟道端部上的第一源极/漏极区311和第二源极/漏极区312垂直地重叠之外。因此,与图2B的半导体器件200B不同,半导体器件300B不需要从上金属图案(未示出)笔直向下延伸的第一源极/漏极接触结构321和第二源极/漏极接触结构322弯曲以分别与下晶体管301的第一源极/漏极区311和第二源极/漏极区312的侧表面进行相应的侧向接触。因此,第一源极/漏极接触结构321和第二源极/漏极接触结构322可以配置为分别着落在第一源极/漏极区311的顶表面和第二源极/漏极区312的顶表面上,而不像在图2B的半导体器件200B中一样被弯曲。
与相关技术的半导体器件相比,半导体器件300B的以上结构特性使得源极/漏极接触结构的形成更加简单。此外,由于图3B的半导体器件300B中的第三源极/漏极区313或第四源极/漏极区314与第一源极/漏极接触结构321或第二源极/漏极接触结构322之间的距离变得更大,所以与图2B的半导体器件200B的结构相比,可以减小在第三源极/漏极区313或第四源极/漏极区314与第一源极/漏极接触结构321或第二源极/漏极接触结构322之间可能发生的寄生电容。
在半导体器件300B中,下晶体管301可以是p型MOSFET和n型MOSFET中的一个,而上晶体管302可以是p型MOSFET和n型MOSFET中的另一个,在这种情况下,第一源极/漏极区311和第二源极/漏极区312可以与第三源极/漏极区313和第四源极/漏极区314不同地掺杂,第一栅极结构315可以具有与第二栅极结构325不同的功函数材料或特性。
下面,描述制造具有与上述半导体器件300B的结构对应的结构的半导体器件的方法。
图4A-图4C至图12A-图12C示出根据一实施方式的制造具有多堆叠纳米片结构的半导体器件的方法。在附图中,为了简洁起见,在一个或更多个附图中可以省略在不同附图中指示相同元件的附图标记。
图4A至图4C分别示出根据一实施方式的在多个纳米片堆叠形成在基板上的状态下的半导体器件的两个剖视图和平面图。
图4A是沿着图4C中的线X-X’截取的半导体器件400的剖视图,图4C是半导体器件400的俯视平面图,图4B是沿着图4C中的线Y-Y’截取的半导体器件400的剖视图。这里要注意,图4A和图4B中使用的用于示出半导体器件400的比例尺与图4C中使用的不同。这种比例尺差异适用于下文提到的所有其它附图。
参照图4A至图4C,根据一实施方式,第一纳米片堆叠410和第二纳米片堆叠420顺序地堆叠在基板405上而使第一隔离层431在第一纳米片堆叠410与基板405之间并使第二隔离层432在第一纳米片堆叠410和第二纳米片堆叠420之间,并被第三隔离层433完全围绕。第一纳米片堆叠410包括交替形成在基板405之上的三个第一牺牲层410S和两个第一纳米片层410C,第二纳米片堆叠420包括交替形成在第一纳米片堆叠410之上的三个第二牺牲层420S和两个第二纳米片层420C。
尽管图4A和图4B示出第一纳米片堆叠410和第二纳米片堆叠420的每个仅具有两个纳米片层和三个牺牲层,但是每个纳米片堆叠中的纳米片层和牺牲层的数量不限于此。根据一实施方式,第一牺牲层410S和第一纳米片层410C可以通过外延生长一层、然后外延生长另一层直到期望数量的牺牲层和纳米片层被交替堆叠而形成。以与第一纳米片堆叠410相同的方式,可以形成第二牺牲层420S和第二纳米片层420C以构建第二纳米片堆叠420。根据一实施方式,第一纳米片堆叠410中的纳米片层的数量和牺牲层的数量可以不同于第二纳米片堆叠420中的那些。
根据一实施方式,第一隔离层431可以在第一纳米片堆叠410形成在基板405上之前从基板405外延生长以将第一纳米片堆叠410与基板405隔离。在形成第一纳米片堆叠410之后,可以形成第二隔离层432以将第一纳米片堆叠410与将随后形成的第二纳米片堆叠420分隔开。在第二隔离层432上形成第二纳米片堆叠420之后,形成第三隔离层433以在基板405上方完全围绕第一纳米片堆叠410和第二纳米片堆叠420。
在基板405中形成浅沟槽隔离(STI)区域406,以将半导体器件400与相邻的电路元件或半导体器件隔离。
根据一实施方式,第一纳米片堆叠410的每个第一纳米片层410C可以在Y-Y'方向上具有相同的长度L1,在X-X'方向上具有相同的宽度W1,并在与X-X'方向和Y-Y'方向垂直的方向上具有相同的厚度T1,第二纳米片堆叠420的每个第二纳米片层420C可以在X-X'方向上具有相同的长度L2,在Y-Y'方向上具有相同的宽度W2,并在与X-X'方向和Y-Y'方向垂直的方向上具有相同的厚度T2。此外,根据一实施方式,长度L1、宽度W1、长度L2和宽度W2可以彼此相等。因此,第一纳米片堆叠410和第二纳米片堆叠420可以在平面图(未示出)中具有相同的正方形形状。然而,根据实施方式,这些尺寸可以在第一纳米片层410C之间和在第二纳米片层420C之间以及在第一纳米片堆叠410和第二纳米片堆叠420之间不同。例如,长度L1可以不等于宽度W1,而是可以等于长度L2,因此,第一纳米片堆叠410和第二纳米片堆叠420可以具有相同的矩形形状。然而,根据一实施方式,第一纳米片层410C的沟道长度方向和沟道宽度方向仍然可以分别与第二纳米片层420C的沟道长度方向和沟道宽度方向不同。
基板405可以由硅(Si)形成,STI区域406可以由硅氧化物(SiOx)形成,第一隔离层431至第三隔离层433也可以由与STI区域406相同或不同的SiOx形成,第一牺牲层410S和第二牺牲层420S可以由硅锗(SiGe)形成,第一纳米片层410C和第二纳米片层420C可以由Si形成。根据一实施方式,第一牺牲层410S和第二牺牲层420S可以是SiGe 35%,其表示SiGe化合物由35%的Ge和65%的Si组成。
图5A至图5C分别示出根据一实施方式的具有形成在其上的虚设栅极的半导体器件的两个剖视图和平面图。
图5A是沿着图5C中的线X-X’截取的半导体器件500的剖视图,图5C是半导体器件500的俯视平面图,图5B是沿着图5C中的线Y-Y’截取的半导体器件500的剖视图。
参照图5A至图5C,在图4A至图4C的半导体器件400上形成第一虚设栅极414D和第二虚设栅极424D以及层间电介质(ILD)层441。第一虚设栅极414D和第二虚设栅极424D被这样称谓是因为它们将在随后的步骤中被真正的栅极结构代替。
第一虚设栅极414D例如通过光刻和蚀刻而形成在第一纳米片堆叠410上,以覆盖形成在第二纳米片堆叠420下面的第一纳米片堆叠410的所有侧的侧面(side flank)。具体地,第一虚设栅极414D围绕形成在第一纳米片堆叠410的所有侧表面上的第三隔离层433。接下来,在第一虚设栅极414D上形成第二虚设栅极424D,例如也通过光刻和蚀刻,以不仅覆盖第二纳米片堆叠420的所有侧的侧面而且覆盖其顶部。具体地,第二虚设栅极424D围绕形成在第二纳米片堆叠420的所有侧表面和顶表面上的第三隔离层433。
第一虚设栅极414D可以包括非晶硅(a-Si)或多晶硅(poly-Si),第二虚设栅极424D可以包括相同或不同的a-Si或poly-Si。
一旦如上所述形成第一虚设栅极414D和第二虚设栅极424D,就形成ILD层441以围绕第一虚设栅极414D的所有侧表面和第二虚设栅极424D的所有侧表面。ILD层441可以通过大量沉积氧化物材料(例如具有低介电常数的二氧化硅)来形成。根据一实施方式,可以在形成第一虚设栅极414D和第二虚设栅极424D之前形成ILD层441。
在如上所述形成第一虚设栅极414D和第二虚设栅极424D以及ILD层441之后,第二虚设栅极424D和ILD层441例如通过化学机械抛光(CMP)工艺在它们的顶表面处被平坦化。
像图4A和图4B,图5A和图5B示出半导体器件500的相同结构,因为其X方向截面具有与其Y方向截面相同的结构尺寸。
图6A至图6C分别示出根据一实施方式的半导体器件的两个剖视图和平面图,在该半导体器件中围绕上纳米片堆叠的虚设栅极的部分被图案化。
图6A是沿着图6C中的线X-X’截取的半导体器件600的剖视图,图6C是半导体器件600的俯视平面图,图6B是沿着图6C中的线Y-Y’截取的半导体器件600的剖视图。
参照图6A至图6C,第二虚设栅极424D、ILD层441和第三隔离层433例如通过干蚀刻被部分地图案化,例如通过干蚀刻在第二纳米片堆叠420的四个侧面的每个从顶部仅以预定长度W被部分地图案化。这里,预定长度W可以不大于第二纳米片层420C的宽度W2和长度L2的每个。
从顶部到底部执行这种图案化操作,以到达第一纳米片堆叠410的最上面的第一牺牲层410S的顶表面的水平。为了促进这种图案化,根据一实施方式,蚀刻停止层(未示出)可以已经在图5A至图5C所示的步骤中在最上面的第一牺牲层410S的顶表面的水平处在ILD层441、第一虚设栅极414D和第三隔离层433中成层(layered)。通过这种图案化操作,第二纳米片堆叠420的所有四个侧面被暴露,并且在顶部沟道钝化层451形成在第二纳米片堆叠420的暴露的四个侧面和暴露的第三隔离层433上之前围绕第一纳米片堆叠410的四个侧面的第一虚设栅极414D、ILD层441和第三隔离层433被向上暴露。
根据一实施方式,这种图案化操作可以如图6C所示通过在第二虚设栅极424D之上形成与第二虚设栅极424D的第一部分424-1至第五部分424-5相对应的掩模层(未示出)来执行。根据一实施方式,第二虚设栅极424D的第五部分424-5可以具有正方形或矩形形状,其具有与第二纳米片层420C的宽度和第二纳米片层420C的长度相同的水平长度。此外,如在图6C中的半导体器件600的俯视平面图所示,第一部分424-1至第四部分424-4可以采取从第五部分424-5的四个边缘起的四个突起的形状。
这里要注意,在第二虚设栅极424D中,第一部分424-1至第四部分424-4在作为主体部分的第五部分424-5周围被图案化,以获得穿透到第一部分424-1至第四部分424-4中的至少一个中的孔或沟槽(在下文“孔”),至少第一纳米片堆叠410的第一虚设栅极414D和第一牺牲层410S通过该孔被去除,并且可以在随后的步骤沉积置换金属栅极(RMG),该置换金属栅极围绕与第二纳米片堆叠420的第二纳米片层420C交叉的第一纳米片堆叠410的第一纳米片层410C。尽管图6C示出通过上述图案化形成第一部分424-1至第四部分424-4,但是第一部分424-1至第四部分424-4中的仅一个、两个或三个部分可以被图案化以用于前述目的。此外,相对于图5C所示的第五部分424-5的尺寸,第一部分424-1至第四部分424-4的尺寸没有按精确的比例。此外,根据实施方式,第一部分424-1至第四部分424-4可以具有彼此不同的尺寸。
接下来,在通过上述图案化的第二纳米片堆叠420的暴露的四个侧面和暴露的第三隔离层433上形成顶部沟道钝化层451。当在随后的步骤中在第一纳米片堆叠410的第一纳米片层410C上外延生长源极/漏极区时,形成顶部沟道钝化层451以保护第二纳米片堆叠420的第二纳米片层420C。如图6B所示的在第二纳米片堆叠420的两侧处的顶部沟道钝化层451与第二虚设栅极424D的第五部分424-5一起用作掩模以去除在第一纳米片堆叠410的两侧处的第一虚设栅极414D、ILD层441和第三隔离层433,源极/漏极区将在下一步骤中在该处被外延生长。
图7A至图7C分别示出根据一实施方式的半导体器件的两个剖视图和俯视图,在该半导体器件中源极/漏极区生长在下纳米片堆叠上。
图7A是沿着图7C中的线X-X’截取的半导体器件700的剖视图,图7C是半导体器件700的俯视平面图,图7B是沿着图7C中的线Y-Y’截取的半导体器件700的剖视图。
参照图7A至图7C,围绕第一纳米片堆叠的第一虚设栅极414D、ILD层441和第三隔离层433在第一纳米片堆叠410的两侧被部分地去除以暴露第一纳米片堆叠410在沟道长度方向上的两端(例如通过干蚀刻和/或湿蚀刻),然后,源极/漏极区411和412形成在第一纳米片堆叠410的所述两侧(即沿着图7B的线Y-Y’的两侧而不是沿着图7A的线X-X’的两侧)处。这些源极/漏极区411和412对应于图3B所示的下晶体管301的源极/漏极区311和312。源极/漏极区411和412可以通过外延生长工艺形成在第一纳米片堆叠410(具体地,第一纳米片层410C)的在沟道长度方向上的暴露的两端上。可以应用原位掺杂(ISD)以对源极/漏极区411和412掺杂。
图8A至图8C分别示出根据一实施方式的半导体器件的两个剖视图和俯视图,在该半导体器件中源极/漏极区生长在上纳米片堆叠上。
图8A是沿着图8C中的线X-X’截取的半导体器件800的剖视图,图8C是半导体器件800的俯视平面图,图8B是沿着图8C中的线Y-Y’截取的半导体器件800的剖视图。
参照图8A至图8C,形成在第二纳米片堆叠420的在其沟道长度方向上的两端处的顶部沟道钝化层451和在其下面的第三隔离层433沿着图8A中的X-X’方向被去除(例如通过干蚀刻),并且在第一纳米片堆叠410的在其沟道长度方向的两端处的暴露的ILD层441和第一虚设栅极414D上形成第四隔离层434。第四隔离层434可以由SiO、SiN或其等同物形成,以进一步将第一源极/漏极区411和第二源极/漏极区412与将要形成的第三源极/漏极区413和第四源极/漏极区414隔离。此第四隔离层434的厚度可以与第二隔离层432相同。
接下来,以与在之前的步骤中形成第一源极/漏极区411和第二源极/漏极区412相同的方式,在第二纳米片堆叠420的在沿着X-X’方向的其沟道长度方向的两端处在第四隔离层434上形成第三源极/漏极区413和第四源极/漏极区414,如图8A和图8C所示。
图9A至图9C分别示出根据一实施方式的半导体器件的两个剖视图和俯视图,在该半导体器件中附加的ILD层形成在上纳米片堆叠之上。
图9A是沿着图9C中的线X-X’截取的半导体器件900的剖视图,图9C是半导体器件900的俯视平面图,图9B是沿着图9C中的线Y-Y’截取的半导体器件900的剖视图。这里要注意,图9C所示的线X-X’和Y-Y’不是如在图4C至图8C所示的线X-X’和Y-Y’那样的在俯视平面图中的半导体器件900的中心线。在图9C中,线X-X’和Y-Y’被绘出以示出第二虚设栅极424D的第一部分424-1、第二部分424-2和第四部分424-4以及邻接元件的截面。
参照图9A至图9C,在线X-X'和Y-Y'处的截面仍然示出第三隔离层433、第一虚设栅极414D和第二虚设栅极424D以及围绕这两个虚设栅极的ILD层441,类似于图5A所示的半导体器件500。然而,在第二纳米片堆叠420之上(具体地,在第二纳米片堆叠420上的第三隔离层433之上)的第二虚设栅极424D被部分地去除,并且附加的ILD层442替代地填充在其中。接下来,附加的ILD层442的顶部例如通过CMP被平坦化,以与现有的ILD层441的顶表面和第二虚设栅极424D的顶表面共面。
图10A至图10C分别示出根据一实施方式的半导体器件的两个剖视图和俯视平面图,在该半导体器件中形成置换金属栅极以围绕下纳米片堆叠的纳米片层。
图10A是沿着图10C中的线X-X’截取的半导体器件1000的剖视图,图10C是半导体器件1000的俯视平面图,图10B是沿着图10C中的线Y-Y’截取的半导体器件1000的剖视图。这里要注意,图10C所示的线X-X’和Y-Y’在与图9C所示的线X-X’和Y-Y’相同的位置绘出。
参照图10A至图10C,第一部分424-1从顶部向下被部分地去除以便形成到达第一虚设栅极414D的孔415H。然后,通过此孔415H,第一纳米片堆叠410的第一虚设栅极414D和第一牺牲层410S被完全去除。此时,在第一纳米片堆叠410的侧部的第三隔离层433也被去除。接下来,用第一置换金属栅极415填充从此去除操作形成的包括孔415H的空的空间。此去除操作可以通过干蚀刻、湿蚀刻、反应离子蚀刻(RIE)和/或化学氧化物去除(COR)工艺来进行。当第一置换金属栅极415填充在该空的空间中时,可以首先沉积基于铪(Hf)的高k电介质层以及钛(Ti)、钽(Ta)或其化合物的功函数金属层,然后可以沉积诸如钨(W)或铝(Al)的导体金属,以形成围绕第一纳米片层的第一置换金属栅极415。
这里要注意,如图10A和图10C所示,用于以上去除操作的形成在第二虚设栅极424D中的孔415H可以用第一置换金属栅极415填充,使得第一置换金属栅极415的此部分415-1可以用于在下一步骤中与围绕第二纳米片层420C的置换金属栅极连接。
尽管图10A和图10C示出仅第二虚设栅极424D的第一部分424-1被部分地去除以形成用于以上去除和填充操作的孔415H,但是根据实施方式,第一部分424-1至第四部分424-4中的一个或更多个可以用于相同的目的。因此,根据实施方式,第一置换金属栅极415可以通过填充形成在第一部分424-1至第四部分424-4中的一个或更多个处的一个或更多个孔或沟槽而被部分地形成。
图11A至图11C分别示出根据一实施方式的半导体器件的两个剖视图和俯视平面图,在该半导体器件中置换金属栅极被形成为围绕上纳米片堆叠的纳米片层。
图11A是沿着图11C中的线X-X’截取的半导体器件1100的剖视图,图11C是半导体器件1100的俯视平面图,图11B是沿着图11C中的线Y-Y’截取的半导体器件1100的剖视图。这里要注意,图11C所示的线X-X’和Y-Y’在与图9C和图10C所示的线X-X’和Y-Y’相同的位置绘出。
参照图11A至图11C,现在第二虚设栅极424D与第二纳米片堆叠420的第二牺牲层420S和剩余的第三隔离层433一起被完全去除。替代地,由此去除操作产生的空间用第二置换金属栅极425填充。类似于在之前步骤中执行的操作,此去除操作可以通过RIE或COR工艺来执行,并且第二置换金属栅极的形成通过首先沉积基于Hf的高k电介质层和Ti、Ta或它们的化合物的功函数金属层、然后沉积诸如钨(W)或铝(Al)的导体金属来执行。这里要注意,第一置换金属栅极415和第二置换金属栅极425可以通过包括例如高k电介质材料的另一隔离层(未示出)而彼此绝缘。
图11A和图11B示出,在半导体器件1100中,图10A至图10C所示的包括第二虚设栅极424D的剩余的第一部分424-1至第四部分424-4的第二虚设栅极424D被完全地去除并用第二置换金属栅极425代替。因此,半导体器件1100现在不仅在与第五部分424-5对应的部分而且在与第一部分424-1至第四部分424-4相对应的四个部分具有第二置换金属栅极425。这里要注意,如图11A所示,与部分424-1相对应的部分现在包括第一置换金属栅极415的部分415-1以及并排的第二置换金属栅极425的部分。然而,根据实施方式,与第一部分424-1至第四部分424-4相对应的部分中的一个或更多个可以形成为包括第一置换金属栅极415的一部分以及第二置换金属栅极425的一部分。半导体器件1100的这种结构不同于图3B所示的半导体器件300B的结构。
接下来,在与第一部分424-1至第四部分424-4相对应的部分处的第二置换金属栅极425的顶部被凹陷并填充有用于将第二置换金属栅极425与其它电路元件(未示出)连接的相应金属图案461。填充在与第二虚设栅极424D的第一部分424-1相对应的部分中的金属图案将第二置换金属栅极425与填充在图10A至图10C的之前步骤中形成的孔415H中的第一置换金属栅极415的部分415-1连接。第一置换金属栅极415和第二置换金属栅极425的这种连接可以被实现以用于具有公共栅极的晶体管,诸如反相器电路,但是可以在其它电路中被省略。
接下来,根据一实施方式,第一盖电介质材料471可以形成在金属图案461上并被平坦化。
图12A至图12C分别示出根据一实施方式的其中形成源极/漏极接触结构的半导体器件的两个剖视图和俯视平面图。
图12A是沿着图12C中的线X-X’截取的半导体器件1200的剖视图,图12C是半导体器件1200的俯视平面图,图12B是沿着图12C中的线Y-Y’截取的半导体器件1200的剖视图。这里要注意,图12C所示的线X-X’和Y-Y’对应于在俯视平面图中的半导体器件1200的中心线(像图4C至图8C的线X-X’和Y-Y’)处的截面。
参照图12A至图12C,第一纳米片层410C和第二纳米片层420C现在分别被第一置换金属栅极415和第二置换金属栅极425完全围绕,以构建第一纳米片晶体管401和第二纳米片晶体管402。此外,第一源极/漏极接触结构421至第四源极/漏极接触结构424分别形成在第一源极/漏极区411至第四源极/漏极区414上,以将第一纳米片晶体管401和第二纳米片晶体管402连接到其它电路元件或电源。此外,在第二置换金属栅极425之上形成栅极金属接触462、第二盖电介质材料472和栅极接触结构426。还形成附加的ILD层443以使第一源极/漏极接触结构421和第二源极/漏极接触结构422与栅极接触结构426彼此绝缘。
制造用于参照图4A-图4C至图12A-图12C的半导体器件1200的多堆叠纳米片结构的步骤可以不按上述顺序执行。例如,尽管在形成第一源极/漏极区411至第四源极/漏极区414之后形成第一置换金属栅极415和第二置换金属栅极425,但是根据实施方式,可以在形成第一源极/漏极区411至第四源极/漏极区414之前形成第一置换金属栅极415和第二置换金属栅极425。此外,上述多堆叠纳米片结构具有第一纳米片堆叠410和第二纳米片堆叠420并使它们的沟道组彼此垂直地交叉,根据实施方式,这两个沟道组可以以不同的角度交叉。
至此,已经关于制造多堆叠纳米片结构描述了本发明构思。然而,本发明构思不限于此,而是,根据实施方式,可以应用于制造不同类型的多堆叠晶体管结构,诸如混合多堆叠晶体管结构(其中上晶体管堆叠可以是finFET堆叠或纳米片堆叠,而下晶体管堆叠是纳米片堆叠)。
图13示出根据一实施方式的制造参照图4A-图4C至图12A-图12C的具有多堆叠晶体管结构的半导体器件的方法的流程图。
在操作S10中,提供半导体器件结构,该半导体器件结构包括基板、形成在基板上的第一晶体管堆叠以及形成在第一晶体管堆叠上的第二晶体管堆叠,其中第一晶体管堆叠可以包括多个第一沟道结构,第二晶体管堆叠可以包括多个第二沟道结构(见例如图4A-图4C)。
在操作S20中,形成第一虚设栅极以围绕第一晶体管堆叠,以及在第一虚设栅极上形成第二虚设栅极以围绕第二晶体管堆叠和第二晶体管堆叠的顶表面(见例如图5A-图5C)。
在操作S30中,去除在第一晶体管堆叠的四个侧面当中的至少第一侧面和第二侧面的至少部分上的第一虚设栅极,以及分别在第一晶体管堆叠的其中去除第一虚设栅极的第一侧面和第二侧面上形成第一源极/漏极区和第二源极/漏极区(见例如图6A-图6C和图7A-图7C)。
在操作S40中,去除在第二晶体管堆叠的四个侧面当中的至少第三侧面和第四侧面的至少部分上的第二虚设栅极,然后分别在第二晶体管堆叠的其中去除第二虚设栅极的第三侧面和第四侧面上形成第三源极/漏极区和第四源极/漏极区(见例如图6A-图6C和图7A-图7C)。这里,可以在去除第一虚设栅极之前去除第二虚设栅极,而且可以在形成第三源极/漏极区和第四源极/漏极区之前形成第一源极/漏极区和第二源极/漏极区(见例如图6A-图6C和图8A-图8C)。
在操作S50中,第一晶体管堆叠的第一源极/漏极区和第二源极/漏极区通过隔离层而与第三源极/漏极区和第四源极/漏极区隔离(见例如图8A-图8C)。
在操作S60中,在第二晶体管堆叠的顶表面上形成ILD层(见例如图9A-图9C)。
在操作S70中,去除剩余的第一虚设栅极和剩余的第二虚设栅极(见例如图10A-图10C和图11A和图11C)。在此时,可以首先去除第一虚设栅极,然后可以去除第二虚设栅极。具体地,可以在第二虚设栅极的至少一个边缘区域之一处形成孔以通过该孔暴露第一虚设栅极,并且可以通过该孔去除第一虚设栅极。
在操作S80中,通过第一虚设栅极和第二虚设栅极的去除而形成的空的空间分别用第一置换金属栅极和第二置换金属栅极填充,以形成分别围绕被包括在第一晶体管堆叠和第二晶体管堆叠中的第一沟道结构和第二沟道结构的第一栅极结构和第二栅极结构(见例如图10A-图10C和图11A和图11C)。具体地,第一置换金属栅极可以通过在之前的操作中形成的孔而填充在该空间中以围绕第一沟道结构从而形成第一栅极结构。此孔也可以填充有第一置换金属栅极。然后,第二置换金属栅极可以填充剩余的空间以围绕第二沟道结构从而形成第二栅极结构。作为此操作的结果,第一源极/漏极区至第四源极/漏极区可以被形成为使得第三源极/漏极区不与第一源极/漏极区或第二源极/漏极区重叠并且第四源极/漏极区不与第一源极/漏极区或第二源极/漏极区重叠。
在操作S90中,在至少第二栅极结构上形成栅极接触结构,并且第一源极/漏极接触结构至第四源极/漏极接触结构形成为分别着落在第一源极/漏极区至第四源极/漏极区上(见例如图12A-图12C)。通过这种方法,第一源极/漏极接触结构和第二源极/漏极接触结构不需要被弯曲以分别连接到第一源极/漏极区和第二源极/漏极区,或者不需要分别着落在第一源极/漏极区的侧表面和第二源极/漏极区的侧表面上。替代地,第一源极/漏极接触结构至第四源极/漏极接触结构可以形成为从形成在第二晶体管堆叠之上的结构(诸如上金属图案)分别着落在第一源极/漏极区至第四源极/漏极区的顶表面上。
图14A示出根据一实施方式的半导体模块的示意平面图。
参照图14A,根据一实施方式的半导体模块500可以包括安装在模块基板510上的处理器520和半导体器件530。处理器520和/或半导体器件530可以包括一个或更多个在以上实施方式中描述的多堆叠晶体管结构。
图14B示出根据一实施方式的电子系统的示意框图。
参照图14B,根据一实施方式的电子系统600可以包括使用总线640执行数据通信的微处理器610、存储器620和用户接口630。微处理器610可以包括中央处理器(CPU)或应用处理器(AP)。电子系统600还可以包括与微处理器610直接通信的随机存取存储器(RAM)650。微处理器610和/或RAM 650可以被实现在单个模块或封装中。用户接口630可以用于向电子系统600输入数据,或者从电子系统600输出数据。例如,用户接口630可以包括键盘、触摸板、触摸屏、鼠标、扫描仪、语音检测器、液晶显示器(LCD)、微发光器件(LED)、有机发光二极管(OLED)装置、有源矩阵发光二极管(AMOLED)装置、打印机、照明装置或各种其它输入/输出装置,而没有限制。存储器620可以存储微处理器610的操作代码、由微处理器610处理的数据、或从外部装置接收的数据。存储器620可以包括存储器控制器、硬盘或固态驱动器(SSD)。
电子系统600中的至少微处理器610、存储器620和/或RAM 650可以包括一个或更多个在以上实施方式中描述的多堆叠晶体管结构。
由于上述交叉的多堆叠晶体管结构具有不同的沟道方向,半导体器件结构可以省去用于侧向连接到下堆叠晶体管结构的源极/漏极区的被弯曲的源极/漏极接触结构,从而能够使具有着落在相应的源极/漏极区的顶表面上的源极/漏极接触结构的半导体器件结构的制造更加容易。此外,所公开的结构能够减小在下堆叠(上堆叠)晶体管结构的源极/漏极区与上堆叠(下堆叠)的源极/漏极接触结构之间的寄生电容。
以上是对示范性实施方式的说明,将不被解释为对其进行限制。例如,可以省略用于制造SuperVia的上述一个或更多个步骤,以简化工艺。尽管已经描述了一些示范性实施方式,但是本领域技术人员将易于理解,在以上实施方式中可以有许多修改,而实质上没有脱离本发明构思。
本申请基于2020年10月2日在美国专利和商标局提交的美国临时申请第63/086763号并要求其优先权,其公开内容通过引用整体地结合于此。
Claims (30)
1.一种半导体器件,包括:
基板;
第一晶体管,形成在所述基板之上,并具有第一晶体管堆叠,所述第一晶体管堆叠包括多个第一沟道结构、围绕所述多个第一沟道结构的第一栅极结构以及在所述第一晶体管堆叠的在第一沟道长度方向上的两端处的第一源极/漏极区和第二源极/漏极区;以及
第二晶体管,在垂直方向上形成在所述第一晶体管之上,并具有第二晶体管堆叠,所述第二晶体管堆叠包括多个第二沟道结构、围绕所述多个第二沟道结构的第二栅极结构以及在所述第二晶体管堆叠的在第二沟道长度方向上的两端处的第三源极/漏极区和第四源极/漏极区,
其中所述第三源极/漏极区不与所述第一源极/漏极区或所述第二源极/漏极区垂直地重叠,并且所述第四源极/漏极区不与所述第一源极/漏极区或所述第二源极/漏极区垂直地重叠。
2.根据权利要求1所述的半导体器件,还包括:
栅极接触结构,连接到至少所述第二栅极结构;和
第一源极/漏极接触结构至第四源极/漏极接触结构,从金属层笔直向下延伸以分别连接到所述第一源极/漏极区至所述第四源极/漏极区。
3.根据权利要求2所述的半导体器件,其中至少所述第一源极/漏极接触结构和所述第二源极/漏极接触结构分别着落在所述第一源极/漏极区的顶表面和所述第二源极/漏极区的顶表面上。
4.根据权利要求2所述的半导体器件,其中所述第一源极/漏极接触结构至所述第四源极/漏极接触结构分别着落在所述第一源极/漏极区至所述第四源极/漏极区的顶表面上。
5.根据权利要求2所述的半导体器件,其中所述第一源极/漏极接触结构和所述第二源极/漏极接触结构没有被弯曲以分别连接到所述第一源极/漏极区和所述第二源极/漏极区,或者没有分别着落在所述第一源极/漏极区的侧表面和所述第二源极/漏极区的侧表面上。
6.根据权利要求1所述的半导体器件,其中所述第一晶体管堆叠是包括多个鳍结构的鳍场效应晶体管(finFET)堆叠,以及
其中所述第二晶体管堆叠是包括多个第二纳米片层的第二纳米片堆叠。
7.根据权利要求1所述的半导体器件,其中所述第一晶体管堆叠是包括多个第一纳米片层的第一纳米片堆叠,以及
其中所述第二晶体管堆叠是包括多个第二纳米片层的第二纳米片堆叠。
8.根据权利要求7所述的半导体器件,其中所述多个第一纳米片层在第一沟道宽度方向上的宽度相同,并且所述多个第二纳米片层在第二沟道宽度方向上的宽度相同,以及
其中所述多个第一纳米片层在所述第一沟道长度方向上的长度相同,并且所述多个第二纳米片层在所述第二沟道长度方向上的长度相同。
9.根据权利要求8所述的半导体器件,其中所述多个第一纳米片层在所述第一沟道宽度方向上的所述宽度与所述多个第二纳米片层在所述第二沟道长度方向上的所述长度相同。
10.根据权利要求1所述的半导体器件,其中所述第一沟道长度方向和所述第二沟道长度方向彼此不同。
11.根据权利要求1所述的半导体器件,其中所述第一栅极结构的一部分在所述第一晶体管堆叠之上延伸到所述第二晶体管堆叠的一侧以连接到所述第二栅极结构。
12.根据权利要求1所述的半导体器件,其中在俯视平面图中,所述第二晶体管堆叠包括从所述第二晶体管堆叠的至少一个边缘突出的至少一个突起,以及
其中所述突起包括所述第一栅极结构的一部分和所述第二栅极结构的一部分。
13.一种晶体管结构,包括第一晶体管堆叠和形成在所述第一晶体管堆叠之上的第二晶体管堆叠,
其中所述第一晶体管堆叠包括被第一栅极结构围绕的多个第一沟道结构,所述第二晶体管堆叠包括被第二栅极结构围绕的多个第二沟道结构,
其中所述第一沟道结构配置为形成用于第一电流在第一沟道长度方向上流动的第一沟道,所述第二沟道结构配置为形成用于第二电流在第二沟道长度方向上流动的第二沟道,以及
其中所述第一沟道长度方向和所述第二沟道长度方向彼此不同。
14.根据权利要求13所述的晶体管结构,其中所述第一晶体管堆叠是包括多个第一纳米片层的第一纳米片堆叠,或者是包括多个鳍结构的鳍场效应晶体管(finFET)堆叠,以及
其中所述第二晶体管堆叠是包括多个第二纳米片层的第二纳米片堆叠。
15.根据权利要求13所述的晶体管结构,其中所述第一晶体管堆叠还包括第一源极/漏极区和第二源极/漏极区,所述第二晶体管堆叠还包括第三源极/漏极区和第四源极/漏极区,以及
其中所述第三源极/漏极区不与所述第一源极/漏极区或所述第二源极/漏极区垂直地重叠,并且所述第四源极/漏极区不与所述第一源极/漏极区或所述第二源极/漏极区垂直地重叠。
16.根据权利要求13所述的晶体管结构,其中所述第一栅极结构的一部分在所述第一晶体管堆叠之上延伸到所述第二晶体管堆叠的一侧以连接到所述第二栅极结构。
17.根据权利要求13所述的晶体管结构,其中所述多个第一沟道结构当中的一个第一沟道结构在所述第一沟道长度方向上的长度等于所述多个第二沟道结构当中的一个第二沟道结构在第二沟道宽度方向上的宽度,所述第二沟道宽度方向平行于所述第一沟道长度方向并垂直于所述第二沟道长度方向,以及
其中所述一个第二沟道结构在所述第二沟道长度方向上的长度等于所述一个第一沟道结构在第一沟道宽度方向上的宽度,所述第一沟道宽度方向平行于所述第二沟道长度方向并垂直于所述第一沟道长度方向。
18.根据权利要求17所述的晶体管结构,其中在俯视平面图中,所述第二晶体管堆叠包括从所述第二晶体管堆叠的至少一个边缘突出的至少一个突起,以及
其中所述突起包括所述第一栅极结构的一部分和所述第二栅极结构的一部分。
19.一种制造半导体器件的方法,所述方法包括以下操作:
(a)提供半导体器件结构,该半导体器件结构包括基板、形成在所述基板上的第一晶体管堆叠和形成在所述第一晶体管堆叠上的第二晶体管堆叠,其中所述第一晶体管堆叠和所述第二晶体管堆叠分别包括多个第一沟道结构和多个第二沟道结构;
(b)形成第一虚设栅极以围绕所述第一晶体管堆叠,并在所述第一虚设栅极上形成第二虚设栅极以围绕所述第二晶体管堆叠和所述第二晶体管堆叠的顶表面;
(c)去除在所述第一晶体管堆叠的四个侧面当中的至少第一侧面和第二侧面的至少部分上的所述第一虚设栅极,并分别在所述第一晶体管堆叠的其中去除所述第一虚设栅极的所述第一侧面和所述第二侧面上形成第一源极/漏极区和第二源极/漏极区;
(d)去除在所述第二晶体管堆叠的四个侧面当中的至少第三侧面和第四侧面的至少部分上的所述第二虚设栅极,并分别在所述第二晶体管堆叠的其中去除所述第二虚设栅极的所述第三侧面和所述第四侧面上形成第三源极/漏极区和第四源极/漏极区;以及
(e)去除剩余的第一虚设栅极和剩余的第二虚设栅极并分别用第一置换金属栅极和第二置换金属栅极替代所述剩余的第一虚设栅极和所述剩余的第二虚设栅极,以形成分别围绕所述第一沟道结构和所述第二沟道结构的第一栅极结构和第二栅极结构,
其中所述第一源极/漏极区至所述第四源极/漏极区形成为使得所述第三源极/漏极区不与所述第一源极/漏极区或所述第二源极/漏极区重叠,并且所述第四源极/漏极区不与所述第一源极/漏极区或所述第二源极/漏极区重叠。
20.根据权利要求19所述的方法,还包括:
(f)在所述第二栅极结构上形成栅极接触结构;以及
(g)形成第一源极/漏极接触结构至第四源极/漏极接触结构以分别着落在所述第一源极/漏极区至所述第四源极/漏极区上,
其中所述第一源极/漏极接触结构和所述第二源极/漏极接触结构没有被弯曲以分别连接到所述第一源极/漏极区和所述第二源极/漏极区,或者没有分别着落在所述第一源极/漏极区的侧表面和所述第二源极/漏极区的侧表面上。
21.根据权利要求20所述的方法,在操作(g)中,至少所述第一源极/漏极接触结构和所述第二源极/漏极接触结构形成为分别着落在所述第一源极/漏极区的顶表面和所述第二源极/漏极区的顶表面上。
22.根据权利要求20所述的方法,在操作(g)中,所述第一源极/漏极接触结构至所述第四源极/漏极接触结构形成为分别着落在所述第一源极/漏极区至所述第四源极/漏极区的顶表面上。
23.根据权利要求19所述的方法,其中操作(e)包括:
(e-1)去除所述剩余的第一虚设栅极并用所述第一置换金属栅极替代所述剩余的第一虚设栅极,以形成用于所述第一晶体管堆叠的所述第一栅极结构;以及
(e-2)在操作(e-1)之后,去除所述剩余的第二虚设栅极并用所述第二置换金属栅极替代所述剩余的第二虚设栅极,以形成用于所述第二晶体管堆叠的所述第二栅极结构。
24.根据权利要求23所述的方法,
其中,在操作(c)中,在所述第一晶体管堆叠的至少所述第一侧面和所述第二侧面的每个的一部分处去除所述第一虚设栅极,以及
其中,在操作(d)中,在所述第二晶体管堆叠的至少所述第三侧面和所述第四侧面的每个的一部分处去除所述第二虚设栅极。
25.根据权利要求24所述的方法,其中在操作(c)之前执行操作(d),以及
其中,在所述第二晶体管堆叠的至少所述第三侧面和所述第四侧面的每个的所述部分处去除所述第二虚设栅极之后,所述第二虚设栅极的至少一个边缘区域保留而没有被去除。
26.根据权利要求24所述的方法,其中在操作(c)之前执行操作(d),以及
其中,在操作(d)中,在所述第二晶体管堆叠的包括所述第三侧面和所述第四侧面的四个侧面的一部分处去除所述第二虚设栅极,并且所述第二虚设栅极的四个边缘区域保留而没有被去除。
27.根据权利要求25所述的方法,其中被去除的第二虚设栅极在与所述第二晶体管堆叠的沟道宽度方向平行的方向上的长度不大于所述第二沟道结构的宽度。
28.根据权利要求25所述的方法,其中操作(e)包括:
(e-1)在所述第二虚设栅极的所述至少一个边缘区域之一处形成孔以通过所述孔暴露所述第一虚设栅极;
(e-2)通过所述孔去除所述剩余的第一虚设栅极;以及
(e-3)通过所述孔形成所述第一置换金属栅极。
29.根据权利要求28所述的方法,还包括:
(e-4)在所述孔中形成所述第一置换金属栅极;以及
(e-5)将形成在所述孔处的所述第一置换金属栅极与所述第二置换金属栅极连接。
30.根据权利要求19所述的方法,其中所述第一源极/漏极区至所述第四源极/漏极区被形成为使得所述第一沟道结构的沟道长度方向垂直于所述第二沟道结构的沟道长度方向。
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