CN114387926B

CN114387926B - Pixel circuit, driving method thereof and display device

Info

Publication number: CN114387926B
Application number: CN202210177668.8A
Authority: CN
Inventors: 陈凯; 陈沫; 韩飞; 吴旺娣; 李方庆; 高锦成; 赵洁; 鲍王婷
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Display Lighting Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Display Lighting Co Ltd
Priority date: 2022-02-24
Filing date: 2022-02-24
Publication date: 2024-04-09
Anticipated expiration: 2042-02-24
Also published as: CN114387926A

Abstract

The embodiment of the application provides a pixel circuit, a driving method thereof and a display device, relates to the technical field of display, and is used for improving the luminous stability of a luminous device. The pixel circuit includes a first switch circuit, a second switch circuit, a first driving circuit, a second driving circuit, and a light emitting device. The first switching circuit is configured to transmit a first input signal to a first node. The first driving circuit is configured to transmit a first voltage signal to a first pole of the light emitting device. The second switching circuit is configured to transmit a second input signal to the second node. The second driving circuit is configured to transmit a first voltage signal to a first electrode of the light emitting device. In the case where one of the first driving circuit and the second driving circuit transmits the first voltage signal to the first electrode of the light emitting device, the other is in an off state. The pixel circuit, the driving method thereof and the display device are used for image display.

Description

Pixel circuit, driving method thereof and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, and a display device.

Background

In the display field, an OLED (Organic Light Emitting Diode ) display device has the characteristics of self-luminescence, high contrast, low energy consumption, wide viewing angle, high response speed, wide use temperature range and the like.

Disclosure of Invention

The embodiment of the application provides a pixel circuit, a driving method thereof and a display device, which are used for improving the light-emitting stability of a light-emitting device.

In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

in a first aspect, there is provided a pixel circuit comprising: the light emitting device comprises a first switch circuit, a second switch circuit, a first driving circuit, a second driving circuit and a light emitting device. The first switch circuit is coupled to the first control signal terminal, the first input signal terminal and the first node. The first switching circuit is configured to transmit a first input signal provided by the first input signal terminal to the first node under control of a first control signal provided by the first control signal terminal. The first driving circuit is coupled to the first node, the first voltage signal terminal, and the first electrode of the light emitting device. The first driving circuit is configured to transmit a first voltage signal provided by the first voltage signal terminal to a first pole of the light emitting device under control of a voltage of the first node. The second switch circuit is coupled to the second control signal terminal, the second input signal terminal and the second node. The second switching circuit is configured to transmit a second input signal provided by the second input signal terminal to the second node under control of a second control signal provided by the second control signal terminal. The second driving circuit is coupled to the second node, the first voltage signal terminal, and the first electrode of the light emitting device. The second driving circuit is configured to transmit the first voltage signal to a first pole of the light emitting device under control of a voltage of the second node. Wherein, in a case where one of the first driving circuit and the second driving circuit transmits the first voltage signal to the first electrode of the light emitting device, the other is in an off state.

The present application sets a pixel circuit to include: the first switch circuit, the second switch circuit, the first driving circuit, the second driving circuit and the light emitting device may enable the first switch circuit to transmit the first input signal to the first node by controlling the level of the first control signal provided by the first control signal terminal and the level of the first input signal provided by the first input signal terminal. Further, under the control of the voltage of the first node, the first driving circuit is in a conducting state, a first voltage signal of the first node is transmitted to a first pole of the light emitting device, and the light emitting device is driven to emit light, at the moment, the first driving circuit is in a positive bias state, and the threshold voltage of a transistor included in the first driving circuit can drift forward; or the first driving circuit is in an off state, and at this time, the first driving circuit is in a negative bias state, and the threshold voltage of the transistor included in the first driving circuit may drift negatively.

The second switch circuit may also be configured to transmit the second input signal to the second node by controlling the level of the second control signal provided by the second control signal terminal and the level of the second input signal provided by the second input signal terminal. Further, under the control of the voltage of the second node, the second driving circuit is in a conducting state, a first voltage signal of the second node is transmitted to a first pole of the light emitting device, and the light emitting device is driven to emit light, at the moment, the second driving circuit is in a positive bias state, and the threshold voltage of a transistor included in the second driving circuit can drift forward; or the second driving circuit is in an off state, and at this time, the second driving circuit is in a negative bias state, and the threshold voltage of the transistor included in the second driving circuit may drift negatively.

By alternately placing the first drive circuit and the second drive circuit in an on state, when one of the first drive circuit and the second drive circuit is in a positive bias state (or a negative bias state), the other is in a negative bias state (or a positive bias state). That is, the threshold voltages of the transistors included in the first driving circuit alternately drift in the positive direction and drift in the negative direction, and the threshold voltages of the transistors included in the second driving circuit alternately drift in the negative direction and drift in the positive direction, so that the total drift amount of the threshold voltages can be reduced by using the offset of the positive drift amount and the negative drift amount of the threshold voltages, the stability of the value of the driving signal generated by the driving transistor can be further enhanced, and the light emitting stability of the light emitting device can be improved.

In some embodiments, the first switching circuit comprises: and a first transistor, wherein a gate of the first transistor is coupled to the first control signal terminal, a first pole of the first transistor is coupled to the first input signal terminal, and a second pole of the first transistor is coupled to the first node. The first driving circuit includes: a second transistor and a first capacitor. The gate of the second transistor is coupled to the first node, the first pole of the second transistor is coupled to the first voltage signal terminal, and the second pole of the second transistor is coupled to the first pole of the light emitting device. A first pole of the first capacitor is coupled to the first node, and a second pole of the first capacitor is coupled to the first pole of the light emitting device. The second switching circuit includes: and a third transistor, a gate of the third transistor is coupled to the second control signal terminal, a first pole of the third transistor is coupled to the second input signal terminal, and a second pole of the third transistor is coupled to the second node. The second driving circuit includes: a fourth transistor and a second capacitor. The gate of the fourth transistor is coupled to the second node, the first pole of the fourth transistor is coupled to the first voltage signal terminal, and the second pole of the fourth transistor is coupled to the first pole of the light emitting device. A first pole of the second capacitor is coupled to the second node, and a second pole of the second capacitor is coupled to the first pole of the light emitting device.

In some embodiments, the pixel circuit further comprises a first selection circuit and a second selection circuit. The first selection circuit is coupled to the first voltage signal terminal, the second voltage signal terminal, the third voltage signal terminal, the fourth voltage signal terminal, the scanning signal terminal, the data signal terminal, the first control signal terminal and the first input signal terminal. The first selection circuit is configured to transmit the first voltage signal to the first control signal terminal and transmit the fourth voltage signal provided by the fourth voltage signal terminal to the first input signal terminal under the control of the second voltage signal provided by the second voltage signal terminal; or under the control of the third voltage signal provided by the third voltage signal end, transmitting the scanning signal provided by the scanning signal end to the first control signal end, and transmitting the data signal provided by the data signal end to the first input signal end. The second selection circuit is coupled to the first voltage signal terminal, the fifth voltage signal terminal, the sixth voltage signal terminal, the fourth voltage signal terminal, the scan signal terminal, the data signal terminal, the second control signal terminal, and the second input signal terminal. The second selection circuit is configured to transmit the first voltage signal to the second control signal terminal and the fourth voltage signal to the second input signal terminal under the control of a fifth voltage signal provided by the fifth voltage signal terminal; or, under the control of a sixth voltage signal provided by the sixth voltage signal terminal, transmitting the scan signal to the second control signal terminal, and transmitting the data signal to the second input signal terminal.

In some embodiments, the first selection circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The grid electrode of the fifth transistor is coupled with the second voltage signal end, the first electrode of the fifth transistor is coupled with the first voltage signal end, and the second electrode of the fifth transistor is coupled with the first control signal end. The gate of the sixth transistor is coupled to the third voltage signal terminal, the first pole of the sixth transistor is coupled to the scan signal terminal, and the second pole of the sixth transistor is coupled to the first control signal terminal. The gate of the seventh transistor is coupled to the second voltage signal terminal, the first pole of the seventh transistor is coupled to the fourth voltage signal terminal, and the second pole of the seventh transistor is coupled to the first input signal terminal. The gate of the eighth transistor is coupled to the third voltage signal terminal, the first pole of the eighth transistor is coupled to the data signal terminal, and the second pole of the eighth transistor is coupled to the first input signal terminal. The second selection circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor. The gate of the ninth transistor is coupled to the fifth voltage signal terminal, the first pole of the ninth transistor is coupled to the first voltage signal terminal, and the second pole of the ninth transistor is coupled to the second control signal terminal. The gate of the tenth transistor is coupled to the sixth voltage signal terminal, the first pole of the tenth transistor is coupled to the scan signal terminal, and the second pole of the tenth transistor is coupled to the second control signal terminal. The gate of the eleventh transistor is coupled to the fifth voltage signal terminal, the first pole of the eleventh transistor is coupled to the fourth voltage signal terminal, and the second pole of the eleventh transistor is coupled to the second input signal terminal. The gate of the twelfth transistor is coupled to the sixth voltage signal terminal, the first pole of the twelfth transistor is coupled to the data signal terminal, and the second pole of the twelfth transistor is coupled to the second input signal terminal.

In some embodiments, the first selection circuit includes transistors of the same type as the second selection circuit. The second voltage signal and the fifth voltage signal are mutually opposite signals; the third voltage signal and the sixth voltage signal are mutually opposite signals.

In some embodiments, the second voltage signal and the sixth voltage signal are the same signal; the third voltage signal and the fifth voltage signal are the same signal.

In some embodiments, the first selection circuit includes a type of transistor that is different from the type of transistor included in the second selection circuit. The second voltage signal and the fifth voltage signal are the same signals; the third voltage signal and the sixth voltage signal are the same signal.

In some embodiments, the second voltage signal and the sixth voltage signal are mutually inverted signals; the third voltage signal and the fifth voltage signal are mutually opposite signals.

In some embodiments, the pixel circuit further comprises a sensing circuit. The sensing circuit is coupled with the first pole of the light emitting device, the third control signal terminal and the sensing signal terminal. The sensing circuit is configured to detect a threshold voltage of the second transistor or the fourth transistor under the control of a third control signal provided by the third control signal terminal.

In some embodiments, the sensing circuit includes a thirteenth transistor. The gate of the thirteenth transistor is coupled to the third control signal terminal, the first electrode of the thirteenth transistor is coupled to the first electrode of the light emitting device, and the second electrode of the thirteenth transistor is coupled to the sensing signal terminal.

In a second aspect, a driving method of a pixel circuit for the pixel circuit according to the first aspect is described above. The driving method of the pixel circuit includes a plurality of first stages and second stages which alternate in sequence. In the first stage, the first switch circuit transmits a first input signal provided by the first input signal terminal to the first node in response to a first control signal provided by the first control signal terminal. The first driving circuit transmits a first voltage signal provided by a first voltage signal terminal to a first pole of the light emitting device under the control of the voltage of the first node. The second driving circuit is in an off state. In the second stage, the second switch circuit transmits a second input signal provided by the second input signal terminal to the second node in response to a second control signal provided by the second control signal terminal. The second driving circuit transmits the first voltage signal to a first electrode of the light emitting device under control of a voltage of the second node. The first driving circuit is in an off state.

The driving method of the pixel circuit provided by the application has similar beneficial effects to those of the pixel circuit provided by the technical scheme, and is not repeated herein.

In some embodiments, in the first stage, in response to a third voltage signal provided by a third voltage signal terminal, the first selection circuit transmits a scan signal provided by a scan signal terminal to the first control signal terminal and transmits a data signal provided by a data signal terminal to the first input signal terminal. The first switching circuit transmits the data signal as the first input signal to the first node under control of the first control signal. The first driving circuit transmits the first voltage signal to a first pole of the light emitting device under control of a voltage of the first node. In response to a fifth voltage signal provided by a fifth voltage signal terminal, the second selection circuit transmits a first voltage signal provided by a first voltage signal terminal to the second control signal terminal, and transmits a fourth voltage signal provided by a fourth voltage signal terminal to the second input signal terminal. The second switching circuit transmits the fourth voltage signal as the second input signal to the second node under the control of the second control signal, and the second driving circuit is turned off under the control of the voltage of the second node and is in a cut-off state. In the second stage, the second selection circuit transmits the scan signal to the second control signal terminal and the data signal to the second input signal terminal in response to a sixth voltage signal provided from a sixth voltage signal terminal. The second switching circuit transmits the data signal as the second input signal to the second node under control of the second control signal. The second driving circuit transmits the first voltage signal to a first electrode of the light emitting device under control of a voltage of the second node. The first selection circuit transmits the first voltage signal to the first control signal terminal and the fourth voltage signal to the first input signal terminal in response to a second voltage signal provided by a second voltage signal terminal. The first switching circuit transmits the fourth voltage signal as the first input signal to the first node under the control of the first control signal, and the first driving circuit is turned off under the control of the voltage of the first node and is in a cut-off state.

In some embodiments, the first stage is less than or equal to 1/4 second; the second stage is less than or equal to 1/4 second.

In some embodiments, the first phase is equal in duration to the second phase.

In a third aspect, embodiments of the present application provide a display device, where the display device includes a substrate, a plurality of pixel circuits as described in the first aspect above, and a cover plate. The plurality of pixel circuits are arranged on one side of the substrate, and the cover plate is arranged on one side of the plurality of pixel circuits away from the substrate.

The display device provided by the application has similar beneficial effects to those of the pixel circuit provided by the technical scheme, and the detailed description is omitted herein.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a block diagram of a pixel circuit according to some embodiments of the present application;

FIG. 2 is a circuit diagram of a pixel circuit according to some embodiments of the present application;

FIG. 3 is a graph of voltage versus current after a period of forward bias for a transistor according to some embodiments of the present application;

FIG. 4 is a graph of voltage versus current after a period of negative bias for a transistor according to some embodiments of the present application;

FIG. 5 is a block diagram of another pixel circuit provided in some embodiments of the present application;

FIG. 6 is a circuit diagram of another pixel circuit provided in some embodiments of the present application;

FIG. 7 is a circuit diagram of yet another pixel circuit provided in some embodiments of the present application;

FIG. 8 is a schematic diagram of a further pixel circuit according to some embodiments of the present application;

FIG. 9 is a circuit diagram of yet another pixel circuit provided in some embodiments of the present application;

FIG. 10 is a circuit diagram of yet another pixel circuit provided in some embodiments of the present application;

FIG. 11 is a timing diagram of a pixel circuit according to some embodiments of the present disclosure;

fig. 12 is a block diagram of a display device according to some embodiments of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," "particular examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

"A and/or B" includes the following three combinations: only a, only B, and combinations of a and B.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

In the circuit structures (for example, pixel circuits) provided in the embodiments of the present application, the transistors may be thin film transistors (Thin Film Transistor, abbreviated as TFTs), field effect transistors (Metal Oxide Semiconductor, abbreviated as MOS) or other switching devices with the same characteristics, and the thin film transistors are taken as examples in the embodiments of the present application.

In the circuit structure provided by the embodiment of the application, the first pole of each transistor is one of a source electrode and a drain electrode, and the second pole of each transistor is the other of the source electrode and the drain electrode. Since the source and drain of a transistor may be symmetrical in structure, the source and drain may be indistinguishable in structure, that is, the first and second poles of the transistor in embodiments of the present application may be indistinguishable in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

In the circuit structure provided in the embodiments of the present application, the first node, the second node, and the like are not nodes representing actually existing components, but represent junction points of related coupling in the circuit diagram, that is, the nodes are equivalent nodes formed by the junction points of the related coupling in the circuit diagram.

The pixel circuit generally includes a light emitting device and a pixel driving circuit for driving the light emitting device to emit light.

In one implementation, the pixel driving circuit includes only one driving transistor. In the process of driving the light emitting device by the pixel driving circuit to emit light, a voltage difference Vgs exists between the gate and the source of the driving transistor, and the driving transistor is in a conductive state. As the operating time of the driving transistor increases, the threshold voltage thereof may drift under the action of the voltage difference Vgs, thereby causing the value of the driving signal generated by the driving transistor to become smaller, resulting in a decrease in the light emission luminance of the light emitting device and a decrease in the light emission stability of the light emitting device.

Taking the driving transistor as an N-type transistor as an example, when the driving transistor is in an on state, the voltage difference Vgs is a positive value, and the driving transistor is in a forward bias state. After the driving transistor is in the forward bias state for a period of time, the threshold voltage of the driving transistor becomes large, that is, the threshold voltage of the driving transistor has a forward drift. Thus, the light emitting device is caused to emit unstable light.

Based on this, the embodiment of the present application provides a pixel circuit 100, referring to fig. 1 and 2, the pixel circuit 100 includes: the first switching circuit 10, the second switching circuit 20, the first driving circuit 30, the second driving circuit 40, and the light emitting device L.

In the embodiment of the present application, the light emitting device L in the pixel circuit 100 may be an organic light emitting diode (Organic Light Emitting Diode, OLED), a quantum dot light emitting diode (Quantum Dot Light Emitting Diode, QLED), a Micro light emitting diode (Micro Light Emitting Diode, micro LED), a Mini light emitting diode (Mini Light Emitting Diode, mini LED), or the like.

In some examples, referring to fig. 1 and 2, the first switch circuit 10 is coupled to the first control signal terminal a, the first input signal terminal B, and the first node N1. The first switching circuit 10 is configured to transmit the first input signal provided by the first input signal terminal B to the first node N1 under the control of the first control signal provided by the first control signal terminal a. The first driving circuit 30 is coupled to the first node N1, the first voltage signal terminal Vdd, and the first electrode of the light emitting device L. The first driving circuit 30 is configured to transmit a first voltage signal supplied from the first voltage signal terminal Vdd to a first electrode of the light emitting device L under control of the voltage of the first node N1.

Illustratively, the first voltage signal terminal Vdd is configured to transmit a dc high level signal. The dc high level signal is referred to herein as a first voltage signal, and the following embodiments are the same as the first voltage signal and will not be described again.

In some examples, the first pole of the light emitting device L may be, for example, an anode, and the second pole of the light emitting device L may be, for example, a cathode. The second electrode of the light emitting device L may be coupled to the fourth voltage signal terminal Vss.

The fourth voltage signal terminal Vss is illustratively configured to transmit a dc low level signal. The dc low level signal is referred to as a fourth voltage signal, and the following embodiments are the same and will not be repeated.

Illustratively, the voltage of the first node N1 is controlled by a first input signal transmitted to the first node N1. For example, the level of the first input signal transmitted to the first node N1 is high, and accordingly, the voltage of the first node N1 is high. As another example, the level of the first input signal transmitted to the first node N1 is low, and accordingly, the voltage of the first node N1 is low.

The first driving circuit 30 can be in a conducting state by controlling the level of the first control signal and the level of the first input signal, and the first driving circuit 30 transmits the first voltage signal to the first electrode of the light emitting device L, so that the light emitting device L is driven to emit light. Alternatively, the first driving circuit 30 may be in the off state by adjusting the level of the first control signal and the level of the first input signal.

In some examples, referring to fig. 1 and 2, the second switch circuit 20 is coupled to the second control signal terminal C, the second input signal terminal D, and the second node N2. The second switching circuit 20 is configured to transmit the second input signal provided by the second input signal terminal D to the second node N2 under the control of the second control signal provided by the second control signal terminal C. The second driving circuit 40 is coupled to the second node N2, the first voltage signal terminal Vdd and the first electrode of the light emitting device L. The second driving circuit 20 is configured to transmit a first voltage signal to a first pole of the light emitting device L under control of a voltage of the second node N2.

Illustratively, the voltage of the second node N2 is controlled by a second input signal transmitted to the second node N2. For example, the level of the second input signal transmitted to the second node N2 is high, and correspondingly, the voltage of the second node N2 is high. As another example, the level of the second input signal transmitted to the second node N2 is low, and correspondingly, the voltage of the second node N2 is low.

The second driving circuit 40 can be in a conducting state by controlling the level of the second control signal and the level of the second input signal, and the second driving circuit 40 transmits the first voltage signal to the first electrode of the light emitting device L, so that the light emitting device L is driven to emit light. Alternatively, the second driving circuit 40 may be turned off by adjusting the level of the second control signal and the level of the second input signal.

In some embodiments of the present application, in the case where one of the first driving circuit 30 and the second driving circuit 40 transmits the first voltage signal to the first electrode of the light emitting device L, the other is in the off state.

For example, in a case where the first driving circuit 30 transmits the first voltage signal to the first electrode of the light emitting device L and drives the light emitting device L to emit light, the second driving circuit 40 is in an off state.

Accordingly, the level of the first input signal controlling the voltage of the first node N1 is opposite to the level of the second input signal controlling the voltage of the second node N2, and a voltage difference exists between the voltage of the first node N1 and the voltage value of the first voltage signal, and a voltage difference exists between the voltage of the second node N2 and the voltage value of the first voltage signal.

For example, the level of the first input signal controlling the voltage of the first node N1 is a high level, and the level of the second input signal controlling the voltage of the second node N2 is a low level. At this time, the first driving circuit 30 is in a forward bias state, and the threshold voltage of the transistor included in the first driving circuit 30 may drift forward; the second driving circuit 40 is in a negative bias state, and the threshold voltage of the transistors included in the second driving circuit 40 may drift negatively.

As another example, the level of the first input signal controlling the voltage of the first node N1 is a low level, and the level of the second input signal controlling the voltage of the second node N2 is a high level. At this time, the second driving circuit 40 is in a forward bias state, and the threshold voltage of the transistor included in the second driving circuit 40 may drift forward; the first driving circuit 30 is in a negative bias state, and the threshold voltage of the transistors included in the first driving circuit 30 may drift negatively.

For example, in a case where the second driving circuit 40 transmits the first voltage signal to the first electrode of the light emitting device L and drives the light emitting device L to emit light, the first driving circuit 30 is in an off state.

For example, the level of the second input signal controlling the voltage of the second node N2 is a high level, and the level of the first input signal controlling the voltage of the first node N1 is a low level. At this time, the second driving circuit 40 is in a forward bias state, and the threshold voltage of the transistor included in the second driving circuit 40 may drift forward; the first driving circuit 30 is in a negative bias state, and the threshold voltage of the transistors included in the first driving circuit 30 may drift negatively.

As another example, the level of the second input signal controlling the voltage of the second node N2 is a low level, and the level of the first input signal controlling the voltage of the first node N1 is a high level. At this time, the first driving circuit 30 is in a forward bias state, and the threshold voltage of the transistor included in the first driving circuit 30 may drift forward; the second driving circuit 40 is in a negative bias state, and the threshold voltage of the transistors included in the second driving circuit 40 may drift negatively.

Since the first driving circuit 30 and the second driving circuit 40 are alternately in the on state, when one of the first driving circuit 30 and the second driving circuit 40 is in the positive bias state (or the negative bias state), the other is in the negative bias state (or the positive bias state). That is, the threshold voltages of the transistors included in the first driving circuit 30 may alternately drift in the positive direction and drift in the negative direction, and the threshold voltages of the transistors included in the second driving circuit 40 may alternately drift in the negative direction and drift in the positive direction, so that the total drift amount of the threshold voltages can be reduced by using the offset of the positive direction drift amount and the negative direction drift amount of the threshold voltages, thereby enhancing the stability of the value of the driving signal generated by the driving transistor and improving the light emitting stability of the light emitting device L.

In this application, the structures of the first switch circuit 10, the second switch circuit 20, the first driving circuit 30, and the second driving circuit 40 include various structures, and can be selectively set according to actual needs. The structures of the first switch circuit 10, the second switch circuit 20, the first driving circuit 30, and the second driving circuit 40 will be schematically described with reference to fig. 2, wherein the structures 40 of the first switch circuit 10, the second switch circuit 20, the first driving circuit 30, and the second driving circuit are not limited to the examples of the present application.

In some examples, referring to fig. 2, the first switching circuit 10 includes: a first transistor T1.

Illustratively, the gate of the first transistor T1 is coupled to the first control signal terminal a, the first pole of the first transistor T1 is coupled to the first input signal terminal B, and the second pole of the first transistor T1 is coupled to the first node N1.

For example, in the case that the level of the first control signal is an active level, the first transistor T1 may be turned on under the control of the first control signal, and receive and transmit the first output signal to the first node N1.

In some examples, referring to fig. 2, the first driving circuit 30 includes: a second transistor T2 and a first capacitor C1.

Illustratively, the gate of the second transistor T2 is coupled to the first node N1, the first electrode of the second transistor T2 is coupled to the first voltage signal terminal Vdd, and the second electrode of the second transistor T2 is coupled to the first electrode of the light emitting device L.

For example, in case that the level of the first node N1 is an active level, the second transistor T2 may be turned on under the control of the signal of the level of the first node N1, and receive and transmit the first voltage signal to the first electrode of the light emitting device L.

Illustratively, a first pole of the first capacitor C1 is coupled to the first node N1, and a second pole of the first capacitor C1 is coupled to a first pole of the light emitting device L.

For example, the first capacitor C1 may store charge during the turn-on of the first transistor T1. After the first transistor T1 is turned off, the first capacitor C1 may be discharged to maintain the voltage of the first node N1, so that the second transistor T2 is kept in an on state or an off state.

In some examples, referring to fig. 2, the second switching circuit 20 includes: and a third transistor T3.

Illustratively, the gate of the third transistor T3 is coupled to the second control signal terminal C, the first pole of the third transistor T3 is coupled to the second input signal terminal D, and the second pole of the third transistor T3 is coupled to the second node N2.

For example, in the case that the level of the second control signal is an active level, the third transistor T3 may be turned on under the control of the second control signal, and receive and transmit the second output signal to the second node N2.

In some examples, referring to fig. 2, the second driving circuit includes: a fourth transistor T4 and a second capacitor C2.

Illustratively, the gate of the fourth transistor T4 is coupled to the second node, the first pole of the fourth transistor T4 is coupled to the first voltage signal terminal Vdd, and the second pole of the fourth transistor T4 is coupled to the first pole of the light emitting device L.

For example, in case that the level of the second node N2 is an active level, the fourth transistor T4 may be turned on under the control of a signal of the level of the second node N2, and receive and transmit the first voltage signal to the first electrode of the light emitting device L.

Illustratively, a first pole of the second capacitor C2 is coupled to the second node N2, and a second pole of the second capacitor C2 is coupled to a first pole of the light emitting device L.

For example, the second capacitor C2 may store charge during the turn-on of the third transistor T3. After the third transistor T3 is turned off, the second capacitor C2 may be discharged to maintain the voltage of the second node N2, so that the fourth transistor T4 maintains the on state or the off state.

The transistors included in each of the above-described circuits may be N-type transistors or P-type transistors, which are not limited in this application.

In this application, the "active level" refers to a level at which a transistor can be turned on. In the case where the transistor is an N-type transistor, the "effective level" is a high level; in the case of a P-type transistor, the "active level" is low.

It will be appreciated that, referring to fig. 2, if the second transistor T2 and the fourth transistor T4 are both N-type transistors, the second transistor T2 is in a forward bias state when the second transistor T2 is in an on state, and after a period of time, referring to fig. 3, the voltage-current curve of the second transistor T2 is changed from S1 to S2, that is, the threshold voltage of the second transistor T2 is shifted forward. With the fourth transistor T4 in the off state, the fourth transistor T4 is in a negative bias state, and after a period of time, referring to fig. 4, the voltage-current curve of the fourth transistor T4 will change from S3 to S4, i.e. the threshold voltage of the fourth transistor T4 has a negative shift.

It can be appreciated that in the case where the second transistor T2 is in the off state, the threshold voltage of the second transistor T2 will drift negatively; with the fourth transistor T4 in an on state, a forward shift of the threshold voltage of the fourth transistor T4 will occur.

It is understood that the threshold voltage change process of the P-type transistor is opposite to that of the N-type transistor, and will not be described herein.

Referring to fig. 2, the second transistor T2 in the first driving circuit 30 and the fourth transistor T4 in the second driving circuit 40 are both N-type transistors.

In the case where one of the voltage of the first node N1 and the voltage of the second node N2 is a high voltage, the other is a low voltage. That is, in the case where one of the second transistor T2 and the fourth transistor T4 is turned on, the other is turned off.

Illustratively, the second transistor T2 is turned on and transmits a first voltage signal to the first electrode of the light emitting device L to drive the light emitting device L to emit light. At this time, the second transistor T2 is in an on state, and the fourth transistor T4 is in an off state. The threshold voltage of the second transistor T2 will drift positively and the threshold voltage of the fourth transistor T4 will drift negatively.

After a period of time, the fourth transistor T4 is turned on and transmits a first voltage signal to the first electrode of the light emitting device L to drive the light emitting device L to emit light. At this time, the fourth transistor T4 is in an on state, and the second transistor T2 is in an off state. The fourth transistor T4 threshold voltage will drift positively and the second transistor T2 threshold voltage will drift negatively.

Therefore, the negative shift of the threshold voltage of the second transistor T2 may partially or completely cancel the positive shift of the threshold voltage of the second transistor T2 occurring in the previous period of time, and the positive shift of the threshold voltage of the fourth transistor T4 may partially or completely cancel the negative shift of the threshold voltage of the fourth transistor T4 occurring in the previous period of time. Thereby reducing or eliminating threshold voltage drift of the second transistor T2 and the fourth transistor T4, reducing or eliminating variation of driving current for driving the light emitting device L to emit light, reducing or eliminating brightness variation when the light emitting device L emits light, and improving stability of light emission of the light emitting device L.

In some embodiments, referring to fig. 5-7, the pixel circuit 100 further includes a first selection circuit 50 and a second selection circuit 60.

In some examples, referring to fig. 5 to 7, the first selection circuit 50 is coupled to the first voltage signal terminal Vdd, the second voltage signal terminal V1, the third voltage signal terminal V2, the fourth voltage signal terminal Vss, the scan signal terminal Gate, the Data signal terminal Data, the first control signal terminal a and the first input signal terminal B. The first selection circuit 50 is configured to transmit the first voltage signal to the first control signal terminal a and the fourth voltage signal provided by the fourth voltage signal terminal Vss to the first input signal terminal B under the control of the second voltage signal provided by the second voltage signal terminal V1. Alternatively, under the control of the third voltage signal provided by the third voltage signal terminal V2, the scan signal provided by the scan signal terminal Gate is transmitted to the first control signal terminal a, and the Data signal provided by the Data signal terminal Data is transmitted to the first input signal terminal B.

In some examples, referring to fig. 5 to 7, the second selection circuit 60 is coupled to the first voltage signal terminal Vdd, the fifth voltage signal terminal V3, the sixth voltage signal terminal V4, the fourth voltage signal terminal Vss, the scan signal terminal Gate, the Data signal terminal Data, the second control signal terminal C and the second input signal terminal D. The second selection circuit 60 is configured to transmit the first voltage signal to the second control signal terminal C and the fourth voltage signal to the second input signal terminal D under the control of the fifth voltage signal provided by the fifth voltage signal terminal V3. Alternatively, the scan signal is transmitted to the second control signal terminal C and the data signal is transmitted to the second input signal terminal D under the control of the sixth voltage signal provided by the sixth voltage signal terminal V4.

For example, in the case that the first selection circuit 50 transmits the first voltage signal to the first control signal terminal a and the fourth voltage signal to the first input signal terminal B, the second selection circuit 60 transmits the scan signal to the second control signal terminal C and the data signal to the second input signal terminal D. The first switching circuit 10 transmits the fourth voltage signal to the first node N1 under the control of the first voltage signal transmitted to the first control signal terminal a. The second switching circuit 20 transmits the data signal to the second node N2 under the control of the scan signal transmitted to the second control signal terminal C.

Referring to fig. 6, the second transistor T2 in the first driving circuit 30 and the fourth transistor T4 in the second driving circuit 40 are both N-type transistors.

Since the fourth voltage signal is a dc low level signal, the second transistor T2 is in an off state in the case where the fourth voltage signal is transmitted to the first node N1; in the case where the data signal is transmitted to the second node N2, the fourth transistor T4 is in an on state.

For example, in the case where the first selection circuit 50 transmits the scan signal to the first control signal terminal 1 and the data signal to the first input signal terminal B, the second selection circuit 60 transmits the first voltage signal to the second control signal terminal C and the fourth voltage signal to the second input signal terminal D. The first switching circuit 10 transmits the data signal to the first node N1 under the control of the scan signal transmitted to the first control signal terminal a. The second switch circuit 20 transmits the fourth voltage signal to the second node N2 under the control of the first voltage signal transmitted to the second control signal terminal C.

The on states of the second transistor T2 and the fourth transistor T4 are opposite to the above examples, and will not be described here again.

That is, the present application can control the first driving circuit 30 and the second driving circuit 40 to be alternately in the on state or alternately in the off state by providing the first selecting circuit 50 and the second selecting circuit 60, thereby reducing the threshold voltage shift amount of the transistors in the first driving circuit 30 and the second driving circuit 40.

In this application, the structures of the first selection circuit 50 and the second selection circuit 60 include various types, and can be selected according to actual needs. The structures of the first selection circuit 50 and the second selection circuit 60 are schematically described below with reference to fig. 6 and 7, wherein the first selection circuit 50 and the second selection circuit 60 are not limited to the case exemplified in the present application.

In some examples, referring to fig. 6 and 7, the first selection circuit 50 includes: a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

Illustratively, the gate of the fifth transistor T5 is coupled to the second voltage signal terminal V1, the first pole of the fifth transistor T5 is coupled to the first voltage signal terminal Vdd, and the second pole of the fifth transistor T5 is coupled to the first control signal terminal.

For example, in the case that the level of the second voltage signal is an active level, the fifth transistor T5 may be turned on under the control of the second voltage signal, and receive and transmit the first voltage signal to the first control signal terminal a.

Illustratively, the gate of the sixth transistor T6 is coupled to the third voltage signal terminal V2, the first pole of the sixth transistor T6 is coupled to the scan signal terminal, and the second pole of the sixth transistor T6 is coupled to the first control signal terminal.

For example, in the case that the level of the third voltage signal is an active level, the sixth transistor T6 may be turned on under the control of the third voltage signal, and receive and transmit the scan signal to the first control signal terminal a.

Illustratively, the gate of the seventh transistor T7 is coupled to the second voltage signal terminal V1, the first pole of the seventh transistor T7 is coupled to the fourth voltage signal terminal Vss, and the second pole of the seventh transistor T7 is coupled to the first input signal terminal.

For example, in the case that the level of the second voltage signal is an active level, the seventh transistor T7 may be turned on under the control of the second voltage signal, and receive and transmit the fourth voltage signal to the first input signal terminal B.

Illustratively, the gate of the eighth transistor T8 is coupled to the third voltage signal terminal V2, the first pole of the eighth transistor T8 is coupled to the data signal terminal, and the second pole of the eighth transistor T8 is coupled to the first input signal terminal.

For example, in the case that the level of the third voltage signal is the active level, the eighth transistor T8 may be turned on under the control of the third voltage signal, and receive and transmit the data signal to the first input signal terminal B.

It is understood that the gates of the fifth transistor T5 and the seventh transistor T7 are coupled to the second voltage signal terminal V1, so that the fifth transistor T5 and the seventh transistor T7 can be simultaneously turned on under the control of the second voltage signal and respectively transmit corresponding electrical signals to control the on state of the first transistor T1 in the first switch circuit 10, further control the on state of the second transistor T2 in the first driving circuit 30, and adjust the threshold voltage of the second transistor T2.

It is understood that the gates of the sixth transistor T6 and the eighth transistor T8 are coupled to the third voltage signal terminal V2, so that the sixth transistor T6 and the eighth transistor T8 can be turned on simultaneously under the control of the third voltage signal and respectively transmit corresponding electrical signals to control the on state of the first transistor T1 in the first switch circuit 10, further control the on state of the second transistor T2 in the first driving circuit 30, and adjust the threshold voltage of the second transistor T2.

In some examples, referring to fig. 6 and 7, the second selection circuit 60 includes: a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12.

Illustratively, the gate of the ninth transistor T9 is coupled to the fifth voltage signal terminal V3, the first pole of the ninth transistor T9 is coupled to the first voltage signal terminal Vdd, and the second pole of the ninth transistor T9 is coupled to the second control signal terminal.

For example, in the case that the level of the fifth voltage signal is an active level, the ninth transistor T9 may be turned on under the control of the fifth voltage signal, and receive and transmit the first voltage signal to the second control signal terminal C.

Illustratively, the gate of the tenth transistor T10 is coupled to the sixth voltage signal terminal V4, the first pole of the tenth transistor T10 is coupled to the scan signal terminal, and the second pole of the tenth transistor T10 is coupled to the second control signal terminal.

For example, in the case that the level of the sixth voltage signal is the active level, the tenth transistor T10 may be turned on under the control of the sixth voltage signal, and receive and transmit the scan signal to the second control signal terminal C.

Illustratively, the gate of the eleventh transistor T11 is coupled to the fifth voltage signal terminal V3, the first pole of the eleventh transistor T11 is coupled to the fourth voltage signal terminal Vss, and the second pole of the eleventh transistor T11 is coupled to the second input signal terminal D.

For example, in the case that the level of the fifth voltage signal is an active level, the eleventh transistor T11 may be turned on under the control of the fifth voltage signal, and receive and transmit the fourth voltage signal to the second input signal terminal D.

Illustratively, the gate of the twelfth transistor T12 is coupled to the sixth voltage signal terminal V4, the first pole of the twelfth transistor T12 is coupled to the data signal terminal Date, and the second pole of the twelfth transistor T12 is coupled to the second input signal terminal D.

For example, in the case that the level of the sixth voltage signal is the active level, the twelfth transistor T12 may be turned on under the control of the sixth voltage signal, and receive and transmit the data signal to the second input signal terminal D.

It is understood that the gate of the ninth transistor T9 and the gate of the eleventh transistor T11 are coupled to the fifth voltage signal terminal V3, so that the ninth transistor T9 and the eleventh transistor T11 can be simultaneously turned on under the control of the fifth voltage signal and respectively transmit corresponding electrical signals to control the on state of the third transistor T3 in the second switch circuit 20, further control the on state of the fourth transistor T4 in the second driving circuit 40, and adjust the threshold voltage of the fourth transistor T4.

It is understood that the gate of the tenth transistor T10 and the gate of the twelfth transistor T12 are coupled to the sixth voltage signal terminal V4, so that the tenth transistor T10 and the twelfth transistor T12 can be turned on simultaneously under the control of the sixth voltage signal and transmit corresponding electrical signals respectively to control the on state of the third transistor T3 in the second switch circuit 20, further control the on state of the fourth transistor T4 in the second driving circuit 40, and adjust the threshold voltage of the fourth transistor T4.

The amount of shift in the threshold voltage of the transistor is related to the voltage difference Vgs of the transistor. Therefore, referring to fig. 2, by adjusting the voltage of the first input signal (i.e., the fourth voltage signal or the data signal) provided at the first input signal terminal B transmitted to the first node N1, the negative shift of the threshold voltage generated by the second transistor T2 in the negative bias state and the positive shift of the threshold voltage generated by the second transistor T2 in the previous stage can be completely offset, so that the threshold voltage of the second transistor T2 is accurately restored to the initial state.

It will be appreciated that by adjusting the voltage of the second input signal (i.e. the fourth voltage signal or the data signal) provided at the second input signal terminal D transmitted to the second node N2, the positive shift of the threshold voltage of the fourth transistor T4 generated in the positive bias state and the negative shift of the threshold voltage of the fourth transistor T4 generated in the previous stage can be completely offset, so that the threshold voltage of the fourth transistor T4 is accurately restored to the initial state. In some embodiments, the type of transistors included in the first selection circuit 50 is the same as the type of transistors included in the second selection circuit 60, the second voltage signal and the fifth voltage signal are inverted signals, and the third voltage signal and the sixth voltage signal are inverted signals.

For example, referring to fig. 6, the transistors included in the first selection circuit 50 are all N-type transistors, and the transistors included in the second selection circuit 60 are all N-type transistors. Alternatively, the transistors included in the first selection circuit 50 are P-type transistors, and the transistors included in the second selection circuit 60 are P-type transistors.

For example, the "inverted signal" refers to that, in the same period of time, if the level of the second voltage signal is a high level, the level of the fifth voltage signal is a low level; if the level of the second voltage signal is a low level, the level of the fifth voltage signal is a high level. If the level of the third voltage signal is a high level, the level of the sixth voltage signal is a low level; if the level of the third voltage signal is low, the level of the sixth voltage signal is high.

Referring to fig. 6, the following description will exemplify that the types of transistors included in the first selection circuit 50 and the second selection circuit 60 are both N-type transistors. For example, if the second voltage signal is a high level signal, the fifth voltage signal is a low level signal, the third voltage signal is a low level signal, and the sixth voltage signal is a high level signal within the same period of time. In this case:

In the first selection circuit 50, the sixth transistor T6 is turned off, and the fifth transistor T5 is turned on and transmits the first voltage signal to the first control signal terminal a. The eighth transistor T8 is turned off, the seventh transistor T7 is turned on, and the fourth voltage signal is transmitted to the first input signal terminal B. The first transistor T1 is turned on under the control of the voltage of the first control signal terminal a, and transmits the fourth voltage signal from the first input signal terminal B to the first node N1. Since the level of the fourth voltage signal is a low level, the second transistor T2 is in an off state.

In the second selection circuit 60, the ninth transistor T9 is turned off, and the tenth transistor T10 is turned on and transmits the scan signal to the second control signal terminal C. The eleventh transistor T11 is turned off, and the twelfth transistor T12 is turned on and transmits the data signal to the second input signal terminal D. The third transistor T3 is turned on under the control of the voltage of the second control signal terminal C, and transmits the data signal from the second input signal terminal D to the second node N2. Since the level of the data signal is high, the fourth transistor T4 is in an on state, and transmits the first voltage signal to the first electrode of the light emitting device L.

In some embodiments, referring to fig. 6, in the case where the type of the transistor included in the first selection circuit 50 and the type of the transistor included in the second selection circuit 60 are the same, the second voltage signal and the sixth voltage signal are the same signal; the third voltage signal and the fifth voltage signal are the same signals.

The second voltage signal terminal V1 and the sixth voltage signal terminal V4 are connected to the same signal terminal, and the signal terminal provides the same voltage signal for the second voltage signal terminal and the sixth voltage signal terminal.

The third voltage signal terminal V2 and the fifth voltage signal terminal V3 are connected to the same signal terminal, and the signal terminal provides the same voltage signal for the third voltage signal terminal V2 and the fifth voltage signal terminal V3.

Through the arrangement, the number of voltage signal ends in the pixel circuit can be reduced, and the design and manufacturing process of the pixel circuit are simplified.

In some embodiments, referring to fig. 7, the type of transistors included in the first selection circuit 50 and the type of transistors included in the second selection circuit 60 are different. The second voltage signal and the fifth voltage signal are the same signals; the third voltage signal and the sixth voltage signal are the same signals.

Illustratively, the transistors included in the first selection circuit 50 are all N-type transistors, and the transistors included in the second selection circuit 60 are all P-type transistors. Alternatively, the transistors included in the first selection circuit 50 are P-type transistors, and the transistors included in the second selection circuit 60 are N-type transistors.

The second voltage signal terminal V1 and the fifth voltage signal terminal V3 are connected to the same signal terminal, and the signal terminals provide the same voltage signal for the second voltage signal terminal V1 and the fifth voltage signal terminal V3.

The third voltage signal terminal V2 and the sixth voltage signal terminal V4 are connected to the same signal terminal, and the signal terminals provide the same voltage signal for the third voltage signal terminal V2 and the sixth voltage signal terminal V4.

By the arrangement, the number of voltage signal ends in the pixel circuit can be reduced, and the design and manufacturing process of the pixel circuit are simplified.

Referring to fig. 7, the following description will take, as an example, that the transistors included in the first selection circuit 50 are all N-type transistors, and that the transistors included in the second selection circuit 60 are all P-type transistors. For example, the second voltage signal and the fifth voltage signal are high level signals, and the third voltage signal and the sixth voltage signal are low level signals. In this case:

in the first selection circuit 50, the sixth transistor T6 is turned off, and the fifth transistor T5 is turned on and transmits the first voltage signal to the first control signal terminal a. The eighth transistor T8 is turned off, the seventh transistor T7 is turned on, and the fourth voltage signal is transmitted to the first input signal terminal B. The first transistor T1 is turned on under the control of the voltage of the first control signal terminal a, and transmits the fourth voltage signal from the fourth voltage signal terminal Vss to the first node N1. Since the level of the fourth voltage signal is a low level signal, the second transistor T2 is in an off state.

In the second selection circuit 60, the ninth transistor T9 is turned off, and the tenth transistor T10 is turned on and transmits the scan signal to the second control signal terminal C. The eleventh transistor T11 is turned off, and the twelfth transistor T12 is turned on and transmits the data signal to the second input signal terminal D. The third transistor T3 is turned on under the control of the voltage of the second control signal terminal C, and transmits the data signal from the data signal terminal Date to the second node N2. Since the data signal is a high level signal, the fourth transistor T4 is in a conductive state, and transmits a first voltage signal to the first electrode of the light emitting device L.

In some embodiments, referring to fig. 7, the type of transistors included in the first selection circuit 50 and the type of transistors included in the second selection circuit 60 are different. The second voltage signal and the sixth voltage signal are mutually opposite signals; the third voltage signal and the fifth voltage signal are mutually opposite signals.

For example, the "inverted signal" refers to that, in the same period of time, if the level of the second voltage signal is a high level, the level of the fifth voltage signal is a low level; if the level of the second voltage signal is a low level, the level of the fifth voltage signal is a high level; if the level of the third voltage signal is a high level, the level of the sixth voltage signal is a low level; if the level of the third voltage signal is low, the level of the sixth voltage signal is high.

In some embodiments, referring to fig. 8, the pixel circuit 100 further includes a sensing circuit 70. The sensing circuit 70 is coupled to the first pole of the light emitting device L, the third control signal terminal G, and the sensing signal terminal H. The sensing circuit 70 is configured to detect the threshold voltage of the second transistor T2 or the fourth transistor T4 under the control of the third control signal provided by the third control signal terminal G.

For example, referring to fig. 9 and 10, the sensing circuit 70 may sense the second transistor T2 or the fourth transistor T4 and transmit sensed data to the sensing signal terminal H to calculate a driving voltage value to be compensated using the sensing circuit 70 and perform feedback, thereby implementing external compensation of the pixel circuit 100.

In some embodiments, referring to fig. 9 and 10, the sensing circuit 70 includes a thirteenth transistor T13. The gate of the thirteenth transistor T13 is coupled to the third control signal terminal G, the first electrode of the thirteenth transistor T13 is coupled to the first electrode of the light emitting device L, and the second electrode of the thirteenth transistor T13 is coupled to the sensing signal terminal H.

Illustratively, when the first switching circuit 10 transmits the data signal to the first node N1 with the fourth transistor T4 being turned off, the data signal charges the first node N1. The thirteenth transistor T13 is turned on under the voltage control of the third control signal terminal G.

The second transistor T2 is turned on under the control of the first node N1, receives a first voltage signal, and transmits the first voltage signal to the first electrode of the light emitting device L, and charges the first electrode position of the light emitting device L, so that the voltage of the first electrode position of the light emitting device L increases until the second transistor T2 is turned off. At this time, a voltage difference Vc between the first node N1 and the first electrode of the light emitting device L is equal to the threshold voltage Vth of the second transistor T2.

Since the sensing transistor T13 is in a conductive state and the sensing signal terminal H is in a floating state, the sensing signal terminal H is charged during the process of charging the first electrode of the light emitting device L by the driving transistor T2. By sampling the voltage of the sensing signal terminal H, that is, obtaining the sensing signal, the threshold voltage Vth of the second transistor T2 can be calculated according to the relationship between the voltage of the sensing signal terminal H and the level of the data signal.

After the threshold voltage Vth of the second transistor T2 is calculated, the threshold voltage Vth may be compensated into the data signal of the next frame, and external compensation of the pixel circuit 100 is completed.

On the other hand, the embodiment of the present application provides a driving method of the pixel circuit 100 as above. The driving method of the pixel circuit 100 includes: a plurality of sequentially alternating first and second stages.

In the first stage, the first switching circuit 10 transmits the first input signal provided from the first input signal terminal B to the first node N1 in response to the first control signal provided from the first control signal terminal a. The first driving circuit 30 transmits the first voltage signal provided from the first voltage signal terminal B to the first electrode of the light emitting device L under the control of the voltage of the first node N1. The second drive circuit 40 is in an off state.

For example, in a case where the first driving circuit 30 transmits the first voltage signal to the first electrode of the light emitting device L and drives the light emitting device L to emit light, the second driving circuit 40 is in an off state. Accordingly, there is a voltage difference between the voltage of the first node N1 and the voltage value of the first voltage signal, a voltage difference between the voltage of the second node N2 and the voltage value of the first voltage signal, and the level of the first input signal controlling the voltage of the first node N1 is opposite to the level of the second input signal controlling the voltage of the second node N2.

In the second stage, in response to the second control signal provided by the second control signal terminal C, the second switch circuit 20 transmits the second input signal provided by the second input signal terminal D to the second node N2; the second driving circuit 40 transmits the first voltage signal provided from the first voltage signal terminal E to the first electrode of the light emitting device L under the control of the voltage of the second node N2. The first drive circuit 30 is in an off state.

Since the first phase and the second phase alternate in sequence, the first driving circuit 30 and the second driving circuit 40 are alternately in the on state, so that when one of the first driving circuit 30 and the second driving circuit 40 is in the positive bias state (or the negative bias state), the other is in the negative bias state (or the positive bias state). That is, the threshold voltages of the transistors included in the first driving circuit 30 may alternately drift in the positive direction and drift in the negative direction, and the threshold voltages of the transistors included in the second driving circuit 40 may alternately drift in the negative direction and drift in the positive direction, so that the total drift amount of the threshold voltages can be reduced by using the offset of the positive direction drift amount and the negative direction drift amount of the threshold voltages, thereby enhancing the stability of the value of the driving signal generated by the driving transistor and improving the light emitting stability of the light emitting device L.

In some embodiments, referring to fig. 6, in the first stage, in response to the third voltage signal provided by the third voltage signal terminal V2, the first selection circuit 50 transmits the scan signal provided by the scan signal terminal Gate to the first control signal terminal a and transmits the data signal provided by the data signal terminal Gate to the first input signal terminal B. The first switching circuit 10 transmits the data signal as a first input signal to the first node N1 under the control of the first control signal. The first driving circuit 30 transmits a first voltage signal to a first pole of the light emitting device L under the control of the voltage of the first node N1.

In response to the fifth voltage signal provided from the fifth voltage signal terminal V3, the second selection circuit 60 transmits the first voltage signal provided from the first voltage signal terminal Vdd to the second control signal terminal C, and transmits the fourth voltage signal provided from the fourth voltage signal terminal Vss to the second input signal terminal D. The second switching circuit 20 transmits the fourth voltage signal as a second input signal to the second node N2 under the control of the second control signal, and the second driving circuit 40 is turned off under the control of the voltage of the second node N2 and is in an off state.

In the second stage, the second selection circuit 60 transmits the scan signal to the second control signal terminal C and the data signal to the second input signal terminal D in response to the sixth voltage signal provided from the sixth voltage signal terminal V4. The second switching circuit 20 transmits the data signal as a second input signal to the second node N2 under the control of the second control signal; the second driving circuit 40 transmits a first voltage signal to the first electrode of the light emitting device L under the control of the voltage of the second node N2.

In response to the second voltage signal provided by the second voltage signal terminal V1, the first selection circuit 50 transmits the first voltage signal to the first control signal terminal a and transmits the fourth voltage signal to the first input signal terminal B. The first switching circuit 10 transmits the fourth voltage signal as the first input signal to the first node N1 under the control of the first control signal, and the first driving circuit 30 is turned off under the control of the voltage of the first node N1 and is in an off state.

Next, taking the structure of the pixel circuit 100 shown in fig. 6 as an example, a driving method of the pixel circuit 100 will be described in detail with reference to a timing chart shown in fig. 11. In this example, the transistors in fig. 6 are all N-type transistors.

In the first stage t1, the level of the second voltage signal provided by the second voltage signal terminal V1 is low, the level of the third voltage signal provided by the third voltage signal terminal V2 is high, the level of the fifth voltage signal provided by the fifth voltage signal terminal V3 is high, the level of the sixth voltage signal provided by the sixth voltage signal terminal V4 is low, the level of the scan signal is high, and the level of the data signal is high.

The fifth transistor T5 is turned off and the sixth transistor T6 is turned on. The sixth transistor T6 transmits the scan signal to the first control signal terminal a. The seventh transistor T7 is turned off and the eighth transistor T8 is turned on. The eighth transistor T8 transmits the data signal to the first input signal terminal B. The first transistor T1 is turned on under the control of the scan signal, and transmits the data signal to the first node N1. The second transistor T2 transmits a first voltage signal to a first electrode of the light emitting device L under the control of a data signal from the first node N1.

The ninth transistor T9 is turned on, and the tenth transistor T10 is turned off. The ninth transistor T9 transmits the first voltage signal to the second control signal terminal C. The eleventh transistor T11 is turned on and the twelfth transistor T12 is turned off. The eleventh transistor T11 transmits the fourth voltage signal to the second input signal terminal D. The third transistor T3 is turned on under control of the first voltage signal, and transmits a fourth voltage signal to the second node N2. The fourth transistor T4 is in an off state under control of the voltage of the fourth voltage signal from the second node N2.

In the second stage t2, the second voltage signal terminal V1 is at a high level, and the third voltage signal terminal V2 is at a low level. The fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the fifth transistor T5 transmits the first voltage signal to the first control signal terminal a; the seventh transistor T7 is turned on, the eighth transistor T8 is turned off, and the seventh transistor T7 is turned on to transmit the fourth voltage signal to the first input signal terminal B. The first transistor T1 is turned on under the control of the first voltage signal, and transmits a fourth voltage signal to the first node N1. The second transistor T2 is in an off state under control of the voltage of the fourth voltage signal from the first node NI.

The fifth voltage signal terminal V3 is at a low level, and the sixth voltage signal terminal V4 is at a high level. The ninth transistor T9 is turned off and the tenth transistor T10 is turned on, the tenth transistor T10 transmitting the scan signal to the second control signal terminal C; the eleventh transistor T11 is turned off and the twelfth transistor T12 is turned on, and the twelfth transistor T12 transmits the data signal to the second input signal terminal D. The third transistor T3 is turned on under control of the scan signal, and transmits the data signal to the second node N2. The fourth transistor T4 transmits the first voltage signal from the second node N2 to the first electrode of the light emitting device L under control of the voltage of the data signal.

The first phase T1 and the second phase T2 alternate, the second transistor T2 is alternately in an on state and an off state, and the fourth transistor T4 is alternately in an on state and an off state.

In some embodiments, the duration of the first stage is less than or equal to 1/4 second; the duration of the second stage is less than or equal to 1/4 second.

For example, referring to fig. 6, in case that the refresh frequency of the light emitting device L is 60Hz, the duration of the first stage may include a time corresponding to fifteen frames of images, i.e., 1/4 second at most. Thus, the threshold voltage drift amount generated by the second transistor and the fourth transistor T4 in the first stage is not excessive, and the light emitting stability of the light emitting device can be ensured to a certain extent.

Illustratively, the duration of the first stage may include a time corresponding to one frame, two frames, fifteen frames, and accordingly, the duration of the first stage may be 1/60 second, 1/30 second, 1/4 second; the second stage may include one frame, two frames, fifteen frames, and accordingly, the duration of the second stage may be 1/60 second, 1/30 second, 1/4 second.

It will be appreciated that the number of frames involved in the first and second phases described above may be increased accordingly when the refresh frequency of the light emitting device is high.

In some embodiments, the duration of the first phase is equal to the duration of the second phase.

Illustratively, in the case where the duration of the first phase is 1/60 seconds, the duration of the second phase is also 1/60 seconds; in the case of the first phase having a duration of 1/4 second, the second phase also has a duration of 1/4 second.

In an exemplary manner, in the process of displaying the light emitting device, in the case that the duration of the first stage is one frame time, the duration of the second stage is also one frame time; in the case that the duration of the first stage is two frame times, the duration of the second stage is also two frame times.

It can be understood that, referring to fig. 6, in the case where the duration of the first phase is equal to the duration of the second phase, the positive shift (or negative shift) of the threshold voltage generated by the second transistor T2 in the first phase and the negative shift (or positive shift) of the threshold voltage generated by the second transistor T2 in the second phase may be substantially completely offset, so as to reduce the total shift amount of the threshold voltage, further improve the stability of the value of the driving signal generated by the second transistor T2, and improve the light emitting stability of the light emitting device L.

Similarly, when the duration of the first phase is equal to the duration of the second phase, the negative shift (or positive shift) of the threshold voltage generated by the fourth transistor T4 in the first phase and the positive shift (or negative shift) of the threshold voltage generated by the fourth transistor T4 in the second phase can be substantially completely offset, so that the total shift amount of the threshold voltage is reduced, and further, the stability of the value of the driving signal generated by the fourth transistor T4 is improved, and the light emitting stability of the light emitting device L is improved.

The embodiment of the application also provides the display device 1000. Referring to fig. 12, the display device 1000 includes a substrate 1, a plurality of pixel circuits 100, and a cover plate 2. The plurality of pixel circuits 100 are disposed on one side of the substrate 1, and the cover plate 2 is disposed on a side of the plurality of pixel circuits 100 away from the substrate 1, and the cover plate 2 can protect the light emitting device L in the pixel circuits 100.

In this embodiment, the display device 1000 may further include other components, such as a control circuit for providing an electrical signal to the pixel circuit, which may include a printed circuit board and/or an integrated circuit electrically connected to the light emitting substrate.

In some embodiments, the display device 1000 is used to display images (i.e., pictures). At this time, the display device 1000 may include a display or a product including the display. Among them, the display may be a flat panel display (Flat Panel Display, FPD), a micro display, or the like. The display may be a transparent display or an opaque display, depending on whether the user can see the scene division on the back of the display. The display may be a flexible display or a general display (which may be referred to as a rigid display) if the display is capable of being bent or rolled. By way of example, an article of manufacture containing a display may include: computer displays, televisions, billboards, laser printers with display capabilities, telephones, cell phones, personal digital assistants (Personal Digital Assistant, PDA), laptop computers, digital cameras, camcorders, viewfinders, vehicles, large area walls, theatre screens or stadium signs, etc.

The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope of the present disclosure should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A pixel circuit, the pixel circuit comprising: a first switching circuit, a second switching circuit, a first driving circuit, a second driving circuit, and a light emitting device;

the first switch circuit is coupled with the first control signal end, the first input signal end and the first node; the first switch circuit is configured to transmit a first input signal provided by the first input signal terminal to the first node under the control of a first control signal provided by the first control signal terminal;

the first driving circuit is coupled with the first node, the first voltage signal end and the first pole of the light emitting device; the first driving circuit is configured to transmit a first voltage signal provided by the first voltage signal terminal to a first pole of the light emitting device under control of a voltage of the first node;

The second switch circuit is coupled with the second control signal end, the second input signal end and the second node; the second switching circuit is configured to transmit a second input signal provided by the second input signal terminal to the second node under the control of a second control signal provided by the second control signal terminal;

the second driving circuit is coupled with the second node, the first voltage signal end and the first electrode of the light emitting device; the second driving circuit is configured to transmit the first voltage signal to a first pole of the light emitting device under control of a voltage of the second node;

wherein, in a case where one of the first driving circuit and the second driving circuit transmits the first voltage signal to the first electrode of the light emitting device, the other is in an off state;

the pixel circuit further comprises a first selection circuit and a second selection circuit;

the first selection circuit is coupled with the first voltage signal end, the second voltage signal end, the third voltage signal end, the fourth voltage signal end, the scanning signal end, the data signal end, the first control signal end and the first input signal end; the first selection circuit is configured to transmit the first voltage signal to the first control signal terminal and transmit the fourth voltage signal provided by the fourth voltage signal terminal to the first input signal terminal under the control of the second voltage signal provided by the second voltage signal terminal; or under the control of a third voltage signal provided by the third voltage signal end, transmitting a scanning signal provided by the scanning signal end to the first control signal end, and transmitting a data signal provided by the data signal end to the first input signal end;

The second selection circuit is coupled to the first voltage signal terminal, the fifth voltage signal terminal, the sixth voltage signal terminal, the fourth voltage signal terminal, the scanning signal terminal, the data signal terminal, the second control signal terminal and the second input signal terminal; the second selection circuit is configured to transmit the first voltage signal to the second control signal terminal and the fourth voltage signal to the second input signal terminal under the control of a fifth voltage signal provided by the fifth voltage signal terminal; or, under the control of a sixth voltage signal provided by the sixth voltage signal terminal, transmitting the scanning signal to the second control signal terminal, and transmitting the data signal to the second input signal terminal;

the first selection circuit includes: a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

the grid electrode of the fifth transistor is coupled with the second voltage signal end, the first electrode of the fifth transistor is coupled with the first voltage signal end, and the second electrode of the fifth transistor is coupled with the first control signal end;

the grid electrode of the sixth transistor is coupled with the third voltage signal end, the first electrode of the sixth transistor is coupled with the scanning signal end, and the second electrode of the sixth transistor is coupled with the first control signal end;

A gate of the seventh transistor is coupled to the second voltage signal terminal, a first pole of the seventh transistor is coupled to the fourth voltage signal terminal, and a second pole of the seventh transistor is coupled to the first input signal terminal;

a gate of the eighth transistor is coupled to the third voltage signal terminal, a first pole of the eighth transistor is coupled to the data signal terminal, and a second pole of the eighth transistor is coupled to the first input signal terminal;

the second selection circuit includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor;

a gate of the ninth transistor is coupled to the fifth voltage signal terminal, a first pole of the ninth transistor is coupled to the first voltage signal terminal, and a second pole of the ninth transistor is coupled to the second control signal terminal;

a gate of the tenth transistor is coupled to the sixth voltage signal terminal, a first pole of the tenth transistor is coupled to the scan signal terminal, and a second pole of the tenth transistor is coupled to the second control signal terminal;

a gate of the eleventh transistor is coupled to the fifth voltage signal terminal, a first pole of the eleventh transistor is coupled to the fourth voltage signal terminal, and a second pole of the eleventh transistor is coupled to the second input signal terminal;

A gate of the twelfth transistor is coupled to the sixth voltage signal terminal, a first pole of the twelfth transistor is coupled to the data signal terminal, and a second pole of the twelfth transistor is coupled to the second input signal terminal;

the second pole of the light emitting device is coupled with the fourth voltage signal terminal;

the first switching circuit includes: a first transistor;

the grid electrode of the first transistor is coupled with the first control signal end, the first electrode of the first transistor is coupled with the first input signal end, and the second electrode of the first transistor is coupled with the first node;

the first driving circuit includes: a second transistor and a first capacitor;

the grid electrode of the second transistor is coupled with the first node, the first electrode of the second transistor is coupled with the first voltage signal end, and the second electrode of the second transistor is coupled with the first electrode of the light emitting device;

a first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the first electrode of the light emitting device;

the second switching circuit includes: a third transistor;

a gate of the third transistor is coupled to the second control signal terminal, a first pole of the third transistor is coupled to the second input signal terminal, and a second pole of the third transistor is coupled to the second node;

The second driving circuit includes: a fourth transistor and a second capacitor;

a gate of the fourth transistor is coupled to the second node, a first pole of the fourth transistor is coupled to the first voltage signal terminal, and a second pole of the fourth transistor is coupled to the first pole of the light emitting device;

a first pole of the second capacitor is coupled to the second node, and a second pole of the second capacitor is coupled to the first pole of the light emitting device;

in the working stage of the first driving circuit, the second selecting circuit transmits a first voltage signal provided by the first voltage signal end to the grid electrode of the third transistor, and transmits a fourth voltage signal provided by the fourth voltage signal end to the first electrode of the third transistor; the second driving circuit is turned off under the control of the voltage of the second node and is in a cut-off state;

in the working stage of the second driving circuit, the first selecting circuit transmits the first voltage signal to the grid electrode of the first transistor and transmits the fourth voltage signal to the first electrode of the first transistor; the first driving circuit is turned off under the control of the voltage of the first node and is in a cut-off state;

The first voltage signal terminal is configured to transmit a direct-current high-level signal, and the fourth voltage signal terminal is configured to transmit a direct-current low-level signal.

2. The pixel circuit according to claim 1, wherein a type of a transistor included in the first selection circuit and a type of a transistor included in the second selection circuit are the same;

the second voltage signal and the fifth voltage signal are mutually opposite signals;

the third voltage signal and the sixth voltage signal are mutually opposite signals.

3. The pixel circuit according to claim 2, wherein,

the second voltage signal and the sixth voltage signal are the same signals;

the third voltage signal and the fifth voltage signal are the same signal.

4. The pixel circuit according to claim 1, wherein a type of a transistor included in the first selection circuit and a type of a transistor included in the second selection circuit are different;

the second voltage signal and the fifth voltage signal are the same signals;

the third voltage signal and the sixth voltage signal are the same signal.

5. The pixel circuit of claim 4, wherein,

The second voltage signal and the sixth voltage signal are mutually opposite signals;

the third voltage signal and the fifth voltage signal are mutually opposite signals.

6. The pixel circuit of claim 1, wherein the pixel circuit further comprises a sensing circuit;

the sensing circuit is coupled with the first pole of the light emitting device, the third control signal end and the sensing signal end; the sensing circuit is configured to detect a threshold voltage of the second transistor or the fourth transistor under the control of a third control signal provided by the third control signal terminal.

7. The pixel circuit according to claim 6, wherein the sensing circuit includes a thirteenth transistor;

the gate of the thirteenth transistor is coupled to the third control signal terminal, the first electrode of the thirteenth transistor is coupled to the first electrode of the light emitting device, and the second electrode of the thirteenth transistor is coupled to the sensing signal terminal.

8. A driving method of a pixel circuit, characterized in that the driving method is applied to the pixel circuit according to any one of claims 1 to 7; the driving method includes: a plurality of sequentially alternating first and second stages;

In the first stage, the first switch circuit transmits a first input signal provided by a first input signal terminal to a first node in response to a first control signal provided by a first control signal terminal; the first driving circuit transmits a first voltage signal provided by a first voltage signal end to a first pole of the light emitting device under the control of the voltage of the first node; the second driving circuit is in a cut-off state;

in the first stage, in response to a third voltage signal provided by a third voltage signal terminal, a first selection circuit transmits a scanning signal provided by a scanning signal terminal to the first control signal terminal and transmits a data signal provided by a data signal terminal to the first input signal terminal; the first switching circuit transmits the data signal as the first input signal to the first node under the control of the first control signal; the first driving circuit transmits the first voltage signal to a first pole of the light emitting device under the control of the voltage of the first node;

in response to a fifth voltage signal provided by a fifth voltage signal terminal, the second selection circuit transmits a first voltage signal provided by a first voltage signal terminal to the second control signal terminal and transmits a fourth voltage signal provided by a fourth voltage signal terminal to the second input signal terminal; the second switching circuit transmits the fourth voltage signal as the second input signal to the second node under the control of the second control signal, and the second driving circuit is turned off under the control of the voltage of the second node and is in a cut-off state;

In the second stage, the second switch circuit transmits a second input signal provided by a second input signal terminal to a second node in response to a second control signal provided by a second control signal terminal; the second driving circuit transmits the first voltage signal to a first electrode of the light emitting device under the control of the voltage of the second node; the first driving circuit is in a cut-off state;

in the second stage, in response to a sixth voltage signal provided by a sixth voltage signal terminal, the second selection circuit transmits the scan signal to the second control signal terminal and transmits the data signal to the second input signal terminal; the second switching circuit transmits the data signal as the second input signal to the second node under the control of the second control signal; the second driving circuit transmits the first voltage signal to a first electrode of the light emitting device under the control of the voltage of the second node;

the first selection circuit transmits the first voltage signal to the first control signal terminal and transmits the fourth voltage signal to the first input signal terminal in response to a second voltage signal provided by a second voltage signal terminal; the first switch circuit transmits the fourth voltage signal to the first node as the first input signal under the control of the first control signal, and the first driving circuit is turned off under the control of the voltage of the first node and is in a cut-off state;

9. The method for driving a pixel circuit according to claim 8, wherein,

the duration of the first stage is less than or equal to 1/4 second; the duration of the second stage is less than or equal to 1/4 second.

10. The method for driving a pixel circuit according to claim 8, wherein,

the duration of the first stage is equal to the duration of the second stage.

11. A display device, characterized in that the display device comprises:

a substrate;

a plurality of pixel circuits according to any one of claims 1 to 7 provided on one side of the substrate; the method comprises the steps of,

and a cover plate arranged on one side of the plurality of pixel circuits away from the substrate.