TWI773313B - Pixel circuit and driving method thereof - Google Patents

Abstract

A pixel circuit includes a first, a second, a third, a fourth, a fifth and a sixth transistor, a driving transistor, an oxide transistor and a capacitor. The control terminal of the driving transistor is coupled to the second terminal of the oxide transistor. The second terminal of the driving transistor is coupled to the second terminal of the first transistor and the second terminal of the second transistor. The first terminal of the first transistor is coupled to the first terminal of the oxide transistor. The first terminal of the second transistor and the first terminal of the third transistor are coupled to the anode end of the light emitting element. The first terminal of the fourth transistor is coupled to the first terminal of the first transistor and the first terminal of the oxide transistor. One end of the capacitor is coupled to the control terminal of the driving transistor and the second terminal of the oxide transistor. The other end of the capacitor is coupled to the second terminal of the fifth transistor and the first terminal of the sixth transistor.

Description

Pixel circuit and driving method thereof

The present disclosure relates to a pixel circuit and a driving method thereof, and more particularly, to a pixel circuit and a driving method thereof suitable for a low frame refresh rate.

With the increasing demand of digital display devices, low frame rate (or low frame rate, Low Frame Rate) is widely used in display devices to reduce power consumption, save power and prolong usage time. However, when the picture is not updated, the brightness displayed in the light-emitting stage will be unstable while maintaining the frame number of the previous picture, which will lead to flickering.

One aspect of the present disclosure is a one-pixel circuit. The pixel circuit includes a driving transistor, a first transistor, an oxide transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor crystal and a capacitor. The control terminal of the driving transistor is coupled to a first node, the first terminal of the driving transistor receives a system high voltage, and the second terminal of the driving transistor is coupled to a second node. The control terminal of the first transistor receives a first control signal, the first terminal of the first transistor is coupled to a third node, and the second terminal of the first transistor is coupled to the second node. The control terminal of the oxide transistor receives a second control signal, the first terminal of the oxide transistor is coupled to the third node, and the second terminal of the oxide transistor is coupled to the first node. The control terminal of the second transistor receives a light-emitting control signal, the first terminal of the second transistor is coupled to the anode terminal of a light-emitting element, and the second terminal of the second transistor is coupled to the second node . The control terminal of the third transistor receives a third control signal, the first terminal of the third transistor is coupled to the anode terminal of the light-emitting element, and the second terminal of the third transistor receives a first reference voltage . The control terminal of the fourth transistor receives a fourth control signal, the first terminal of the fourth transistor is coupled to the third node, and the second terminal of the fourth transistor receives the first reference voltage. The control terminal of the fifth transistor receives the first control signal, the first terminal of the fifth transistor receives a data voltage, and the second terminal of the fifth transistor is coupled to a fourth node. The control terminal of the sixth transistor receives the light-emitting control signal, the first terminal of the sixth transistor is coupled to the fourth node, and the second terminal of the sixth transistor receives a second reference voltage. The capacitor is coupled between the fourth node and the first node.

Another aspect of the present disclosure is a driving method. The driving method is applicable to a pixel circuit, and includes: resetting an anode terminal of a light-emitting element to a first reference voltage in a first period of a first frame; resetting a second period of the first frame A control terminal and a second terminal of a driving transistor are set to the first reference voltage; in a third period of the first frame, a compensation voltage is provided to the first transistor by turning on a first transistor and an oxide transistor a control terminal of the driving transistor; and in a fourth period of the first frame, a data voltage is coupled to the control terminal of the driving transistor through a sixth transistor that is turned on and a capacitor, so that the driving transistor The crystal outputs a driving current to the light-emitting element according to a working voltage.

To sum up, during the period of maintaining the previous frame of the picture signal, the present disclosure does not write a new data voltage to the pixel circuit, but still resets the anode terminal of the light-emitting element, so that the light-emitting element will not be affected by the residual charge Luminous brightness. Due to the design of the oxide transistor, the voltage level of the control terminal of the driving transistor can be kept close to the voltage level during the period in which the picture signal is updated. In this way, when the picture update rate is reduced (ie, in the low frame rate mode), the power consumption can be saved and the luminous brightness can be stabilized, avoiding the phenomenon of flickering.

The following is a detailed description of the embodiments in conjunction with the accompanying drawings, but the specific embodiments described are only used to explain the present case, and are not used to limit the present case, and the description of the structure and operation is not used to limit the order of its execution. The recombined structures, resulting in devices with equal efficacy, are all within the scope of the present disclosure.

The terms used throughout the specification and the scope of the patent application, unless otherwise specified, generally have the ordinary meaning of each term used in the field, in the content disclosed herein and in the specific content.

As used herein, "coupled" or "connected" may refer to two or more elements in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or two or more elements Elements interact or act on each other.

Please refer to FIG. 1, which depicts a pixel circuit 100 according to some embodiments of the present disclosure. The pixel circuit 100 includes a driving transistor TD, an oxide transistor TO, a plurality of transistors T1-T6, a capacitor C1 and a light-emitting element OLED.

In some embodiments, the pixel circuit 100 may be applied to a display device. For example, Active Matrix Organic Light Emitting Display (AMOLED) and Active Matrix Micro Light Emitting Display (AMOLED, AMµLED) and so on. For example, a display device may include a plurality of pixel circuits 100 arranged in an array to form a complete display panel.

In some embodiments, in addition to the plurality of pixel circuits 100 , the display device may further include a controller, a source driver, and a gate driver. The controller is coupled to the source driver and the gate driver, the source driver is connected to the pixel circuits 100 in the display panel through a plurality of data lines, and the gate driver is connected to the display panel through a plurality of scan lines. A plurality of pixel circuits 100 . The controller sequentially drives the pixel circuits 100 in each column through the source driver and the gate driver.

As shown in FIG. 1, the control terminal (eg gate terminal) of the driving transistor TD is coupled to a node N1, the first terminal (eg the source terminal) of the driving transistor TD receives a system high voltage OVDD, and the driving transistor TD The second terminal (eg, the drain terminal) of the TD is coupled to a node N2. The first end of the transistor T1 is coupled to a node N3, the second end of the transistor T1 is coupled to the node N2, and the control end of the transistor T1 receives a first control signal S2, so that the transistor T1 is used to operate according to the first control signal S2. A control signal S2 is selectively turned on or off. The first end of the oxide transistor TO is coupled to the node N3 (ie the first end of the oxide transistor TO is coupled to the first end of the transistor T1 ), and the second end of the oxide transistor TO is coupled to the node N1 (that is, the second terminal of the oxide transistor TO is coupled to the control terminal of the driving transistor TD), and the control terminal of the oxide transistor TO receives a second control signal S3, so that the oxide transistor TO is used according to The second control signal S3 is selectively turned on or off.

The first end of the transistor T2 is coupled to the anode end of the light emitting element OLED, and the second end of the transistor T2 is coupled to the node N2. In other words, the second end of the driving transistor TD, the second end of the transistor T1 and the second end of the transistor T2 are coupled together. The control end of the transistor T2 receives a light-emitting control signal EM, so that the transistor T2 is selectively turned on or off according to the light-emitting control signal EM.

The first end of the transistor T3 is coupled to the anode end of the light-emitting element OLED (that is, the first end of the transistor T3 is coupled to the first end of the transistor T2), and the second end of the transistor T3 receives a reference voltage Vref_N, The control end of the transistor T3 receives a third control signal S1[N], so that the transistor T3 is selectively turned on or off according to the third control signal S1[N]. The cathode terminal of the light-emitting element OLED receives a system low voltage OVSS.

The first end of the transistor T4 is coupled to the node N3. In other words, the first end of the transistor T4, the first end of the oxide transistor TO and the first end of the transistor T1 are coupled together. The second end of the transistor T4 receives the reference voltage Vref_N, and the control end of the transistor T4 receives the third control signal S1[N+1] of the resuming stage, so that the transistor T4 is used for the third control signal of the resuming stage S1[N+1] is selectively turned on or off.

The capacitor C1 is coupled between the node N1 and a node N4. The first end of the transistor T5 receives a data voltage Vdata, the second end of the transistor T5 is coupled to the node N4, and the control end of the transistor T5 receives the first control signal S2, so that the transistor T5 is used for the first control The signal S2 is selectively turned on or off. The first end of the transistor T6 is coupled to the node N4 (that is, the first end of the transistor T6 is coupled to the second end of the transistor T5 ), the second end of the transistor T6 receives the reference voltage Vref_P, and the The control terminal receives the light-emitting control signal EM, so that the transistor T6 is selectively turned on or off according to the light-emitting control signal EM.

In some embodiments, the reference voltage Vref_P and the reference voltage Vref_N have the same voltage level, but the present disclosure is not limited to this. In other embodiments, the reference voltage Vref_P and the reference voltage Vref_N have different voltage levels respectively. It should be noted that, regardless of whether the reference voltage Vref_P and the reference voltage Vref_N have the same voltage level, the reference voltage Vref_P and the reference voltage Vref_N are respectively supplied by two independent voltage sources.

In the embodiment of FIG. 1, the driving transistor TD and the transistors T1-T6 are all P-type thin film transistors, and the oxide transistor TO is an N-type thin film transistor, but the present disclosure is not limited thereto. . In other embodiments, the driving transistor TD and the transistors T1 to T6 are all N-type thin film transistors, and the oxide transistor TO is still an N-type thin film transistor due to the limitation of its fabrication material. Specifically, the active layers of the driving transistor TD and the transistors T1 to T6 are mainly formed of polysilicon, and the active layer of the oxide transistor TO is mainly formed of an oxide semiconductor.

In some embodiments, the light-emitting element OLED can be an organic light-emitting diode or a micro-light-emitting diode or the like. In some embodiments, the micro-LED refers to the size of the diode chip below 75 μm, wherein the diode chip is produced on the diode wafer first, and then transferred to the display device through the mass transfer technology. The substrate is electrically connected to the transistor.

Please refer to FIG. 2 , which is a timing diagram of the first control signal S2 , the second control signal S3 , the third control signal S1 and the lighting control signal EM according to some embodiments of the present disclosure. In the embodiment of FIG. 2 , in the normal mode, each frame (frame) of the pixel circuit 100 is shown as a period Fd. The signal in the period Fd is the signal when the screen is generally updated. Among them, the third control signal S1[N] in Fig. 2 represents the signal used to control the pixel circuit 100 in Fig. 1, and the third control signal S1[N+1 in the resume stage in Fig. 2 ] represents a signal for driving the pixel circuit in another row adjacent to the pixel circuit 100 .

Next, the operation of the pixel circuit 100 will be described. As shown in FIG. 2, the period Fd includes sub-periods P1 to P4. Specifically, the sub-period P1 is the stage of resetting the anode terminal of the light-emitting element OLED, the sub-period P2 is the stage of resetting the control terminal and the second terminal of the driving transistor TD, and the sub-period P3 is the writing and writing of the pixel circuit 100. The compensation stage, and the sub-period P4 is the light-emitting stage of the pixel circuit 100 .

Please refer to FIGS. 2 and 3A together. FIG. 3A is a schematic diagram illustrating the state of each transistor of the pixel circuit 100 in the reset phase (ie, the sub-period P1 ) of the anode terminal of the light-emitting element OLED. In the sub-period P1, the third control signal S1[N] is switched to the on-voltage level (eg, a low voltage level for P-type thin film transistors, and a high voltage level for N-type thin film transistors) , and the first control signal S2, the second control signal S3, the third control signal S1[N+1] of the retransmission stage and the light-emitting control signal EM are maintained at the off voltage level (for example, for P-type thin film transistors high voltage level for N-type TFTs and low voltage level for N-type TFTs). In this way, the oxide transistor TO and the transistors T1 ˜ T2 and T4 ˜ T6 are all turned off, and the transistor T3 is turned on, so as to provide the reference voltage Vref_N to the anode terminal of the light-emitting element OLED. Accordingly, the anode terminal of the light-emitting element OLED is reset to the reference voltage Vref_N in the sub-period P1 to ensure that the anode terminal of the light-emitting element OLED has no residual charge before the light-emitting phase (ie, the sub-period P4 ).

Please refer to FIGS. 2 and 3B together. FIG. 3B is a schematic diagram illustrating the state of each transistor of the pixel circuit 100 in the stage of resetting the control terminal and the second terminal of the driving transistor TD (ie, the sub-period P2 ). In the sub-period P2, the third control signal S1[N] is switched to the off voltage level, the first control signal S2, the second control signal S3 and the third control signal S1[N+1] of the resuming stage are switched to on voltage level, and the light-emitting control signal EM is maintained at the off-voltage level. As a result, the transistor T2, the transistor T3, and the transistor T6 are turned off, and the transistor T1, the transistor T4, the transistor T5, and the oxide transistor TO are turned on, so as to connect the reference voltage Vref_N from the second voltage of the transistor T4. The terminal is provided to the control terminal (ie node N1 ) and the second terminal (ie node N2 ) of the driving transistor TD. Accordingly, the control terminal and the second terminal of the driving transistor TD are respectively reset to the reference voltage Vref_N in the sub-period P2, so as to clear the residual charge of the previous frame.

Please refer to FIGS. 2 and 3C together. FIG. 3C is a schematic diagram illustrating the states of each transistor of the pixel circuit 100 in the writing and compensation phase (ie, the sub-period P3 ). In the sub-period P3, the third control signal S1[N+1] of the retransmission stage is switched to the off voltage level, the first control signal S2 and the second control signal S3 are maintained at the on voltage level, and the third control signal S1[N] and the light-emitting control signal EM are maintained at the off-voltage level. In this way, the transistor T2 , the transistor T3 , the transistor T4 and the transistor T6 are turned off, and the transistor T1 , the transistor T5 and the oxide transistor TO are turned on. At this time, the voltage difference between the first terminal and the control terminal of the driving transistor TD is the system high voltage OVDD minus the reference voltage Vref_N. The voltage difference is greater than a threshold voltage Vth of the driving transistor TD, so that the driving transistor TD is turned on. Accordingly, the turned-on driving transistor TD charges its control terminal according to the system high voltage OVDD at its first terminal until the voltage difference between the first terminal and the control terminal of the driving transistor TD is reduced to the level of the driving transistor TD. Threshold voltage Vth.

That is, the control terminal of the driving transistor TD (ie, the node N1 ) is compensated to a compensation voltage in the sub-period P3 , and the compensation voltage is the system high voltage OVDD minus the threshold voltage Vth of the driving transistor TD. In addition, in the sub-period P3, the data voltage Vdata is supplied to the node N4 through the turned-on transistor T5.

Please refer to FIG. 2 and FIG. 3D together. FIG. 3D is a schematic diagram illustrating the state of each transistor of the pixel circuit 100 in the light-emitting stage (ie, the sub-period P4 ). In the sub-period P4, the third control signal S1[N] and the third control signal S1[N+1] of the retransmission stage are maintained at the off voltage level, and the first control signal S2 and the second control signal S3 are switched to off. the off-voltage level, and the light-emitting control signal EM is switched to the on-voltage level. In this way, the transistor T1, the transistor T3, the transistor T4, the transistor T5 and the oxide transistor TO are turned off, and the transistor T2 and the transistor T6 are turned on, so as to couple the data voltage Vdata from the node N4 through the capacitor C1 to the control terminal of the drive transistor TD (ie, node N1). Specifically, after the transistor T6 is turned on, the voltage level of the node N4 is changed from the data voltage Vdata to the reference voltage Vref_P. Since the voltage difference between the two ends of the capacitor C1 remains unchanged, the voltage level of the control terminal (ie, the node N1 ) of the driving transistor TD also changes from the compensation voltage to a working voltage correspondingly. The operating voltage is the compensation voltage (ie the system high voltage OVDD minus the threshold voltage Vth of the driving transistor TD) plus the voltage difference changed by the node N4 (ie the reference voltage Vref_P minus the data voltage Vdata).

…(1) Next, the driving transistor TD generates a driving current Id according to the voltage level of its first terminal (ie, the system high voltage OVDD) and the voltage level of its control terminal (ie, the operating voltage). The driving voltage Id sequentially passes through the transistor T2 and the light-emitting element OLED, so that the light-emitting element OLED emits light. Among them, the drive current Id can be represented by formula (1):

…(1)

Among them, K is the Conduction Parameter. Compensated by the compensation voltage generated in the sub-period P3, the current magnitude of the driving current Id will not be affected by the element characteristics of the driving transistor TD (eg, the threshold voltage Vth drift). In this way, the pixel circuit 100 can provide a relatively stable driving current Id when displaying.

Please refer to FIG. 4 , which is a timing diagram of the first control signal S2 , the second control signal S3 , the third control signal S1 and the lighting control signal EM according to other embodiments of the present disclosure. In the embodiment shown in FIG. 4 , in the low frame number mode, each frame of the pixel circuit 100 may be alternately represented by a period Fd and a period Fs. Wherein, the signal in the period Fd is the signal when the picture is generally updated, and the signal in the period Fs is the signal of maintaining the previous frame of the picture. In other words, no new data voltage Vdata is written to the pixel circuit 100 during the period Fs.

For example, when the display device displays a static image, a picture content with a small change range or a slow change speed, the signal of the current frame is shown as the period Fd, the signal of the next frame is shown as the period Fs, and the signal of the next frame is shown as the period Fs. The signal of the frame is shown as the period Fd, and so on. For another example, the display device uses i frame as a cycle, the signal of the first frame in the cycle is shown as a period Fd, and the signals of the second to i frames are shown as a period Fs, wherein i is any positive integer greater than 2. Assuming that the screen update frequency in normal mode is about 60 Hz, when i is 3, the first frame will be updated, and the second and third frames will not be updated. The frequency is about 60/3=20 Hz.

In the embodiment of FIG. 4 , the description of the period Fd is similar to the description of the previous embodiment, so it is not repeated here. As shown in FIG. 4, the period Fs includes the aforementioned sub-periods P1 and P4. In other words, during the period Fs, the pixel circuit 100 will still reset the anode terminal of the light-emitting element OLED (ie, the sub-period P1), and perform light-emitting display (ie, the sub-period P4), so as to avoid the brightness in the low frame number mode. different flickering problems. The descriptions of the sub-periods P1 and P4 in the period Fs are similar to the descriptions of the foregoing embodiments, so they are not repeated here.

It is worth noting that, since the oxide transistor TO has the characteristics of low leakage, the voltage level of the control terminal of the driving transistor TD can be stably maintained at the aforementioned operating voltage during the period Fs. Accordingly, the problem of brightness shift caused by the change of the voltage level of the control terminal of the driving transistor TD in the low frame number mode can be avoided. In addition, with the help of the oxide transistor TO, the capacitance value of the capacitor C1 can also be reduced, thereby reducing the compensation time and layout space.

Please refer to FIG. 5, which depicts a pixel circuit 200 according to other embodiments of the present disclosure. Compared with the pixel circuit 100 of FIG. 1 , the pixel circuit 200 of FIG. 5 further includes a transistor T7 . As shown in FIG. 5, the first end of the transistor T7 is coupled to the first end of the oxide transistor TO, the second end of the transistor T7 is coupled to the node N3, and the control end of the transistor T7 receives the first end Control signal S2. The rest of the settings and operations of the pixel circuit 200 are similar to those in the foregoing embodiments, and thus are not described herein again.

Please refer to FIG. 6, which depicts a one-pixel circuit 200 according to other embodiments of the present disclosure. Compared with the pixel circuit 100 of FIG. 1 , the pixel circuit 200 of FIG. 6 further includes a transistor T7 . As shown in FIG. 6, the first end of the transistor T7 is coupled to the node N1, the second end of the transistor T7 is coupled to the second end of the oxide transistor TO, and the control end of the transistor T7 receives the first end Control signal S2. The rest of the settings and operations of the pixel circuit 200 are similar to those in the foregoing embodiments, and thus are not described herein again.

In summary, in the period Fs that maintains the previous frame of the picture signal, the present disclosure does not write a new data voltage Vdata to the pixel circuit, but still resets the anode terminal of the light-emitting element OLED, so that the light-emitting element OLED does not have any The residual electric charge affects the luminous brightness. Due to the design of the oxide transistor TO, the voltage level of the control terminal of the driving transistor TD can be kept close to the voltage level in the period Fd during which the picture signal is updated. In this way, when the picture update rate is reduced (ie, in the low frame rate mode), the power consumption can be saved and the luminous brightness can be stabilized, avoiding the phenomenon of flickering.

Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. The scope of protection of the disclosed contents shall be determined by the scope of the appended patent application.

100,200: pixel circuit T1, T2, T3, T4, T5, T6, T7: Transistor TD: drive transistor TO: oxide transistor C1: Capacitor N1, N2, N3, N4: Nodes OLED: light-emitting element S1, S2, S3: control signal EM: Illumination control signal Vdata: data voltage OVDD: system high voltage OVSS: System Low Voltage Vref_N, Vref_P: reference voltage Vth: threshold voltage Id: drive current Fd,Fs: period P1, P2, P3, P4: sub-periods

FIG. 1 is a schematic diagram illustrating a pixel circuit according to some embodiments of the present disclosure. FIG. 2 is a timing diagram illustrating a first control signal, a second control signal, a third control signal and a lighting control signal in a pixel circuit according to some embodiments of the present disclosure. FIGS. 3A to 3D are schematic diagrams illustrating a pixel circuit operating in different periods according to some embodiments of the present disclosure. FIG. 4 is a timing diagram illustrating a first control signal, a second control signal, a third control signal and a lighting control signal in a pixel circuit according to other embodiments of the present disclosure. FIG. 5 is a schematic diagram illustrating a pixel circuit according to other embodiments of the present disclosure. FIG. 6 is a schematic diagram illustrating a pixel circuit according to other embodiments of the present disclosure.

Domestic storage information (please note in the order of storage institution, date and number) none Foreign deposit information (please note in the order of deposit country, institution, date and number) none

100: pixel circuit

T1, T2, T3, T4, T5, T6: Transistor

TD: drive transistor

TO: oxide transistor

C1: Capacitor

N1, N2, N3, N4: Nodes

OLED: light-emitting element

S1, S2, S3: control signal

EM: Illumination control signal

Vdata: data voltage

OVDD: system high voltage

OVSS: System Low Voltage

Vref_N, Vref_P: reference voltage

Claims (10)

A pixel circuit, comprising: a driving transistor, wherein a control terminal of the driving transistor is coupled to a first node, the first terminal of the driving transistor receives a system high voltage, and a second terminal of the driving transistor The terminal is coupled to a second node; a first transistor, wherein the control terminal of the first transistor receives a first control signal, the first terminal of the first transistor is coupled to a third node, and the The second end of the first transistor is coupled to the second node; an oxide transistor, wherein the control end of the oxide transistor receives a second control signal, and the first end of the oxide transistor is coupled to the the third node, and the second terminal of the oxide transistor is coupled to the first node; a second transistor, wherein the control terminal of the second transistor receives a light-emitting control signal, and the control terminal of the second transistor The first end is coupled to the anode end of a light-emitting element, and the second end of the second transistor is coupled to the second node; a third transistor, wherein the control end of the third transistor receives a third a control signal, the first end of the third transistor is coupled to the anode end of the light-emitting element, and the second end of the third transistor receives a first reference voltage; a fourth transistor, wherein the fourth transistor The control terminal of the crystal receives a fourth control signal, the first terminal of the fourth transistor is coupled to the third node, and the second terminal of the fourth transistor receives the first reference voltage; a fifth transistor , wherein the control terminal of the fifth transistor receives the first control signal, the first terminal of the fifth transistor receives a data voltage, and the second terminal of the fifth transistor is coupled to a fourth node; a a sixth transistor, wherein the control end of the sixth transistor receives the light a control signal, the first end of the sixth transistor is coupled to the fourth node, and the second end of the sixth transistor receives a second reference voltage; and a capacitor is coupled to the fourth node and the fourth node between the first nodes; wherein, the drive transistor, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are active The layer is formed of a first material, and the active layer of the oxide transistor is formed of a second material different from the first material; wherein, during a first period of a first frame, the first reference voltage provided to the anode terminal of the light-emitting element; wherein, in a second period of the first frame, the first reference voltage is provided to the control terminal and the second terminal of the driving transistor. The pixel circuit of claim 1, further comprising a seventh transistor, wherein a control end of the seventh transistor receives the first control signal, and a first end of the seventh transistor is coupled to the oxide The first end of the object transistor, and the second end of the seventh transistor is coupled to the third node. The pixel circuit of claim 1, further comprising a seventh transistor, wherein a control end of the seventh transistor receives the first control signal, and a first end of the seventh transistor is coupled to the seventh transistor a node, and the second end of the seventh transistor is coupled to the second end of the oxide transistor. The pixel circuit of claim 1, wherein: in a first period of a first frame, the third control signal is switched to be turned on The voltage level, the first control signal, the second control signal, the fourth control signal and the light-emitting control signal are maintained at an off voltage level, so that the third transistor is turned on to provide the first reference voltage to the anode terminal of the light-emitting element; in a second period of the first frame, the third control signal is switched to the off voltage level, the first control signal, the second control signal and the fourth control signal are switched to The turn-on voltage level, the light-emitting control signal is maintained at the turn-off voltage level, so that the first transistor, the fourth transistor, the fifth transistor and the oxide transistor are turned on to provide the first reference voltage to the control terminal and the second terminal of the driving transistor; in a third period of the first frame, the fourth control signal is switched to a turn-off voltage level, and the first control signal and the second control signal are maintained at The turn-on voltage level, the third control signal and the light-emitting control signal are maintained at the turn-off voltage level, so that the first transistor, the fifth transistor and the oxide transistor are turned on to provide a compensation voltage to the driving the control terminal of the transistor and providing the data voltage to the fourth node; in a fourth period of the first frame, the third control signal and the fourth control signal are maintained at the off voltage level, the first A control signal and the second control signal are switched to an off voltage level, and the lighting control signal is switched to an on voltage level, so that the second transistor and the sixth transistor are turned on to couple the data voltage to the The control terminal of the driving transistor enables the driving transistor to output a driving current to the light-emitting element according to a working voltage. The pixel circuit of claim 4, wherein: During a first period of a second frame, the third control signal is switched to the on-voltage level, and the first control signal, the second control signal, the fourth control signal and the light-emitting control signal are maintained at the off-voltage level, so that the third transistor is turned on, so as to provide the first reference voltage to the anode terminal of the light-emitting element; in a second period of the second frame, the first control signal, the second control signal, the The third control signal and the fourth control signal are maintained at the off-voltage level, and the light-emitting control signal is switched to the on-voltage level, so that the second transistor and the sixth transistor are turned on, so that the driving transistor is turned on according to the The operating voltage outputs the driving current to the light-emitting element; wherein, the second frame is located after the first frame. The pixel circuit of claim 4, wherein the compensation voltage is the system high voltage minus a threshold voltage of the driving transistor, and the operating voltage is the compensation voltage plus the second reference voltage minus the data voltage . A driving method, suitable for a pixel circuit, comprises: in a first period of a first frame, resetting an anode terminal of a light-emitting element to a first reference voltage; in a second period of the first frame, resetting the control terminal and the second terminal of a driving transistor to the first reference voltage; in a third period of the first frame, a compensation voltage is provided by turning on a first transistor and an oxide transistor to the control terminal of the driving transistor; and in a fourth period of the first frame, a data voltage is coupled to the control terminal of the driving transistor through a sixth transistor that is turned on and a capacitor, so that the driving transistor outputs a driving current to the light-emitting element; wherein, the anode end of the light-emitting element is coupled to the second end of the driving transistor, and the first transistor is coupled between the second end of the driving transistor and the oxide transistor During this time, the oxide transistor is coupled between the first transistor and the control terminal of the driving transistor, and the capacitor is coupled between the control terminal of the driving transistor and the sixth transistor. The driving method of claim 7, wherein: in a first period of a second frame, the anode terminal of the light-emitting element is reset to the first reference voltage; and in a second period of the second frame, The voltage level of the control terminal of the driving transistor is maintained by the turned-off oxide transistor, so that the driving transistor outputs the driving current to the light-emitting element according to the operating voltage; wherein the second frame is located in the first one frame later. The driving method of claim 7, wherein the compensation voltage is a system high voltage minus a threshold voltage of the driving transistor, and the working voltage is the compensation voltage plus a second reference voltage minus the data voltage. The driving method of claim 9, wherein the first terminal of the driving transistor receives the system high voltage, and the second terminal of the sixth transistor receives the second reference voltage.

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