CN114385093A - System for promoting phased array antenna production efficiency - Google Patents
System for promoting phased array antenna production efficiency Download PDFInfo
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- CN114385093A CN114385093A CN202210295701.7A CN202210295701A CN114385093A CN 114385093 A CN114385093 A CN 114385093A CN 202210295701 A CN202210295701 A CN 202210295701A CN 114385093 A CN114385093 A CN 114385093A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
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Abstract
The invention discloses a system for improving the production efficiency of phased array antennas, which comprises a PC (personal computer) and a main control device, wherein the PC is connected with the main control device through a USB (universal serial bus) interface, and the main control device is respectively connected with N antennas to be processed through synchronous serial ports; the main control equipment receives data sent by a PC computer through a USB interface, and respectively sends the received data to N downstream antennas to be processed through synchronous serial ports by a time division multiplexing method, wherein N is less than or equal to 23. In the system, the data is written into the FLASH through the synchronous serial port of the main control equipment, the data needs to be transmitted on the synchronous serial port, the FLASH chip also needs to consume time during data writing operation, and data is written into other antennas in the time period, so that the time for writing the data in batches can be obviously shortened, and the production efficiency is improved.
Description
Technical Field
The invention belongs to the technical field of antenna control and time division multiplexing, and particularly relates to a system for improving the production efficiency of a phased array antenna.
Background
At present, a phased array antenna needs to store a large amount of data, and if only one or a plurality of antennas are designed and produced, the time for programming the data can be ignored. However, when mass production is required, tens of phased array antennas and hundreds of phased array antennas are produced in a day, and the programming time becomes a key factor influencing the production efficiency. In view of this, it is necessary for those skilled in the art to improve the efficiency of data writing during mass production.
Disclosure of Invention
The invention aims to provide a system for improving the production efficiency of a phased array antenna in order to overcome the defects of the prior art, and the purpose of shortening the data programming time when the antennas are programmed with data in batches is realized through the structural arrangement of the system.
The purpose of the invention is realized by the following technical scheme:
a system for improving the production efficiency of phased array antennas comprises a PC (personal computer) and a main control device, wherein the PC is connected with the main control device through a USB (universal serial bus) interface, and the main control device is respectively connected with N antennas to be processed through synchronous serial ports; the main control equipment receives data sent by a PC through a USB interface, respectively sends the received data to N downstream antennas to be processed through synchronous serial ports by a time division multiplexing method, completes data programming of each antenna, and stores the written data in FLASH of each antenna, wherein N is less than or equal to 23.
According to a preferred embodiment, the main control device is provided with 12 interfaces and is respectively connected with 12 antennas to be processed.
According to a preferred embodiment, the system comprises the following steps in the process of writing data to each antenna to be processed:
s1: the PC computer issues an instruction for setting the number of the antennas;
s2: erasing each antenna to be processed;
s3: setting FLASH addresses for storing write-in data for each antenna to be processed;
s4: and carrying out data writing operation on each antenna to be processed.
According to a preferred embodiment, the step S1 is specifically: and the PC computer issues an instruction for setting the number of the antennas based on the system performance index to complete the setting of the number of the antennas to be processed.
According to a preferred embodiment, the step S2 is specifically: the PC computer firstly issues a whole-chip erasing instruction of the antenna 1, then issues a whole-chip erasing instruction of the antenna 2, and finally sends a whole-chip erasing instruction of the antenna N; and after the data erasure of each antenna is successful, feeding back an erasure success command to the PC computer.
According to a preferred embodiment, the main control device is provided with an instruction storage space therein, which is used for buffering feedback instructions of each antenna and then sending the feedback data to the PC computer.
According to a preferred embodiment, the step S4 is: the upper computer firstly issues 1 byte data of the antenna 1, and then 1 byte data of the antenna 2, and a cycle is completed until 1 byte data of the last antenna N is issued; when m data are required to be written into each antenna, m cycles are carried out, and the data writing into each antenna is completed.
According to a preferred embodiment, the system further includes, after step S4, performing the following steps: s5: and verifying the data written into each antenna to be processed.
According to a preferred embodiment, the step S5 is: and reading the data written into each antenna, comparing the read data with theoretical data written into the PC, and verifying that the written data is correct if the comparison is consistent.
According to a preferred embodiment, the step S5 is specifically: the PC computer issues a reading operation instruction of the antenna 1, and then issues a reading operation instruction of the antenna 2 after the data of the antenna 1 is returned, and waits for the data of the antenna 2 to be returned until the Nth antenna data return is received, and the reading operation is finished; the PC computer compares the received read FLASH data with the write FLASH data, and the comparison is consistent, thereby indicating that the data writing is correct.
The aforementioned main aspects of the invention and their respective further alternatives can be freely combined to form a plurality of aspects, all of which are aspects that can be adopted and claimed by the present invention. The skilled person in the art can understand that there are many combinations, which are all the technical solutions to be protected by the present invention, according to the prior art and the common general knowledge after understanding the scheme of the present invention, and the technical solutions are not exhaustive herein.
The invention has the beneficial effects that: in the system, the data is written into the FLASH through the synchronous serial port of the main control equipment, the data needs to be transmitted on the synchronous serial port, the FLASH chip also needs to consume time during data writing operation, and data is written into other antennas in the time period, so that the time for writing the data in batches can be obviously shortened, and the production efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of the system of the present invention;
FIG. 2 is a schematic diagram of the time required to program antenna data without using the master control device in the system of the present invention;
FIG. 3 is a schematic diagram showing the time required for programming antenna data when the main control device in the system of the present invention is used;
FIG. 4 is a time difference diagram of data programming of 1 antenna using the system of the present invention for 12 antennas in accordance with conventional techniques;
FIG. 5 is a flow chart illustrating a FLASH write operation performed by the system of the present invention;
FIG. 6 is a flow chart of the FLASH read operation performed by the system of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that, in order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are clearly and completely described below, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments.
Referring to fig. 1, the invention discloses a system for improving the production efficiency of phased array antennas, which comprises a PC computer and a main control device, wherein the PC computer is connected with the main control device through a USB interface, and the main control device is respectively connected with N antennas to be processed through synchronous serial ports.
Preferably, the master control device receives data sent by the PC through the USB interface, and sends the received data to the downstream N antennas to be processed through the synchronous serial port by a time division multiplexing method.
Time division multiplexing TDM is to transmit different signals in different time periods of the same physical connection, and can also achieve the purpose of multiplexing. Time division multiplexing uses time as a parameter for signal division, and therefore, it is necessary to prevent signals from overlapping each other on the time axis. Time-division multiplexing (TDM) divides the Time provided for the whole channel to transmit information into a plurality of Time slices (Time slots for short), and allocates the Time slots to each signal source for use, thereby ensuring the utilization rate of resources.
The communication rate of the USB interface can still reach more than 30Mbps after protocol overhead is removed, and the writing rate of a single byte of FLASH in each antenna is 1.3Mbps, so that theoretically one main control board can be simultaneously connected with 23 antennas (30 is divided by 1.3, and the whole is equal to 23), namely N is less than or equal to 23.
When the main control equipment receives the data sent by the PC computer, the data are sequentially sent to each antenna. Thus, 23 antenna data can be programmed in the past time of programming 1 antenna data, and the speed is improved by 23 times. The lifting effect is very obvious.
In the actual design, the power consumption of the whole power supply, the theoretical time margin and the like are integrated, and a 1-to-12 master control device is designed, namely the rear end can be connected with 12 antennas at most. And meanwhile, 12 antennae are connected, the power consumption of a power supply is relatively small, and the data writing time margin completely meets the theoretical time.
Specifically, in the conventional solution, the time for writing one antenna data is shown in fig. 2, the time required for writing one antenna data is T1, and then the time required for 12 antennas is 12 × T1.
However, after the system of the present invention is adopted and 1-to-12 master control devices are adopted, the time for writing 12 antenna data is shown in fig. 3. It can be seen from the figure that the system of the present invention well utilizes the programming time of 1 byte written by 1 antenna, adopts the time division multiplexing technology, and sequentially writes 1 byte to 12 antennas within the time of writing 1 byte, and the time of writing 12 antennas is T2. The time required to write data for 12 antennas is compared as shown in fig. 4. As can be seen from the figure, the time taken to write data of 12 antennas (T2) and the time taken to write data of 1 antenna (T1) are increased by only one byte of programming time, which is very short (in microseconds) and can be ignored. The time for writing 12 antennas is still T1, the efficiency is improved by 12 times.
Specifically, referring to fig. 5, the process of writing data to each antenna to be processed by the system of the present invention includes the following steps:
step S1: the PC computer issues an instruction for setting the number of the antennas.
Specifically, in step S1, the PC issues an instruction for setting the number of antennas based on the system performance index, and completes the setting of the number of antennas to be processed.
For example, the upper computer sets the number of the access antennas, and may set the access antennas to 5 antennas in order to enhance adaptability, and then the issued instruction only traverses 5 antennas in sequence, so that time is saved, and system jamming caused by failure to detect the returned data of the antennas is prevented.
Step S2: and erasing each antenna to be processed.
The step S2 specifically includes: the host computer issues an entire erasing command of the antenna 1, then issues an entire erasing command … of the antenna 2, and finally issues an entire erasing command of the antenna N. And after the data erasure of each antenna is successful, feeding back an erasure success command to the PC computer.
Furthermore, an instruction storage space is arranged in the main control device and used for finishing caching feedback instructions of all antennas and then sending the feedback data to the PC. The corresponding data is transferred once through the instruction storage space of the main control equipment, so that the problem of instruction conflict caused by the fact that the returned instruction simultaneously reaches an upper computer (namely a PC) is solved.
Step S3: and setting a writing FLASH address for each antenna to be processed.
Step S4: and carrying out data writing operation on each antenna to be processed.
Step S4 includes: the PC computer firstly issues 1 byte data of the antenna 1, then 1 byte data of the antenna 2, and so on, and finally issues 1 byte data of the antenna N to complete a cycle; when m data are required to be written into each antenna, m cycles are carried out, and the data writing into each antenna is completed. If 1000 data are required to be written to the antenna, the above operation is cycled 1000 times.
Step S5: and verifying the data written into each antenna to be processed.
Step S5 includes: and reading the data written into each antenna, comparing the read data with theoretical data written into the PC computer, and verifying that the written data is correct if the comparison is consistent.
Further, refer to fig. 6. Step S5 specifically includes: the PC computer issues a reading operation instruction of the antenna 1, and then issues a reading operation instruction of the antenna 2 after the data of the antenna 1 is returned, waits for the data of the antenna 2 to be returned, and so on until the Nth antenna data return is received, and the reading operation is finished; the PC computer compares the received read FLASH data with the write FLASH data, and the comparison is consistent, thereby indicating that the data writing is correct.
In the system, the data is written into the FLASH through the synchronous serial port of the main control equipment, the data needs to be transmitted on the synchronous serial port, the FLASH chip also needs to consume time during data writing operation, and data is written into other antennas in the time period, so that the time for writing the data in batches can be obviously shortened, and the production efficiency is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (8)
1. A system for improving the production efficiency of phased array antennas is characterized by comprising a PC (personal computer) and a main control device, wherein the PC is connected with the main control device through a USB (universal serial bus) interface, and the main control device is respectively connected with N antennas to be processed through synchronous serial ports;
the main control equipment receives data sent by a PC through a USB interface, respectively sends the received data to N downstream antennas to be processed through synchronous serial ports by a time division multiplexing method, completes data programming of each antenna, and stores the written data in FLASH of each antenna, wherein N is less than or equal to 23.
2. The system for improving phased array antenna production efficiency as claimed in claim 1, wherein said master control device has 12 interfaces and is connected to 12 antennas to be processed respectively.
3. The system for improving phased array antenna production efficiency according to claim 1, wherein the system comprises the following steps in the process of writing data on each antenna to be processed:
s1: the PC computer issues an instruction for setting the number of the antennas;
s2: erasing each antenna to be processed;
s3: setting FLASH addresses for storing write-in data for each antenna to be processed;
s4: and carrying out data writing operation on each antenna to be processed.
4. The system for improving phased array antenna production efficiency according to claim 3, wherein said step S1 is specifically: and the PC computer issues an instruction for setting the number of the antennas based on the system performance index to complete the setting of the number of the antennas to be processed.
5. The system for improving phased array antenna production efficiency according to claim 3, wherein said step S2 is specifically:
the PC computer firstly issues a whole-chip erasing instruction of the antenna 1, then issues a whole-chip erasing instruction of the antenna 2, and finally sends a whole-chip erasing instruction of the antenna N;
and after the data erasure of each antenna is successful, feeding back an erasure success command to the PC computer.
6. The system for improving phased array antenna production efficiency as claimed in claim 5, wherein said main control device is provided with an instruction storage space for buffering feedback instructions of each antenna and then sending the feedback data to the PC.
7. The system for improving phased array antenna production efficiency according to claim 5, wherein said step S4 is specifically:
the upper computer firstly issues 1 byte data of the antenna 1, and then 1 byte data of the antenna 2, and a cycle is completed until 1 byte data of the last antenna N is issued;
when m data are required to be written into each antenna, m cycles are carried out, and the data writing into each antenna is completed.
8. The system for improving phased array antenna production efficiency according to claim 3, wherein the system further comprises after step S4, the following steps:
s5: and verifying the data written into each antenna to be processed.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210295701.7A CN114385093A (en) | 2022-03-24 | 2022-03-24 | System for promoting phased array antenna production efficiency |
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| CN202210295701.7A CN114385093A (en) | 2022-03-24 | 2022-03-24 | System for promoting phased array antenna production efficiency |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101271440A (en) * | 2008-04-14 | 2008-09-24 | 杭州华三通信技术有限公司 | Multi-serial port implementing method and apparatus |
| CN109597630A (en) * | 2019-01-29 | 2019-04-09 | 珠海迈科智能科技股份有限公司 | A kind of P2MP software programming device and method with detection function |
| CN110873826A (en) * | 2018-08-31 | 2020-03-10 | 罗克韦尔柯林斯公司 | Antenna array test circuit, phased antenna array and method for testing phased antenna array |
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- 2022-03-24 CN CN202210295701.7A patent/CN114385093A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101271440A (en) * | 2008-04-14 | 2008-09-24 | 杭州华三通信技术有限公司 | Multi-serial port implementing method and apparatus |
| CN110873826A (en) * | 2018-08-31 | 2020-03-10 | 罗克韦尔柯林斯公司 | Antenna array test circuit, phased antenna array and method for testing phased antenna array |
| CN109597630A (en) * | 2019-01-29 | 2019-04-09 | 珠海迈科智能科技股份有限公司 | A kind of P2MP software programming device and method with detection function |
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