CN114361171A

CN114361171A - Manufacturing method of semiconductor structure and semiconductor structure

Info

Publication number: CN114361171A
Application number: CN202210036332.XA
Authority: CN
Inventors: 郭帅
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-01-13
Filing date: 2022-01-13
Publication date: 2022-04-15
Also published as: WO2023133966A1

Abstract

The manufacturing method comprises the steps of providing an initial structure, wherein the initial structure comprises a laminated structure, the laminated structure comprises an initial inter-gate dielectric layer and a first sacrificial layer which are alternately laminated, and the initial inter-gate dielectric layer comprises a first gate dielectric layer, a second sacrificial layer and a second gate dielectric layer; forming a channel groove in the laminated structure, wherein part of the initial inter-gate dielectric layer and part of the first sacrificial layer are exposed out of the channel groove; forming a channel structure in the channel groove, wherein the channel structure fills the channel groove; removing the first sacrificial layer, and forming a grid electrode conducting layer at the position of the first sacrificial layer; and removing the second sacrificial layer, and forming an air gap layer between the first gate dielectric layer and the second gate dielectric layer. In the present disclosure, an air gap layer is formed between two adjacent gate conductive layers in a semiconductor structure, and the presence of the air gap layer can reduce capacitive coupling between the gate conductive layers because air has a low dielectric constant.

Description

Manufacturing method of semiconductor structure and semiconductor structure

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure and a semiconductor structure.

Background

With the development of integrated circuit technology, in order to achieve higher storage density, 3D (3 dimensional) flash memory (NAND flash memory) is developed very rapidly, the number of layers of 3D flash memory stacks is increasing, and the number of layers is increasing from 32 layers to 128 layers, and the number of layers of stacks is also increasing. However, as the number of layers of the 3D flash memory stack increases, the capacitive coupling effect of the 3D flash memory may further increase.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The disclosure provides a manufacturing method of a semiconductor structure and the semiconductor structure.

A first aspect of the present disclosure provides a method for fabricating a semiconductor structure, the method comprising:

providing an initial structure, wherein the initial structure comprises a laminated structure, the laminated structure comprises initial inter-gate dielectric layers and first sacrificial layers which are alternately superposed, and the initial inter-gate dielectric layers comprise first gate dielectric layers, second sacrificial layers and second gate dielectric layers which are sequentially superposed;

forming a channel groove in the laminated structure, wherein the channel groove extends along the laminating direction of the laminated structure, and a part of the initial inter-gate dielectric layer and a part of the first sacrificial layer are exposed out of the channel groove;

forming a channel structure in the channel groove, wherein the channel structure fills the channel groove;

removing the first sacrificial layer, and forming a grid electrode conducting layer at the position of the first sacrificial layer;

and removing the second sacrificial layer, and forming an air gap layer between the first gate dielectric layer and the second gate dielectric layer.

According to some embodiments of the present disclosure, the method for manufacturing a semiconductor structure further comprises:

before the channel structure is formed in the channel groove, removing a part of the initial inter-gate dielectric layer or a part of the first sacrificial layer exposed by the channel groove, and forming a concave part on the side wall of the channel groove, wherein the concave part is concave towards the inside of the laminated structure along the transverse direction.

forming a first insulating layer in the channel groove, wherein the first insulating layer covers the exposed side wall and the exposed bottom wall of the channel groove and the exposed side wall and the exposed bottom wall of the recessed part;

forming a charge storage layer covering the first insulating layer in the recess and filling the recess;

and forming a second insulating layer which covers the charge storage layer and the first insulating layer positioned on the side wall of the channel groove.

According to some embodiments of the present disclosure, the forming of the channel structure in the channel trench includes:

forming a channel layer, wherein the channel layer covers the second insulating layer and the first insulating layer positioned on the bottom wall of the channel groove;

and forming a third insulating layer which covers the channel layer and fills the vacant region in the channel groove.

According to some embodiments of the present disclosure, the initial structure further comprises a substrate, the stacked structure being formed on the substrate; the removing the first sacrificial layer and forming a gate conductive layer at the position where the first sacrificial layer is removed includes:

forming a first trench in the stacked structure, wherein the first trench penetrates through the stacked structure along a stacking direction of the stacked structure and exposes a part of the substrate, and a sidewall of the first trench exposes a part of the first sacrificial layer;

removing the first sacrificial layer based on the first groove to form a first gap;

and filling a conductive material into the first gap through the first groove to form the gate conductive layer.

According to some embodiments of the present disclosure, the removing the second sacrificial layer to form an air gap layer between the first gate dielectric layer and the second gate dielectric layer further includes:

and removing the second sacrificial layer based on the first groove, forming the air gap layer at the position where the second sacrificial layer is removed, and separating the first gate dielectric layer and the second gate dielectric layer by the air gap layer.

forming a first barrier layer in the first trench, the first barrier layer covering sidewalls of the first trench and closing the air gap layer;

and forming a first conductive layer which covers the first barrier layer and fills the first groove.

and forming an epitaxial layer, wherein the epitaxial layer is arranged between the channel structure and the substrate, and the bottom surface of the channel structure is in contact connection with the epitaxial layer.

According to some embodiments of the present disclosure, a depth of the first trench is greater than a depth of the channel trench, and the first gap also exposes a portion of the epitaxial layer; the manufacturing method of the semiconductor structure further comprises the following steps:

and forming a second barrier layer on the part of the epitaxial layer exposed by the first gap.

A second aspect of the present disclosure provides a semiconductor structure comprising:

a substrate;

the grid laminated structure comprises grid conducting layers and inter-grid dielectric layers which are alternately laminated, the inter-grid dielectric layers comprise air gap layers and first grid dielectric layers and second grid dielectric layers which are separated by the air gap layers, the first grid dielectric layers and the second grid dielectric layers of the inter-grid dielectric layers respectively cover the adjacent grid conducting layers, and a channel groove is formed in the grid laminated structure and extends along the laminating direction of the grid laminated structure;

the channel structure is arranged in the channel groove and is in contact connection with the substrate.

According to some embodiments of the present disclosure, the semiconductor structure further comprises:

the storage assembly is arranged in the grid conducting layer or the inter-grid dielectric layer, the storage assembly is arranged around the circumference of the channel structure, and the storage assembly is in contact with the channel structure.

According to some embodiments of the disclosure, the storage component comprises:

the charge storage layer is arranged in the grid conducting layer or the inter-grid dielectric layer;

a first insulating layer disposed between the charge storage layer and the gate conductive layer, or disposed between the charge storage layer and the inter-gate dielectric layer;

a second insulating layer disposed between the charge blocking layer and the channel structure.

According to some embodiments of the disclosure, the channel structure comprises:

a functional wall surface covering a part of a sidewall of the channel groove and a bottom wall of the channel groove;

a channel layer covering the functional wall surface;

a third insulating layer covering the channel layer and filling the remaining portion of the channel trench that is not filled.

a first trench penetrating the gate stack structure in a stacking direction of the gate stack structure;

and the gate gap structure is filled in the first groove and comprises a first barrier layer and a first conductive layer.

the epitaxial layer is arranged between the substrate and the channel structure, the bottom surface of the channel structure is in contact connection with the substrate through the epitaxial layer, and part of the gate conducting layer is arranged around the circumference of the epitaxial layer.

a second barrier layer disposed between a portion of the gate conductive layer and the epitaxial layer.

In the method for manufacturing the semiconductor structure and the semiconductor structure provided by the embodiment of the disclosure, the air gap layer is formed between two adjacent gate conductive layers in the semiconductor structure, and because air has a low dielectric constant, the capacitive coupling between the gate conductive layers can be reduced due to the existence of the air gap layer.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. For a person skilled in the art, other figures can be derived from these figures without inventive effort.

FIG. 1 is a flow chart illustrating a method of fabricating a semiconductor structure according to an exemplary embodiment.

FIG. 2 is a flow chart illustrating a method of fabricating a semiconductor structure according to an exemplary embodiment.

Fig. 3 is a flow chart illustrating the formation of a channel structure according to an example embodiment.

FIG. 4 is a cross-sectional view of the A-A plane of an initial structure shown in accordance with an exemplary embodiment.

FIG. 5 is a cross-sectional view illustrating the formation of the A-A side of a first photoresist layer according to an exemplary embodiment.

Fig. 6 is a cross-sectional view of an a-a face forming a channel trench, shown in accordance with an exemplary embodiment.

Fig. 7 is a cross-sectional view of a-a plane of an epitaxial layer shown formed according to an exemplary embodiment.

Fig. 8 is a cross-sectional view of an a-a face forming a first insulating layer, shown according to an example embodiment.

Fig. 9 is a cross-sectional view illustrating a-a plane where a charge storage layer is formed according to an exemplary embodiment.

Fig. 10 is a cross-sectional view illustrating a-a plane where a second insulating layer is formed according to an exemplary embodiment.

Fig. 11 is a cross-sectional view illustrating an a-a plane where a channel layer is formed, according to an example embodiment.

Fig. 12 is a cross-sectional view illustrating a-a plane where a third insulating layer is formed according to an exemplary embodiment.

FIG. 13 is a cross-sectional view illustrating the B-B side of the formation of a second photoresist layer according to an exemplary embodiment.

Fig. 14 is a cross-sectional view illustrating a B-B surface forming a first trench according to an exemplary embodiment.

Fig. 15 is a top view of fig. 14.

FIG. 16 is a cross-sectional view of a B-B surface forming a first gap shown in accordance with an exemplary embodiment.

Fig. 17 is a cross-sectional view of a B-B plane illustrating the formation of a second barrier layer and an oxide layer, according to an example embodiment.

Fig. 18 is a cross-sectional view of a B-B surface illustrating the deposition of conductive material into a first trench, according to an example embodiment.

Fig. 19 is a cross-sectional view illustrating a B-B plane forming a gate conductive layer according to an example embodiment.

FIG. 20 is a cross-sectional view of a B-B surface forming a first gap shown in accordance with an exemplary embodiment.

Fig. 21 is a partially enlarged view at a of fig. 20.

Fig. 22 is a cross-sectional view of a deposited barrier material covering the B-B face of the sidewalls and bottom wall of the first trench, according to an example embodiment.

Fig. 23 is a cross-sectional view illustrating a B-B plane forming a first barrier layer according to an example embodiment.

FIG. 24 is a cross-sectional view of a B-B plane of a formed semiconductor structure shown in accordance with an exemplary embodiment.

FIG. 25 is a cross-sectional view of the A-A face forming a depression shown according to an exemplary embodiment.

Fig. 26 is a cross-sectional view illustrating a-a plane where a first insulating layer is formed according to an exemplary embodiment.

FIG. 27 is a cross-sectional view illustrating depositing a conductive material to fill the A-A face of the recess, according to an example embodiment.

Fig. 28 is a cross-sectional view illustrating a-a plane where a charge storage layer is formed according to an exemplary embodiment.

Fig. 29 is a cross-sectional view illustrating a-a plane where a second insulating layer is formed according to an exemplary embodiment.

Fig. 30 is a cross-sectional view illustrating an a-a plane where a channel layer is formed, according to an example embodiment.

Fig. 31 is a cross-sectional view illustrating a-a plane where a third insulating layer is formed according to an exemplary embodiment.

FIG. 32 is a cross-sectional view of an A-A plane of a formed semiconductor structure shown in accordance with an exemplary embodiment.

FIG. 33 is a cross-sectional view of a B-B plane of a formed semiconductor structure shown in accordance with an exemplary embodiment.

FIG. 34 is a cross-sectional view of a-A plane forming a recess, shown according to an exemplary embodiment.

FIG. 35 is a cross-sectional view of an A-A plane of a formed semiconductor structure shown in accordance with an exemplary embodiment.

FIG. 36 is a cross-sectional view of a B-B plane of a formed semiconductor structure shown in accordance with an exemplary embodiment.

Reference numerals:

01. a first gap; 02. an air gap layer; 10. a first photoresist layer; 20. a second photoresist layer; 100. an initial structure; 110. a substrate; 111. an isolation layer; 112. an epitaxial layer; 113. a second barrier layer; 114. an oxide layer; 200. a laminated structure; 200a, a gate stack structure; 210. an initial inter-gate dielectric layer; 211. a first gate dielectric layer; 212. a second sacrificial layer; 213. a second gate dielectric layer; 220. a first sacrificial layer; 230. a bottom layer laminated structure; 230a, a bottom gate stack structure; 231. a first material layer; 232. a third material layer; 240. a top insulating layer; 250. a gate conductive layer; 270. an inter-gate dielectric layer; 300. a channel groove; 310. a recessed portion; 400. a channel structure; 410. a first insulating layer; 420. a charge storage layer; 430. a second insulating layer; 440. a channel layer; 450. a third insulating layer; 460. a storage component; 470. a functional wall surface; 500. a first trench; 600. a gate gap structure; 610. a first barrier layer; 620. a first conductive layer.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

In an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, as shown in fig. 1, fig. 1 is a flowchart illustrating a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure, and fig. 4 to 36 are schematic diagrams illustrating various stages of the method for manufacturing a semiconductor structure, which is described below with reference to fig. 4 to 36.

In this embodiment, the semiconductor structure is not limited, and the semiconductor structure is a Dynamic Random Access Memory (DRAM) as an example, but the present embodiment is not limited thereto, and the semiconductor structure in this embodiment may be other structures.

In this embodiment, reference is made to FIG. 15 for the A-A section and the B-B section.

As shown in fig. 1, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps:

step S110: providing an initial structure, wherein the initial structure comprises a laminated structure, the laminated structure comprises initial inter-gate dielectric layers and first sacrificial layers which are alternately laminated, and the initial inter-gate dielectric layers comprise first gate dielectric layers, second sacrificial layers and second gate dielectric layers which are sequentially laminated.

As shown in fig. 4, the initial structure 100 includes a substrate 110 and a stacked structure 200 disposed on the substrate 110. The initial inter-gate dielectric layer 210 and the first sacrificial layer 220 of the stacked structure 200 may be stacked with 2 to 1024 layers or more alternately, for example, 48, 64, 128, 256, 512 layers, or the like may be stacked alternately. In some embodiments, the initial structure 100 further comprises an isolation layer 111 disposed on the top surface of the substrate 110, and the material of the isolation layer 111 comprises Boro-phospho-silicate Glass (BPSG).

The substrate 110 may be a semiconductor substrate, and the semiconductor substrate may include a Silicon substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, an SOI (Silicon-on-Insulator) substrate, a GOI (Germanium-on-Insulator) substrate, or the like. The semiconductor substrate may be doped with ions, for example, the semiconductor substrate may be a P-type doped substrate or an N-type doped substrate. In the present embodiment, the substrate 110 is a silicon crystal substrate.

The first sacrificial layers 220 and the initial inter-gate dielectric layers 210 are alternately stacked on the substrate 110 in a direction perpendicular to the substrate 110, and the initial inter-gate dielectric layers 210 include a first gate dielectric layer 211, a second sacrificial layer 212, and a second gate dielectric layer 213 which are sequentially stacked. That is, the first sacrificial layer 220 is separated from its adjacent second sacrificial layer 212 by the first gate dielectric layer 211 or by the second gate dielectric layer 213.

The first sacrificial layer 220 includes a first material, and the first material may include one or more of silicon nitride or silicon oxynitride. The second sacrificial layer 212 comprises a second material comprising a semiconductor material, for example the second material may comprise one or more of monocrystalline silicon, polycrystalline silicon or amorphous silicon. The second material comprises a semiconductor material which may be an intrinsic semiconductor material or a doped semiconductor material. The first gate dielectric layer 211 comprises a third material comprising an oxide, for example the third material may comprise silicon oxide. The second gate dielectric layer 213 includes a third material thereon. The first material has a high etch selectivity relative to the second material, the first material has a high etch selectivity relative to the third material, and the second material has a high etch selectivity relative to the third material.

As shown in fig. 4, the stacked structure 200 further includes a bottom stacked structure 230, the bottom stacked structure 230 is disposed at the bottom of the stacked structure 200, and the initial inter-gate dielectric layer 210 and the first sacrificial layer 220 which are alternately disposed are located above the bottom stacked structure 230. The bottom laminate structure 230 includes first material layers 231 and third material layers 232 alternately stacked on the isolation layer 111, and the first material layers 231 and the third material layers 232 of the bottom laminate structure 230 are alternately stacked by 2-4 layers.

The stacked structure 200 further comprises a top insulating layer 240, the top insulating layer 240 is disposed on the topmost layer of the stacked structure 200, and the material of the top insulating layer 240 comprises silicon oxide.

In some embodiments, the stacked structure 200 may further include a top-layer stacked structure (not shown) disposed below the top-layer insulating layer 240 and above the initial inter-gate dielectric layer 210 and the first sacrificial layer 220 which are alternately stacked. The top layer laminated structure comprises a first material layer and a third material layer which are alternately stacked, and the first material layer and the third material layer of the top layer laminated structure can be alternately stacked for 2-4 layers.

In the present embodiment, referring to fig. 4, in providing the initial structure 100, the following method may be employed:

a substrate 110 is provided, and an isolation layer 111 is formed on the substrate 110. First material layers 231 and third material layers 232 are alternately formed, and a bottom layer stack structure 230 is formed on the isolation layer 111. In the process of forming the first material Layer 231 and the third material Layer 232, any one of a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, or a sputtering process may be selected.

Then, a first sacrificial layer 220, a first gate dielectric layer 211, a second sacrificial layer 212 and a second gate dielectric layer 213 are sequentially formed through any one of the deposition processes, the first gate dielectric layer 211, the second sacrificial layer 212 and the second gate dielectric layer 213 jointly form an initial inter-gate dielectric layer 210, the process of forming the first sacrificial layer 220 and the initial inter-gate dielectric layer 210 is repeated for multiple times, and the initial inter-gate dielectric layer 210 and the first sacrificial layer 220 which are alternately stacked are formed on the bottom-layer stacked structure 230. Next, an insulating material is deposited by any of the above deposition processes to form a top insulating layer 240, thereby forming the stacked structure 200.

Step S120: and forming a channel groove in the laminated structure, wherein the channel groove extends along the laminating direction of the laminated structure, and part of the initial inter-gate dielectric layer and part of the first sacrificial layer are exposed out of the channel groove.

As shown in fig. 5 and 6, referring to fig. 4, the following method may be employed in forming the channel trench 300 in the stacked structure 200:

forming a first photoresist layer 10 on the top surface of the stacked structure 200, patterning the first photoresist layer 10, etching the stacked structure 200 according to the first photoresist layer 10 to transfer the pattern of the first photoresist layer 10 into the stacked structure 200 until a portion of the substrate 110 is exposed, and forming a channel 300. The channel trench 300 extends toward the substrate 110 in the stacking direction of the stacked structure 200, a portion of the top surface of the substrate 110 is exposed by the channel trench 300 or the bottom surface of the channel trench 300 is lower than the top surface of the substrate 110, and a portion of the initial inter-gate dielectric layer 210 and a portion of the first sacrificial layer 220 are exposed by the wall of the channel trench 300. In the present embodiment, the sidewalls of the channel trench 300 also expose a portion of the first material layer 231 and a portion of the third material layer 232 of the underlying stacked structure 230.

In other embodiments, the sidewalls of the trench 300 also expose a portion of the first material layer and a portion of the third material layer of the top layer stack structure.

In the present embodiment, as shown in fig. 6, referring to fig. 15, a plurality of channel grooves 300 are formed in the stacked structure 200, the plurality of channel grooves 300 are hole-type structures penetrating the stacked structure 200, and the plurality of channel grooves 300 are provided independently.

As shown in fig. 7, referring to fig. 6, after forming the channel groove 300, an epitaxial layer 112 is formed on the substrate 110 exposed by the channel groove 300. In this embodiment, the substrate 110 exposed by the trench 300 is placed in a reaction chamber as a seed crystal, a gas source for forming the epitaxial layer 112 is introduced into the reaction chamber, and the epitaxial layer 112 is formed by epitaxial growth using a chemical vapor deposition process. The material of epitaxial layer 112 may include silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the epitaxial layer 112 is a silicon epitaxial layer, the epitaxial layer 112 may be doped with conductive ions, may be doped with P-type doped ions, may be doped with N-type doped ions, and the types of the conductive ions doped in the epitaxial layer 112 and the substrate 110 may be the same or different. In this embodiment, the top surface of the epitaxial layer 112 and the top surface of the bottom layer stack 230 are substantially flush.

Step S130: a channel structure is formed in the channel trench, the channel structure filling the channel trench.

As shown in fig. 11 and 12, forming the channel structure 400 includes: the channel layer 440 is formed in the channel trench 300, the channel layer 440 covers sidewalls and a bottom wall of the channel trench 300, a third insulation layer 450 is formed, and the third insulation layer 450 covers the channel layer 440 and fills other regions of the channel trench 300 that are not filled.

In the present embodiment, as shown in fig. 8 to 10, before forming the channel layer 440, the method further includes: in the channel groove 300, a first insulating layer 410, a charge storage layer 420 and a second insulating layer 430 are sequentially formed from outside to inside along the radial direction of the channel groove 300, the first insulating layer 410 covers the side wall and the bottom surface of the channel groove 300, the charge storage layer 420 covers the first insulating layer 410 on the side wall of the channel groove 300, and the second insulating layer 430 covers the charge storage layer 420. The channel structure 400 is separated from a subsequently formed gate conductive layer by a first insulating layer 410, a charge storage layer 420 and a second insulating layer 430.

Step S140: and forming a first groove in the laminated structure, wherein the first groove penetrates through the laminated structure along the stacking direction of the laminated structure and exposes a part of the substrate, and the side wall of the first groove exposes a part of the first sacrificial layer and a part of the second sacrificial layer.

As shown in fig. 13, 14, and 15, a second photoresist layer 20 is formed on the top surface of the stacked structure 200, the stacked structure 200 is etched according to the second photoresist layer 20 to form a first trench 500, the first trench 500 extends into the substrate 110 along the stacking direction of the stacked structure 200, and the bottom surface of the first trench 500 is lower than the bottom surface of the channel trench 300. The sidewalls of the first trench 500 expose a portion of the first sacrificial layer 220 and a portion of the initial inter-gate dielectric layer 210. The first trench 500 also exposes a portion of the first material layer 231 and a portion of the third material layer 232 of the underlying stacked structure 230.

Step S150: and removing the first sacrificial layer, and forming a gate conductive layer at the position of the first sacrificial layer.

The first sacrificial layer 220 is removed based on the first trench 500 to form a first gap 01, and then, a conductive material is filled into the first gap 01 through the first trench 500 to form a gate conductive layer 250.

When the first gap 01 is formed, as shown in fig. 16, referring to fig. 15, an etching solution is injected into the first trench 500, the first material for forming the first sacrificial layer 220 is dissolved in the etching solution, and the second material for forming the second sacrificial layer 212 and the third material for forming the first gate dielectric layer 211 and the second gate dielectric layer 213 are not dissolved in the etching solution. For example, the etching solution may be hot phosphoric acid, and the etching solution dissolves all the first sacrificial layer 220, and then the etching solution dissolving the first sacrificial layer 220 is removed, so as to form the first gap 01 at the position of the first sacrificial layer 220. In the present embodiment, the first material layer 231 in the bottom stacked structure 230 is also removed, that is, the first gap 01 is also formed at the position where the first material layer 231 is located.

Then, as shown in fig. 18, a conductive material, which is a conductive metal, for example, Titanium (Titanium), tantalum (tantalum), Tungsten (Tungsten), or an alloy thereof, is deposited into the first trench 500 by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or a sputtering process. After the first gap 01 and the first trench 500 are filled with the conductive material, as shown in fig. 19, referring to fig. 18, the conductive material in the first trench 500 is etched back and removed, and the remaining conductive material is located in the first gap 01 to form the gate conductive layer 250.

In some embodiments, the stack structure 200 further comprises a top-layer stack structure, in which the first material layer is also etched away, and a gate conductive layer is formed in the position of the first material layer of the top-layer stack structure.

Since the first gap 01 formed in the underlying stacked structure 230 exposes a portion of the epitaxial layer 112, as shown in fig. 17, referring to fig. 16, in the present embodiment, before depositing the conductive material into the first trench 500, the method further includes: a second barrier layer 113 is formed on the portion of the epitaxial layer 112 exposed by the first gap 01. For example, the epitaxial layer exposed by the first gap 01 may be thermally oxidized, and the surface of the epitaxial layer 112 exposed by the first gap 01 may be oxidized to form the second barrier layer 113. In this embodiment, the surface of the substrate 110 exposed by the first trench 500 is oxidized while the epitaxial layer 112 is thermally oxidized, so that the oxide layer 114 is formed on the surface of the exposed substrate 110, and the presence of the oxide layer 114 can prevent the conductive material deposited in the first trench 500 from diffusing into the substrate 110 to contaminate the substrate 110. In the present embodiment, when the conductive material in the first trench 500 is etched back, the oxide layer 114 on the surface of the substrate 110 is used as an etch stop layer.

Step S160: and removing the second sacrificial layer, and forming an air gap layer between the first gate dielectric layer and the second gate dielectric layer.

In this embodiment, the second sacrificial layer 212 is removed based on the first trench 500, the air gap layer 02 is formed at the position where the second sacrificial layer 212 is removed, and the first gate dielectric layer 211 and the second gate dielectric layer 213 are separated by the air gap layer 02.

As shown in fig. 20 and 21, referring to fig. 19, the second sacrificial layer 212 exposed by the first trench 500 is dry etched to form an air gap layer 02, after the second sacrificial layer 212 is removed, the first gate dielectric layer 211 and the second gate dielectric layer 213 originally belonging to the same initial inter-gate dielectric layer 200 are separated, and the first gate dielectric layer 211 and the second gate dielectric layer 213 are respectively connected to the upper and lower gate conductive layers 250.

In the manufacturing method of the embodiment, the air gap layer is formed between the two gate conductive layers by removing the second sacrificial layer, air has a low dielectric constant, and the existence of the air gap layer can reduce capacitive coupling between the gate conductive layers. In this embodiment, the initial inter-gate dielectric layer is configured to include a first gate dielectric layer, a second sacrificial layer, and a second gate dielectric layer that are stacked in sequence, and a distance between two adjacent gate conductive layers is larger, so that capacitive coupling between the gate conductive layers can be further reduced, and in a process of removing the second sacrificial layer, the first gate dielectric layer and the second gate dielectric layer can also protect the gate conductive layers from being damaged by etching.

In some embodiments, after step S160 is completed, as shown in fig. 1, the following steps are further included:

step S170: a first barrier layer is formed in the first trench, covering sidewalls of the first trench and closing the air gap layer.

As shown in fig. 22, a barrier material is deposited by a chemical vapor deposition process or an atomic layer deposition process, the barrier material covers the sidewalls of the first trench 500 and closes the side opening of the air gap layer 02, the barrier material also covers the bottom wall of the first trench 500, as shown in fig. 23, and then the barrier material covering the bottom wall of the first trench 500 is etched back to remove, and the remaining barrier material forms a first barrier layer 610. After the first barrier layer 610 is formed, the oxide layer 114 on the bottom wall of the first trench 500 is etched away to expose the substrate 110. The material of the first barrier layer 610 may be silicon oxide or silicon oxynitride.

In the embodiment, the thickness of the air gap layer formed by removing the second sacrificial layer is smaller, and when the blocking material is deposited, the side opening of the air gap layer can be sealed by the blocking material, so that the effect that the blocking material is deposited in the air gap layer to reduce the capacitive coupling of the gate conductive layer by the air gap layer is avoided.

Step S180: and forming a first conductive layer which covers the first barrier layer and fills the first groove.

As shown in fig. 24, a dielectric material is deposited by a chemical vapor deposition process or a physical deposition process, and the dielectric material fills the unfilled region of the first trench 500, forming a first conductive layer 620. The material of the first conductive layer 620 includes silicon oxide or silicon oxynitride. The first barrier layer 610 and the first conductive layer 620 form a gate slit structure 600.

In the manufacturing method of the embodiment, the gate gap structure is formed in the first trench, so that the structure of the formed semiconductor structure is more complete, and the stability of the semiconductor structure is improved. In this embodiment, the initial inter-gate dielectric layer includes a first gate dielectric layer, a second sacrificial layer, and a second gate dielectric layer that are stacked in sequence, so that the thickness of the formed air gap layer is small while the space between two adjacent gate conductive layers is large enough, thereby reducing the difficulty in sealing the air gap layer.

According to an exemplary embodiment, a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is provided, as shown in fig. 2, fig. 2 shows a flowchart of a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure, steps S210 to S220 of the present embodiment are implemented in the same manner as steps S110 to S120 of the above embodiment, and steps S250 to S290 of the present embodiment are implemented in the same manner as steps S140 to S180 of the above embodiment, and the present embodiment is different from the above embodiment in that, in the implementation process, before forming a channel structure in a channel groove, the following steps are further included:

step S230: and removing part of the initial inter-gate dielectric layer or part of the first sacrificial layer exposed by the channel groove, and forming a concave part on the side wall of the channel groove, wherein the concave part is concave towards the inside of the laminated structure along the transverse direction.

The recess 310 may be recessed laterally into the initial intergate dielectric layer 210, as shown in fig. 25, or the recess 310 may be recessed laterally into the first sacrificial layer 220, as shown in fig. 34.

In some embodiments, as shown in fig. 25, a recess 310 is formed in the initial inter-gate dielectric layer 210 at the side circumference of the trench 300 by etching a portion of the initial inter-gate dielectric layer 210 exposed by the sidewall of the trench 300 through the trench 300. In other words, in the present embodiment, the sidewalls of the trench 300 are processed such that the trench width of the trench 300 in the initial intergate dielectric layer 210 is greater than the trench width in the first sacrificial layer 220. In this embodiment, the portion of the initial inter-gate dielectric layer 210 exposed by the sidewall of the trench 300 is etched by an isotropic etching process, and the etching process etches the second material and the third material with a high etching selectivity relative to the etching process etching the first material.

In some embodiments, as shown in fig. 34, the recess 310 is formed by channel trench etching the portion of the first sacrificial layer 220 exposed by the sidewalls of the channel trench 300, the recess 310 being laterally recessed into the first sacrificial layer 220 from the circumferential sidewalls of the channel trench 300. That is, after the process of this step, the trench width of the trench 300 in the first sacrificial layer 220 is larger than that in the initial intergate dielectric layer 210. In this embodiment, a portion of the first sacrificial layer 220 exposed by the sidewall of the trench 300 is etched by an isotropic etching process, the first sacrificial layer 220 includes a first material, the second sacrificial layer 212 includes a second material, the first gate dielectric layer 211 and the second gate dielectric layer 212 include a third material, and the etching process etches the first material with a high etching selectivity with respect to the etching process that etches the second material and the third material.

In the present implementation, as shown in fig. 3, step S240: forming a channel structure in the channel trench, comprising the steps of:

step S241: and forming a first insulating layer in the channel groove, wherein the first insulating layer covers the exposed side wall and the exposed bottom wall of the channel groove and the exposed side wall and the exposed bottom wall of the recessed part.

In the embodiment, the recess 310 is recessed into the initial inter-gate dielectric layer 210 along the lateral direction, as shown in fig. 26, a first insulating layer 410 may be formed by depositing an insulating material through an atomic layer deposition process, the first insulating layer 410 covers the inner wall of the recess 310 and the sidewalls and the bottom wall of the trench 300, and the material of the first insulating layer 410 includes silicon oxide or silicon oxynitride.

Step S242: and forming a charge storage layer which covers the first insulating layer in the concave part and fills the concave part.

As shown in fig. 27, a conductive material may be deposited through an atomic layer deposition process, the conductive material covering the first insulating layer 420 in the recess 310 and filling the recess 310, and the conductive material further covering the first insulating layer 410 in the channel groove 300, as shown in fig. 28, referring to fig. 27, the conductive material in the channel groove 300 is etched back, and the remaining conductive material forms a plurality of charge storage layers 420 independently disposed in the plurality of recesses 310. The material of the charge storage layer 420 includes one or more of single crystal silicon, polycrystalline silicon, or amorphous silicon. In the present embodiment, the material of the charge storage layer 420 includes polysilicon.

Step S243: and forming a second insulating layer which covers the charge storage layer and the first insulating layer on the side wall of the channel groove.

As shown in fig. 29, a deposited insulating material may be formed by an atomic layer deposition process, the insulating material covers the exposed surface of the charge storage layer 420, the first insulating layer 410 on the sidewall of the channel groove 300, and the first insulating layer 410 on the bottom wall of the channel groove 300, the insulating material on the bottom wall of the channel groove 300 is etched back to remove, and the remaining insulating material forms a second insulating layer 430, and the material of the second insulating layer 430 includes silicon oxide or silicon oxynitride.

Step S244: and forming a channel layer, wherein the channel layer covers the second insulating layer and the first insulating layer positioned on the bottom wall of the channel groove.

As shown in fig. 30, a conductive material may be deposited into the channel groove 300 by an atomic layer deposition process, the conductive material covering the second insulating layer 430 and the first insulating layer 410 at the bottom wall of the channel groove 300, forming a channel layer 440. The material of the channel layer 440 includes one or more of single crystal silicon, polycrystalline silicon, or amorphous silicon. In the present embodiment, the material of the channel layer 440 includes polysilicon.

Step S245: and forming a third insulating layer which covers the channel layer and fills the vacant region in the channel groove.

As shown in fig. 31, an insulating material may be deposited through a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, the insulating material fills the unfilled region in the channel trench 300, and a third insulating layer 450 is formed, and the material of the third insulating layer 450 includes silicon oxide or silicon oxynitride.

As shown in fig. 32, when the channel layer 440 and the third insulating layer 450 are formed, a portion of the remaining channel layer 440 and the third insulating layer 450 is covered on the top insulating layer 240, and in order to remove the remaining channel layer 440 and the third insulating layer 450, the remaining channel layer 440 and the third insulating layer 450 covering the top insulating layer 240 are etched back to remove the first insulating layer 410 as an etch stop layer.

As shown in fig. 32, which is a cross-sectional view of the a-a plane of the semiconductor structure formed in the present embodiment; as shown in fig. 33, which is a cross-sectional view of the B-B plane of the semiconductor structure formed in this embodiment. The channel layer 440 and the third insulating layer 450 form a channel structure 400, the bottom surface of the channel structure 400 being in contact connection with the epitaxial layer 112 through the first insulating layer 410. The first insulating layer 410, the charge storage layer 420 and the second insulating layer 430 covering the charge storage layer 420 in the recess 310 form a memory element 460, and the first insulating layer 410 and the second insulating layer 430 on the sidewall of the channel trench 300 and the first insulating layer 410 on the bottom wall of the channel trench 300 form a functional wall 470.

In the semiconductor structure formed in the embodiment, the storage component arranged around the circumferential direction of the channel structure is formed on the side wall of the channel structure, the storage component can increase the storage capacity of the semiconductor structure, and the concave part is sunken into the initial gate dielectric layer, so that more space is reserved for forming the gate conductive layer, and the storage capacity of the formed semiconductor structure is higher.

In other embodiments, the recess 310 is recessed into the first sacrificial layer 220 along the lateral direction, as shown in fig. 35, which is a cross-sectional view of the a-a surface of the semiconductor structure formed in the present embodiment; as shown in fig. 36, which is a cross-sectional view of the B-B plane of the semiconductor structure formed in this embodiment. The memory element 460 is disposed around the circumference of the channel structure 400, and the memory element 460 is disposed in the gate conductive layer 250, the air gap layer 02 is increased, and the semiconductor structure has a better effect of preventing capacitive coupling.

In an exemplary embodiment of the present disclosure, a semiconductor structure is provided, as shown in fig. 24, 33, and 36, the semiconductor structure includes a substrate 110, and a gate stack structure 200a disposed on the substrate 110. The gate stack structure 200a includes a gate conductive layer 250 and an inter-gate dielectric layer 270 stacked alternately, and the inter-gate dielectric layer 270 includes an air gap layer 02 and a first gate dielectric layer 211 and a second gate dielectric layer 213 separated by the air gap layer 02. The first gate dielectric layer 211 and the second gate dielectric layer 213 of the inter-gate dielectric layer 270 respectively cover the adjacent gate conductive layers 250, a channel groove 300 is disposed in the gate stack structure 200a, and the channel groove 300 extends along the stacking direction of the gate stack structure 200 a. The semiconductor structure further comprises a channel structure 400, the channel structure 400 being arranged in the channel trench 300, the channel structure 400 being in contact with the substrate 110.

In the present embodiment, an isolation layer 111 is further disposed on the substrate 110, and the gate stack structure 200a is disposed on the isolation layer 111. The gate stack structure 200a further includes a bottom gate stack structure 230a, and the bottom gate stack structure 230a includes a gate metal layer 250 and a third material layer 232 that are alternately stacked.

The semiconductor structure further comprises an epitaxial layer 112, the epitaxial layer 112 is arranged between the substrate 110 and the channel structure 400, the bottom surface of the channel structure 400 is in contact connection with the substrate 110 through the epitaxial layer 112, and part of the gate conductive layer 250 is arranged around the circumference of the epitaxial layer 112.

In the present embodiment, the top surface of the epitaxial layer 112 is substantially flush with the top surface of the bottom gate stack structure 230a, i.e., the gate conductive layer 250 in the bottom gate stack structure 230a is disposed around the circumference of the epitaxial layer 112. A second barrier layer 113 is disposed between the epitaxial layer 112 and the gate conductive layer 250 to prevent the material of the gate conductive layer 250 from penetrating into the epitaxial layer 112 to contaminate the epitaxial layer 112 and the substrate 110.

According to an exemplary embodiment, as shown in fig. 33 and fig. 36, the semiconductor structure further includes a memory component 460, the memory component 460 is disposed in the gate conductive layer 250 or the inter-gate dielectric layer 270, the memory component 250 is disposed around the circumference of the channel structure 400, and the memory component 400 is in contact with the channel structure.

According to an exemplary embodiment, as shown in fig. 33, a storage element 460 may be located at the gate conductive layer 250; as shown in fig. 36, a memory element 460 may also be located in the intergate dielectric layer 270. As shown in fig. 33 and 36, the memory element 460 includes a charge storage layer 420, a first insulating layer 410, and a second insulating layer 430 disposed between the charge storage layer 420 and the channel structure 400. In some embodiments, as shown in fig. 33, the first insulating layer 410 in the memory component 460 is disposed between the charge storage layer 420 and the gate conductive layer 250. In other embodiments, as shown in FIG. 36, a first insulating layer 410 is disposed between the charge storage layer 420 and the intergate dielectric layer 270.

In the present embodiment, as shown in fig. 33, or as shown in fig. 36, the channel structure 400 further includes a functional wall 470, a channel layer 440, and a third insulating layer 450, the functional wall 470 includes a first insulating layer 410 and a second insulating layer 430 covering a portion of the sidewall of the channel groove 300, and the functional wall 470 further includes the first insulating layer 410 covering the bottom wall of the channel groove 300. The channel layer 440 covers the functional walls 470 and the second insulating layer 430 of the memory element 460. The third insulating layer 450 covers the channel layer 440 and fills the remaining portion of the channel groove 300 that is not filled.

As shown in fig. 33 or fig. 36, the semiconductor structure of the present embodiment further includes a first trench 500 and a gate gap structure 600 filled in the first trench 500, wherein the first trench 500 penetrates the gate stack structure 200a along the stacking direction of the gate stack structure 200a, and the bottom surface of the first trench 500 is lower than the bottom surface of the channel trench 300. The gate slit structure 600 includes a first conductive layer 620 and a first barrier layer 610 between the first conductive layer 620 and the gate stack structure 200 a.

In the semiconductor structure of this embodiment, the air gap layer 02 is disposed between two adjacent gate conductive layers 250, and air in the air gap layer 02 has a low dielectric constant, so that interference between the gate conductive layers 250 can be reduced, and capacitive coupling can be reduced. In addition, in the semiconductor structure of the present embodiment, the memory element 460 circumferentially disposed around the channel structure 400 is disposed on the sidewall of the channel structure 400, and the memory element 460 increases the memory capacity of the semiconductor structure.

The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

In the description herein, references to the terms "embodiment," "exemplary embodiment," "some embodiments," "illustrative embodiments," "example" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing and simplifying the present disclosure, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like as used in this disclosure may be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

Like elements in one or more of the drawings are referred to by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Numerous specific details of the present disclosure, such as structure, materials, dimensions, processing techniques and techniques of the devices, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; while the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims

1. A method for fabricating a semiconductor structure, the method comprising:

2. The method of claim 1, further comprising:

3. The method of claim 2, further comprising:

4. The method of claim 3, wherein forming a channel structure in the channel trench comprises:

5. The method of claim 1, wherein the initial structure further comprises a substrate, the stacked structure being formed on the substrate; the removing the first sacrificial layer and forming a gate conductive layer at the position where the first sacrificial layer is removed includes:

6. The method of claim 5, wherein the step of removing the second sacrificial layer to form an air gap layer between the first gate dielectric layer and the second gate dielectric layer further comprises:

7. The method of claim 6, further comprising:

8. The method of claim 7, further comprising:

9. The method of claim 8, wherein a depth of the first trench is greater than a depth of the channel trench, and the first gap further exposes a portion of the epitaxial layer; the manufacturing method of the semiconductor structure further comprises the following steps:

10. A semiconductor structure, comprising:

a substrate;

11. The semiconductor structure of claim 10, further comprising:

12. The semiconductor structure of claim 11, wherein the memory component comprises:

13. The semiconductor structure of claim 12, wherein the channel structure comprises:

a channel layer covering the functional wall surface;

14. The semiconductor structure of claim 10, further comprising:

15. The semiconductor structure of claim 10, further comprising:

16. The semiconductor structure of claim 15, further comprising: