CN114361159A - Semiconductor device, three-dimensional memory having the same, and memory system - Google Patents
Semiconductor device, three-dimensional memory having the same, and memory system Download PDFInfo
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Abstract
The application provides a semiconductor device, a three-dimensional memory having the same and a memory system. The semiconductor device includes: a semiconductor substrate; the transistor structures are arranged on one side of the semiconductor substrate at intervals along a first direction, each transistor structure comprises a grid electrode, a grid dielectric layer and a source/drain region, the grid dielectric layers and the grid electrodes are arranged on the surface of the semiconductor substrate in a stacked mode, the source/drain regions are located in the semiconductor substrate on two sides of the grid electrodes, and adjacent source/drain regions located on the same side of the grid electrodes do not overlap after extending along the first direction; and the conductive channels are arranged on the semiconductor substrate and are connected with the source/drain regions positioned at two sides of the grid electrode. According to the method and the device, the size of the source/drain region can be further extended along the arrangement direction of each transistor structure under the condition that the whole process layout area of the semiconductor device is not changed, so that the process window of the contact hole for arranging the conductive channel can be enlarged, and the flexibility of device design is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a three-dimensional memory having the same, and a memory system.
Background
As the demand for integration and storage capacity continues to increase, 3D NAND memories have come into play. The 3D NAND memory greatly saves the area of a silicon chip, reduces the manufacturing cost and increases the storage capacity.
In the 3D NAND memory structure, a stacked 3D NAND memory structure is implemented by vertically stacking multiple layers of data storage units, however, other circuits such as decoders (decoders), page buffers (page buffers), latches (latches), and the like are formed by CMOS devices, and the processes of the CMOS devices cannot be integrated with the 3D NAND devices. In the current process, a 3D NAND memory array and peripheral circuits are formed by different processes, and then bonded together by a bonding technique.
In the current process of CMOS in 3D NAND memory, the requirements on the CMOS process are higher and higher, especially in the aspect of size reduction. In an Active Area (AA) of the device, a source/drain area is used for being connected with a conductive channel in a contact hole (CT) to lead out a lead, the size of the source/drain area is enlarged, although the window of the CT process can be enlarged, the requirement on the process layout area (space) is higher, the size of the device is not reduced, and the flexibility of the device design is limited.
Disclosure of Invention
The present disclosure is directed to a semiconductor device, a three-dimensional memory having the same, and a storage system, so as to solve the problem in the prior art that the size of the semiconductor device is difficult to further shrink, which results in the limitation of flexibility of device design.
In order to achieve the above object, according to one aspect of the present application, there is provided a semiconductor device including: a semiconductor substrate; the transistor structures are arranged on one side of the semiconductor substrate at intervals along a first direction, each transistor structure comprises a grid electrode, a grid dielectric layer and a source/drain region, the grid dielectric layers and the grid electrodes are arranged on the surface of the semiconductor substrate in a stacked mode, the source/drain regions are located in the semiconductor substrate on two sides of the grid electrodes, and adjacent source/drain regions located on the same side of the grid electrodes do not overlap after extending along the first direction; and the conductive channels are arranged on the semiconductor substrate and are connected with the source/drain regions positioned at two sides of the grid electrode.
Furthermore, the semiconductor substrate comprises fin body sections corresponding to the transistor structures one to one, the fin body sections are located between source/drain regions of the same transistor structure, the grid electrode is arranged across the fin body sections, and the grid medium layer is at least arranged between the grid electrode and the fin body sections.
Furthermore, the source/drain regions positioned on the same side of the grid electrode are arranged in a staggered mode along the first direction; or the grid electrode has a first projection region on the surface of the semiconductor substrate, and the minimum distance between each source/drain region positioned on the same side of the grid electrode and the first projection region increases progressively along a first direction; or the grid electrode has a first projection area on the surface of the semiconductor substrate, and the minimum distance between each source/drain area positioned on the same side of the grid electrode and the first projection area is increased gradually and then decreased gradually along the first direction; or the grid electrode has a first projection area on the surface of the semiconductor substrate, and the minimum distance between each source/drain area positioned on the same side of the grid electrode and the first projection area is decreased gradually and then increased gradually along the first direction.
Furthermore, in the same transistor structure, the conductive channel has a second projection region on the surface of the semiconductor substrate, the source/drain region on the side of the gate electrode has a third region on the surface of the semiconductor substrate, and the length of the second projection region along the first direction is L1The length of the third region along the first direction is L2，L2＞2L1。
Further, in the same transistor structure, the source/drain region on the gate side has a third region on the surface of the semiconductor substrate, and the length of the third region along the first direction is L2The length of the third region along the second direction is L3，L2＞L3The second direction is perpendicular to the first direction.
Furthermore, in the same transistor structure, the grid electrode has a first projection region on the surface of the semiconductor substrate, and the distance between the source/drain region and the first projection region is H1，H1≤100nm。
Furthermore, the semiconductor device further comprises isolation structures located on two sides of the fin body section along the first direction, the isolation structures are used for separating the semiconductor substrate into a plurality of active regions, the gate dielectric layer and the gate electrode are at least arranged on the surfaces of the active regions in a stacked mode, and the source/drain regions are located in the active regions on two sides of the gate electrode.
According to another aspect of the present application, there is provided a method for manufacturing the semiconductor device, including the steps of: providing a semiconductor substrate; forming a plurality of transistor structures arranged at intervals along a first direction on one side of a semiconductor substrate, wherein each transistor structure comprises a grid electrode, a grid dielectric layer and a source/drain region; and forming a plurality of conductive channels on the semiconductor substrate, wherein the conductive channels are connected with the source/drain regions positioned at two sides of the grid electrode.
According to another aspect of the present application, there is also provided a three-dimensional memory including a memory array, peripheral circuitry, and an interconnect layer, the memory array and the peripheral circuitry being bonded through the interconnect layer, the peripheral circuitry including the semiconductor device described above.
According to another aspect of the present application, there is also provided a storage system including a controller and a three-dimensional memory, the three-dimensional memory being configured to store data, the controller being coupled to the three-dimensional memory and being configured to control the three-dimensional memory, the three-dimensional memory being the three-dimensional memory described above.
By applying the technical scheme of the application, the semiconductor device comprises a semiconductor substrate, a plurality of transistor structures and a plurality of conductive channels, wherein the transistor structures are arranged on one side of the semiconductor substrate at intervals along a first direction, a gate dielectric layer and a gate of each transistor structure are arranged on the surface of the semiconductor substrate in a stacked mode, a source/drain region of each transistor structure is located in the semiconductor substrate on two sides of the gate, and adjacent source/drain regions located on the same side of the gate are not overlapped after extending along the first direction. The transistor structure adopting the X-FET structure can narrow the active region, but the difficulty of the contact hole process for forming the conductive channel is increased, and the adjacent source/drain regions positioned on the same side of the grid electrode do not overlap after extending along the first direction.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 is a schematic diagram illustrating a partial top view structure of a semiconductor device provided in an embodiment of the present application;
fig. 2 is a schematic diagram illustrating a partial top view structure of another semiconductor device provided in an embodiment of the present application;
fig. 3 is a schematic diagram illustrating a partial top view structure of another semiconductor device provided in an embodiment of the present application;
fig. 4 is a schematic cross-sectional view of a region a in the semiconductor device shown in fig. 1 in the X direction;
fig. 5 is a schematic top view of a region B of the semiconductor device shown in fig. 1;
fig. 6 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram illustrating a three-dimensional memory according to an embodiment of the present application;
fig. 8 shows a schematic structural diagram of a storage system provided in an embodiment of the present application.
Wherein the figures include the following reference numerals:
10. a semiconductor substrate; 110. a fin section; 210. a gate electrode; 220. a gate dielectric layer; 230. a source/drain region; 30. a conductive channel; 40. an isolation structure; 300. a three-dimensional memory; 301. a memory array; 302. a peripheral circuit; 303. an interconnect layer; 400. a storage system; 401. a three-dimensional memory; 402. and a controller.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As described in the background, in the current CMOS process in 3D NAND memory, the requirements for CMOS process are higher and higher, especially in the aspect of size reduction. In an Active Area (AA) of the device, a source/drain area is used for being connected with a conductive channel in a contact hole (CT) to lead out a lead, the size of the source/drain area is enlarged, although the window of the CT process can be enlarged, the requirement on the process layout area (space) is higher, the size of the device is not reduced, and the flexibility of the device design is limited.
In order to solve the above problem, an embodiment of the present invention provides a semiconductor device, as shown in fig. 1 to fig. 3, including a semiconductor substrate 10, a plurality of transistor structures and a plurality of conductive vias 30, where the plurality of transistor structures are disposed at intervals along a first direction on one side of the semiconductor substrate 10, each transistor structure includes a gate 210, a gate dielectric layer 220 and a source/drain region 230, the gate dielectric layer 220 and the gate 210 are stacked on a surface of the semiconductor substrate 10, the source/drain regions 230 are located in the semiconductor substrate 10 on both sides of the gate 210, and adjacent source/drain regions 230 located on the same side of the gate 210 do not overlap after extending along the first direction (X direction); a plurality of conductive vias 30 are disposed on the semiconductor substrate 10, and the conductive vias 30 are disposed in connection with the source/drain regions 230 located at both sides of the gate electrode 210.
The adjacent source/drain regions 230 on the same side of the gate electrode 210 do not overlap after extending along the first direction (X direction), which is to be understood that the adjacent source/drain regions 230 on the same side of the gate electrode 210 do not overlap after extending along the arrangement direction of the transistor structure, as shown in fig. 1.
The transistor structure adopting the X-FET structure can narrow the active region, but the difficulty of the contact hole process for forming the conductive channel is increased, and the adjacent source/drain regions positioned on the same side of the grid electrode do not overlap after extending along the first direction.
The material of the semiconductor substrate 10 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.
The transistor structure in the embodiment of the application is an X-FET structure. For example, the semiconductor substrate 10 may include fin segments 110 corresponding to one-to-one transistor structures, the fin segments 110 being located between source/drain regions 230 of the same transistor structure, and the gate 210 being disposed across the fin segments 110, and the gate dielectric layer 220 being at least disposed between the gate 210 and the fin segments 110, as shown in fig. 4. The arrangement mode of the gate 210 can narrow the active region, thereby being beneficial to the reduction of the process layout and further being beneficial to the miniaturization of the device.
The gate 210 may be a polysilicon layer, and the gate dielectric layer 220 may be silicon oxide. The gate 210 may further include a work function layer, the work function layer may be a plurality of layers, the material forming the work function layer includes, but is not limited to, a combination of a metal material, a silicide material, an insulator material, and the like, and those skilled in the art may adjust each work function layer constituting the gate 210 according to actual needs. The transistor structure may further include side walls (not shown) located at two sides of the gate 210, where the side walls are used to define a distance between a source and a drain of the transistor structure and protect the work function layer.
The semiconductor device according to the embodiment of the present invention may further include isolation structures 40 located at two sides of the fin body 110 along the first direction, as shown in fig. 4, the isolation structures 40 are used to separate the semiconductor substrate 10 into a plurality of active regions, the gate dielectric layer 220 and the gate 210 are stacked and disposed at least on the surface of the active regions, and the source/drain regions 230 are located in the active regions at two sides of the gate 210.
The isolation structure 40 may be a structure formed by a Shallow Trench Isolation (STI) process, and the material forming the isolation structure 40 may be an insulating material, such as silicon oxide, which is conventional in the art.
In the above semiconductor device of the present application, adjacent source/drain regions 230 located on the same side of the gate electrode 210 do not overlap after extending in the first direction. In an alternative embodiment, as shown in fig. 1, the source/drain regions 230 located on the same side of the gate electrode 210 are staggered along the first direction.
The way to achieve non-overlapping after extending the adjacent source/drain regions 230 on the same side of the gate 210 along the first direction is not limited to the above-mentioned embodiment, but in another alternative embodiment of the present application, as shown in fig. 2, the gate 210 has a first projected area on the surface of the semiconductor substrate 10, and the minimum distance between each source/drain region 230 on the same side of the gate 210 and the first projected area increases along the first direction. It should be noted that the first direction is not limited to the x direction shown in fig. 2, but may be the direction opposite to the x direction in fig. 2, in which case, the minimum distance between each source/drain region 230 and the first projection region on the same side of the gate electrode 210 increases in the direction opposite to the x direction (contrary to the variation trend in fig. 2).
In other alternative embodiments, the gate electrode 210 has a first projected area on the surface of the semiconductor substrate 10, and the minimum distance between each source/drain region 230 located on the same side of the gate electrode 210 and the first projected area decreases and increases along the first direction, or the minimum distance between each source/drain region 230 located on the same side of the gate electrode 210 and the first projected area increases and decreases along the first direction, as shown in fig. 3.
The source/drain regions 230 may be formed according to a conventional ion implantation process and an annealing process in the prior art, and a person skilled in the art may reasonably select the types of the implanted ions according to the prior art, which is not described in detail herein.
In the semiconductor device of the present application, the plurality of conductive vias 30 are disposed on the semiconductor substrate 10, and the conductive vias 30 are disposed in connection with the source/drain regions 230 located at two sides of the gate 210, and since the adjacent source/drain regions 230 located at the same side of the gate 210 do not overlap after extending along the first direction, the source/drain regions 230 can laterally expand along the first direction, so as to expand the process window of the contact hole for disposing the conductive via 30.
In an alternative embodiment of the present application, as shown in fig. 1 and 5, in the same transistor structure, the conductive channel 30 has a second projection region on the surface of the semiconductor substrate 10, the source/drain region 230 on the side of the gate 210 has a third region on the surface of the semiconductor substrate 10, and the second projection region has a length L along the first direction1The length of the third region along the first direction is L2，L2＞2L1Wherein the first direction is an X direction shown in fig. 1. In the above embodiment, the source/drain regions 230 have a larger size by lateral expansion, and the process window for providing the contact hole of the conductive via 30 is enlarged.
In an alternative embodiment of the present application, as shown in fig. 1 and 5, the source/drain regions 230 on one side of the gate 210 are in the semiconductor substrate in the same transistor structureThe surface of the bottom 10 has a third area with a length L along the first direction2The length of the third region along the second direction is L3，L2＞L3And a second direction perpendicular to the first direction, wherein the first direction is an X direction shown in fig. 1, and the second direction is a Y direction shown in fig. 1. In the above-described embodiment, the source/drain regions 230 have a large size by lateral expansion, thereby facilitating the implementation of the contact hole process for disposing the conductive vias 30.
In an alternative embodiment of the present application, the source/drain regions 230 in each transistor structure have the same pitch. With the above embodiments, the staggered arrangement of the adjacent source/drain regions 230 on the same side of the gate 210 can be more easily achieved, which facilitates the process layout design of the device.
In the alternative embodiment described above, the conductive vias 30 on both sides of the gate 210 in each transistor structure are preferably equally spaced. With the above preferred embodiment, the lateral extension of the process window for forming the contact hole (CT) of the conductive channel 30 in the arrangement direction of the transistor structure can be facilitated, and the flexibility of the device design is further improved.
In an alternative embodiment of the present application, in the first direction, the spaced apart source/drain regions 230 on the same side of the gate electrode 210 are completely overlapped after extending along the first direction, as shown in fig. 1. By adopting the embodiment, the process layout design of the device can be simpler.
In the above alternative embodiment, each conductive via 30 preferably has a first projection area on the surface of the source/drain region 230, and the first projection areas spaced on the same side of the gate electrode 210 extend along the first direction and then overlap. With the above preferred embodiment, the lateral extension of the process window for forming the contact hole (CT) of the conductive channel 30 in the arrangement direction of the transistor structure can be facilitated, and the flexibility of the device design is further improved.
In an alternative embodiment of the present application, as shown in fig. 2, in the same transistor structure, the gate 210 has a first projection area on the surface of the semiconductor substrate 10, and the source/drain region in each transistor structure230 is spaced from the first projection region by a distance H1，H1Less than or equal to 100 nm. With the preferred embodiment, flexibility of staggered arrangement between adjacent source/drain regions 230 located on the same side of the gate 210 can be ensured without increasing the overall layout area of the semiconductor device.
In an alternative embodiment of the present application, the projected areas of the source/drain regions 230 on both sides of the gate electrode 210 in each transistor structure on the surface of the semiconductor substrate 10 are equal. By adopting the embodiment, the contact hole process window of the conductive channel 30 connected with the source/drain region 230 in the same transistor structure can be favorably formed to carry out uniform size expansion, so that the process layout design of the device is simpler.
In an alternative embodiment of the present application, the projected areas of the source/drain regions 230 on the same side of the gate electrode 210 on the surface of the semiconductor substrate 10 are equal. By adopting the embodiment, the process window for forming the contact hole (CT) of the conductive channel 30 can be favorably and uniformly expanded in the arrangement direction of the transistor structure, so that the process layout design of the device is simpler.
According to an embodiment of the present application, there is also provided a method for manufacturing the semiconductor device, as shown in fig. 6, including the following steps:
providing a semiconductor substrate;
forming a plurality of transistor structures arranged at intervals along a first direction on one side of a semiconductor substrate, wherein each transistor structure comprises a grid electrode, a grid dielectric layer and a source/drain region;
and forming a plurality of conductive channels on the semiconductor substrate, wherein the conductive channels are connected with the source/drain regions positioned at two sides of the grid electrode.
The transistor structure adopting the X-FET structure can narrow the active region, but the difficulty of the contact hole process for forming the conductive channel is increased, and the adjacent source/drain regions positioned on the same side of the grid electrode do not overlap after extending along the first direction.
According to another aspect of the present application, there is also provided a three-dimensional memory 300, as shown in fig. 7, including a memory array 301, a peripheral circuit 302 and an interconnection layer 303, where the memory array 301 and the peripheral circuit 302 are bonded and connected through the interconnection layer 303, the peripheral circuit 302 includes the above semiconductor device or the semiconductor device obtained by the above manufacturing method, and a conductive channel in the semiconductor device is connected with the interconnection layer 303.
Because the adjacent source/drain regions positioned on the same side of the grid electrode in the three-dimensional memory are arranged in a staggered mode along the first direction, compared with the prior art, the size of the source/drain regions can be further extended along the arrangement direction of each transistor structure under the condition that the whole process layout area of a semiconductor device is not changed, so that the window of a contact hole process for forming a conductive channel is expanded, and the flexibility of device design is improved.
Illustratively, the three-dimensional memory is a 3D NAND memory. The stacked 3D NAND memory structure can be implemented in a manner of vertically stacking a plurality of layers of data storage units. In order to obtain the stacked 3D NAND memory structure, a stacked structure in which sacrificial layers and isolation layers are alternately stacked may be formed on a substrate, a channel via may be formed by etching the stacked structure, a memory structure may be formed in the channel via, a gate spacer may be formed in the stacked structure, the sacrificial layer may be removed to fill a gate in contact with the memory structure, and a common source may be formed in the gate spacer. The memory structure is used for bonding with peripheral circuits through an interconnection layer.
The embodiment of the present disclosure also provides a storage system 400, as shown in fig. 8, including a three-dimensional memory 401 and a controller 402, where the three-dimensional memory 401 is configured to store data, and the controller 402 is coupled to the three-dimensional memory 401 and configured to control the three-dimensional memory 401, where the three-dimensional memory 401 includes the above-mentioned semiconductor device, as shown in fig. 1 to 5, or where the three-dimensional memory 401 includes the semiconductor device obtained by the above-mentioned manufacturing method, as shown in fig. 6.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
the transistor structure adopting the X-FET structure can narrow the active region, but the difficulty of the contact hole process for forming the conductive channel is increased, and the adjacent source/drain regions positioned on the same side of the grid electrode do not overlap after extending along the first direction.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A semiconductor device, comprising:
a semiconductor substrate;
the transistor structures are arranged on one side of the semiconductor substrate at intervals along a first direction, each transistor structure comprises a grid electrode, a grid dielectric layer and a source/drain region, the grid dielectric layers and the grid electrodes are arranged on the surface of the semiconductor substrate in a stacked mode, the source/drain regions are located in the semiconductor substrate on two sides of the grid electrodes, and adjacent source/drain regions located on the same side of the grid electrodes do not overlap after extending along the first direction;
and the conductive channels are arranged on the semiconductor substrate and are connected with the source/drain regions positioned at two sides of the grid electrode.
2. The semiconductor device of claim 1, wherein the semiconductor substrate comprises fin segments corresponding to the transistor structures one to one, the fin segments being located between the source/drain regions of the same transistor structure, and wherein the gate is disposed across the fin segments, and wherein the gate dielectric layer is disposed at least between the gate and the fin segments.
3. The semiconductor device according to claim 1 or 2,
the source/drain regions positioned on the same side of the grid electrode are arranged in a staggered mode along the first direction; or
The grid electrode is provided with a first projection region on the surface of the semiconductor substrate, and the minimum distance between each source/drain region positioned on the same side of the grid electrode and the first projection region increases progressively along a first direction; or
The grid electrode is provided with a first projection region on the surface of the semiconductor substrate, and the minimum distance between each source/drain region positioned on the same side of the grid electrode and the first projection region is increased gradually and then decreased gradually along a first direction; or
The grid electrode is provided with a first projection region on the surface of the semiconductor substrate, and the minimum distance between each source/drain region positioned on the same side of the grid electrode and the first projection region is decreased gradually and then increased gradually along a first direction.
4. The semiconductor device according to claim 1 or 2, wherein the conductive channel has a second projected area on the surface of the semiconductor substrate, and the source/drain region on the gate side has a third area on the surface of the semiconductor substrate in the same transistor structure, and the second projected area has a length L along the first direction1The length of the third region along the first direction is L2，L2＞2L1。
5. The semiconductor device according to claim 1 or 2, wherein the source/drain region on the gate side is on the surface of the semiconductor substrate in the same transistor structureThe face has a third region having a length L in the first direction2The length of the third area along the second direction is L3，L2＞L3The second direction is perpendicular to the first direction.
6. The semiconductor device according to claim 1 or 2, wherein the gate electrode has a first projected area on the surface of the semiconductor substrate in the same transistor structure, and the source/drain region is spaced apart from the first projected area by a distance H1，H1≤100nm。
7. The semiconductor device of claim 2, further comprising isolation structures located on two sides of the fin body along the first direction, wherein the isolation structures are configured to separate the semiconductor substrate into a plurality of active regions, the gate dielectric layer and the gate stack are at least disposed on a surface of the active regions, and the source/drain regions are located in the active regions on two sides of the gate.
8. A method for manufacturing a semiconductor device according to any one of claims 1 to 7, comprising the steps of:
providing a semiconductor substrate;
forming a plurality of transistor structures arranged at intervals along a first direction on one side of the semiconductor substrate, wherein each transistor structure comprises a grid electrode, a grid dielectric layer and a source/drain region, the grid dielectric layers and the grid electrodes are arranged on the surface of the semiconductor substrate in a stacked mode, the source/drain regions are located in the semiconductor substrate on two sides of the grid electrodes, and adjacent source/drain regions located on the same side of the grid electrodes do not overlap after extending along the first direction;
and forming a plurality of conductive channels on the semiconductor substrate, wherein the conductive channels are connected with the source/drain regions positioned at two sides of the grid electrode.
9. A three-dimensional memory comprising a memory array, peripheral circuitry and an interconnect layer, the memory array and the peripheral circuitry being bonded through the interconnect layer, characterized in that the peripheral circuitry comprises a semiconductor device according to any one of claims 1 to 7.
10. A storage system comprising a controller and a three-dimensional memory, the three-dimensional memory configured to store data, the controller coupled to the three-dimensional memory and configured to control the three-dimensional memory, wherein the three-dimensional memory is the three-dimensional memory of claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210039306.2A CN114361159A (en) | 2022-01-13 | 2022-01-13 | Semiconductor device, three-dimensional memory having the same, and memory system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210039306.2A CN114361159A (en) | 2022-01-13 | 2022-01-13 | Semiconductor device, three-dimensional memory having the same, and memory system |
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| CN202210039306.2A Pending CN114361159A (en) | 2022-01-13 | 2022-01-13 | Semiconductor device, three-dimensional memory having the same, and memory system |
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