CN114361144A - Substrate, integrated packaging device and manufacturing method of integrated packaging device - Google Patents
Substrate, integrated packaging device and manufacturing method of integrated packaging device Download PDFInfo
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- CN114361144A CN114361144A CN202111671191.0A CN202111671191A CN114361144A CN 114361144 A CN114361144 A CN 114361144A CN 202111671191 A CN202111671191 A CN 202111671191A CN 114361144 A CN114361144 A CN 114361144A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
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- 239000011159 matrix material Substances 0.000 claims abstract description 21
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- 238000003466 welding Methods 0.000 claims description 8
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
- H01L33/54—Encapsulations having a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
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Abstract
The invention discloses a substrate, an integrated packaging device and a manufacturing method of the integrated packaging device, wherein the substrate comprises a graphical conducting layer, an isolation structure layer and a chip bonding pad unit; the conducting layer is provided with at least three layers which are arranged in a laminated way; the isolation structure layer is provided with a plurality of layers and is respectively inserted between two adjacent conductive layers, and the isolation structure layer comprises a base body layer and at least one insulation layer; the chip bonding pad units are provided with a plurality of chips and are arranged into a matrix; each conducting layer of the non-bottom layer corresponds to at least one row of chip pad units respectively; the chip pad units are provided with a plurality of types and respectively correspond to the conductive layers, and the chip pad units are arranged on the isolation structure layer on the top layer; the bottom conducting layer is connected with each non-bottom conducting layer above the bottom conducting layer through a via hole respectively; the top conductive layer is connected with the corresponding chip bonding pad unit; the non-top conductive layers are respectively connected with the corresponding chip pad units through the communication holes. The invention can realize high resolution of the packaged device and reduce the packaging size.
Description
Technical Field
The invention belongs to the technical field of LED packaging, and particularly relates to a substrate, an integrated packaging device and a manufacturing method of the integrated packaging device.
Background
With the development of lighting technology, the LED light source is made into pixels, and the smart matrix lighting is becoming a development trend, and especially in the field of automotive intelligent lighting and display, the demand for a package structure compatible with higher pixels is increasingly urgent. In the prior art, a plurality of chips are respectively and independently packaged and then are mounted on a PCB, or a COB (chip on board) technology is adopted, the chips and a circuit board are bonded through leads, and then the chips and the leads are packaged by packaging adhesive.
The plurality of chips are packaged independently and then are attached to the PCB, so that on one hand, the size of the whole PCB is limited due to the large structure size of the packaged LED; on the other hand, after mounting, the distance between different pixels is large, high-resolution pixel display is difficult to realize, and light emission is not uniform.
And the chip and the circuit board are bonded by the lead by adopting a COB (chip on board) technology, and the chip and the lead are packaged by packaging glue, so that the packaging size is larger because the welding position of the lead needs to be reserved.
Therefore, a new technology is needed to solve the problem that the prior art package device is difficult to realize high resolution and has a large package size.
Disclosure of Invention
The invention provides a substrate, an integrated packaging device and a manufacturing method of the integrated packaging device, aiming at solving the problems that the packaging device in the prior art is difficult to realize high resolution and large in packaging size.
The invention adopts the following technical scheme:
a substrate is used for integrating and packaging a device and comprises a graphical conducting layer, an isolation structure layer and a chip pad unit;
the conducting layer is provided with at least three layers which are arranged in a laminated manner;
the isolation structure layer is provided with a plurality of layers, is respectively inserted between two adjacent conductive layers and is fixedly connected with the conductive layers, and comprises a base body layer and at least one insulating layer;
the chip bonding pad unit is used for connecting a light-emitting chip, is provided with a plurality of insulating structure layers on the top layer and is arranged in a matrix; each conducting layer of the non-bottom layer corresponds to at least one row of chip pad units respectively, and each row of chip pad units only corresponds to one conducting layer;
the chip pad units are provided with a plurality of types and respectively correspond to the conductive layers, and the chip pad units are arranged on the isolation structure layer on the top layer;
the bottom conducting layer is connected with each non-bottom conducting layer above the bottom conducting layer through a via hole respectively; the top conductive layer is connected with the corresponding chip bonding pad unit; the non-top conductive layers are respectively connected with the corresponding chip pad units through the communication holes.
In some embodiments, the top conductive layer includes a plurality of first edge pads and a plurality of first pattern leads, one end of each first pattern lead is connected to the corresponding first edge pad, and the other end of each first pattern lead is connected to the corresponding chip pad unit, and the first edge pads are connected to the bottom conductive layer through the via holes.
In some embodiments, the conductive layers located between the top conductive layer and the bottom conductive layer are inner conductive layers, each inner conductive layer includes a plurality of second edge pads, a plurality of second pattern leads, and a plurality of second connection pads, the second connection pads are connected to the second edge pads through the second pattern leads, the second connection pads are connected to the corresponding chip pad units through vias, and the second edge pads are connected to the bottom conductive layer through the vias;
the positions of the second edge bonding pad and the first edge bonding pad are staggered up and down, and the second connecting welding is opposite to the corresponding chip bonding pad unit up and down.
In some embodiments, the bottom conductive layer includes a number of third edge pads connected with the first edge pads or the second edge pads through the vias; the third edge pad is opposite to the first edge pad or the second edge pad connected to the third edge pad.
In some embodiments, the row of chip pad cells corresponding to the top conductive layer is located in an outermost row of the matrix.
In some embodiments, a solder resist layer and a thermally conductive layer are also included; the solder mask layer is arranged on the isolation structure layer of the top layer and covers the area of the isolation structure layer except the top layer conducting layer and the chip bonding pad unit; the heat conducting layer is arranged on the isolation structure layer of the bottom layer.
In some embodiments, the material of the substrate layer is a ceramic material including Al2O3Ceramics, AlN ceramics, Si3N4Ceramic or BeO ceramic.
In some embodiments, each of the chip pad units includes a positive pad and a negative pad, the matrix is divided into a plurality of rectangular functional regions, in the same functional region, the plurality of chip pad units are sequentially arranged, and the positive pad of one of the two adjacent chip pad units is connected with the negative pad of the other one.
An integrated packaging device comprises the substrate, and further comprises a plurality of light emitting chips, light conversion layers corresponding to the light emitting chips one to one, connecting glue layers, filling glue and a dam;
each light-emitting chip is connected with each chip bonding pad unit respectively; in the same functional region, all the light-emitting chips are sequentially and adjacently arranged without vacant positions;
the light conversion layer is fixed on the light emitting chip through the connecting adhesive layer, and the dam is fixed on the isolation structure layer on the top layer and surrounds the matrix; the filling glue is filled in the dam and filled in gaps among the light-emitting chips, the light conversion layers and the connecting glue layers.
A manufacturing method of an integrated packaging device adopts the substrate, and comprises the following steps:
s1, welding a plurality of light-emitting chips with the chip pad units, wherein in the same functional region, the light-emitting chips are sequentially and adjacently arranged without vacant positions;
s2, fixing the light conversion layers on the light emitting chips respectively through the connecting glue layer;
s3, forming a box dam surrounding the matrix on the isolation structure layer on the top layer by using colloid;
and S4, filling glue in the dam, so that the filling glue is filled in the dam and is filled in gaps among the light-emitting chips, the light conversion layers and the connecting glue layers.
Compared with the prior art, the invention has the beneficial effects that:
1. in the substrate, different conducting layers are arranged aiming at each chip bonding pad unit, and each imaged conducting layer is connected with the chip bonding pad unit through the through hole without being connected with an external lead, so that the space between each chip bonding pad unit can be tighter, when the substrate is used for integrating and packaging devices, the space between the light-emitting chips is smaller, the integrated packaging devices with higher pixels can be realized, and the size structure after packaging is smaller;
2. in the integrated packaging device, the substrate is adopted, the matrix of the chip bonding pad unit is divided into a plurality of rectangular functional areas, a plurality of chip bonding pad units are sequentially arranged in the same functional area, and the light-emitting chips are sequentially and adjacently arranged without vacant positions, so that the pixel packaging of small-space and irregular matrixes can be realized; the packaging size is reduced, the circuit arrangement is simplified, and the downstream mounting is facilitated.
Drawings
The technology of the present invention will be described in further detail with reference to the accompanying drawings and detailed description below:
FIG. 1 is a front view of an integrated packaged device of the present invention;
FIG. 2 is a cross-sectional view of an integrated packaged device of the present invention;
FIG. 3 is a schematic diagram of a top conductive layer, a die pad unit, on a first insulating layer;
FIG. 4 is a cross-sectional view taken along A-A of FIG. 3;
FIG. 5 is a cross-sectional view taken along line B-B of FIG. 3;
FIG. 6 is a schematic diagram of a chip-pad cell at E in FIG. 3;
FIG. 7 is a schematic view of an inner conductive layer on the front side of a substrate layer;
FIG. 8 is a cross-sectional view taken along line C-C of FIG. 7;
FIG. 9 is a schematic view of the second inner conductive layer on the back side of the base layer;
FIG. 10 is a cross-sectional view taken along line D-D of FIG. 9;
FIG. 11 is a schematic view of an underlying conductive layer on a second insulating layer;
FIG. 12 is a schematic diagram of the steps of the manufacturing method of the present invention.
Reference numerals:
1-a conductive layer; 11-top conductive layer; 111-a first edge pad; 112-a first graphics lead; 12-inner conductive layer; 121-first inner conductive layer; 122-inner conductive layer two; 1201-a second edge pad; 1202-a second graphics lead; 1203 — second connection pads; 13-a bottom conductive layer; 131-third edge pad;
2-isolating structural layer; 21-top layer isolation structure layer; 211-a solder mask; 22-middle layer isolation structure layer; 23-a bottom layer insulation structure layer; 231-a thermally conductive layer; 201-a substrate layer; 202-a first insulating layer; 203-a second insulating layer;
3-a chip pad unit; 31-positive electrode pad; 32-negative electrode pad;
41-a first via hole; 42-via two; 43-conducting hole three;
5-a communicating hole; 51-a first communication hole; 52-communicating hole two;
6-filling glue; 7-a box dam; 8-a light emitting chip; 9-a light conversion layer; 10-connecting glue layer.
Detailed Description
The conception, the specific structure and the technical effects of the present invention will be clearly and completely described in conjunction with the embodiments and the accompanying drawings to fully understand the objects, the schemes and the effects of the present invention. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The same reference numbers will be used throughout the drawings to refer to the same or like parts.
It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly fixed or connected to the other feature or indirectly fixed or connected to the other feature. Further, the description of the upper, lower, left, right, etc. used in the present invention is only with respect to the positional relationship of the respective components of the present invention with respect to each other in the drawings.
Example 1:
referring to fig. 2 to 11, a substrate for integrated package devices includes a patterned conductive layer 1, an insulating structure layer 2, and a chip pad unit 3.
Referring to fig. 4, 5, 8 and 10, the conductive layer 1 is provided with at least three layers and arranged in a stacked manner, i.e. the conductive layer 1 may be three or more layers. In this embodiment, the conductive layer 1 has 4 layers, which are a top conductive layer 11, a first inner conductive layer 121, a second inner conductive layer 122 and a bottom conductive layer 13 from top to bottom.
Referring to fig. 2, 4, 5, 8 and 10, the isolation structure layer 2 is provided with a plurality of layers, and is respectively inserted between two adjacent conductive layers 1 and is connected and fixed with the conductive layers 1, and as can be seen from the structure, the number of the isolation structure layer 2 is one less than that of the conductive layers 1, and if the number of the conductive layers 1 is N (N is a natural number greater than or equal to 3), the number of the isolation structure layer 2 is N-1. Specifically, the insulating structure layer 2 includes a substrate layer 201 and at least one insulating layer.
In this embodiment, referring to fig. 4, 5, 8 and 10, the conductive layer 1 has 4 layers, and the isolation structure layer 2 has 3 layers, which are a top layer isolation structure layer 21, a middle layer isolation structure layer 22 and a bottom layer isolation structure layer 23, respectively, where the middle layer isolation structure layer 22 is a substrate layer 201, and the top layer isolation structure layer 21 and the bottom layer isolation structure layer 23 are insulating layers, which are a first insulating layer 202 and a second insulating layer 203, respectively. The first inner conductive layer 121 and the second inner conductive layer 122 are respectively arranged on the upper surface and the lower surface of the base layer 201, the first insulating layer 202 and the second insulating layer 203 respectively cover the first inner conductive layer 121 and the second inner conductive layer 122 on the upper surface and the lower surface of the base layer 201, and the top conductive layer 11 is positioned on the first insulating layer 202.
Referring to fig. 3, the die pad unit 3 is used for connecting the light emitting chip 8, and the die pad unit 3 is provided with a plurality of die pad units and arranged in a matrix on the top insulating structure layer 2, that is, in the present embodiment, the matrix of the die pad units 3 is disposed on the first insulating layer 202.
Referring to fig. 3, each of the conductive layers 1 of the non-bottom layer corresponds to at least one row of the die pad units 3, and each row of the die pad units 3 corresponds to only one conductive layer 1. The chip pad units 3 are provided with a plurality of types and respectively correspond to the conductive layers 1, and the chip pad units 3 are all arranged on the isolation structure layer 2 on the top layer. As can be seen from this correspondence, the rows of the chip pad units 3 are divided into N-1 types, each corresponding to a non-underlying conductive layer 1, and each type has at least one row, which may be a plurality of rows. In the present embodiment, there are 4 conductive layers in total, and there are 3 conductive layers 1 on the non-bottom layer, and there are 3 types of rows of the corresponding chip pad units 3, and there are 2 rows of each type, and there are 6 rows in total.
Referring to fig. 4, 5, 8 and 10, the bottom conductive layer 13 and the non-bottom conductive layers 13 above the bottom conductive layer are respectively connected through via holes, that is, each non-bottom conductive layer 13 is connected to the bottom conductive layer 13, and it can be understood that, because the distance between each non-bottom conductive layer 13 and the bottom conductive layer 13 is different, the length of each via hole is different, and the structure of each via hole is different. In the embodiment, the via holes are the first via hole 41, the second via hole 42, and the third via hole 43, the top conductive layer 11 is connected to the bottom conductive layer 13 through the first via hole 41, the first inner conductive layer 121 is connected to the bottom conductive layer 13 through the second via hole 42, and the second inner conductive layer 122 is connected to the bottom conductive layer 13 through the third via hole 43, and correspondingly, the first via hole 41 penetrates through the top insulating structure layer 21, the middle insulating structure layer 22, and the bottom insulating structure layer 23, the second via hole 42 penetrates through the middle insulating structure layer 22 and the bottom insulating structure layer 23, and the third via hole 43 penetrates through the bottom insulating structure layer 23.
Referring to fig. 4, the top conductive layer 11 is connected to the corresponding chip pad unit 3; referring to fig. 5, 8 and 10, the non-top conductive layers 11 are connected to the corresponding chip pad units 3 through the communication holes 5, respectively. That is, each type of die pad unit 3 is connected to each non-underlying conductive layer 1, and each non-underlying conductive layer 1 is connected to the underlying conductive layer 13, so that each type of die pad unit 3 is connected to the underlying conductive layer 13. In the present embodiment, there are 4 conductive layers in total, and there are 3 conductive layers 1 on the non-bottom layer, and there are 3 types of rows of the corresponding chip pad units 3, and there are 2 rows of each type, and there are 6 rows in total. Wherein, the 1 st row and the 6 th row are correspondingly connected with the top conductive layer 11; the 2 nd row and the 5 th row are correspondingly connected with the first inner conducting layer 121; and the 3 rd row and the 4 th row are correspondingly connected with the second inner conducting layer 122.
Based on the above structure, in the substrate of the present invention, the conductive layer 1 is adopted to connect each chip pad unit 3 arranged on the top isolation structure layer 21 to the conductive layer 1 at the bottommost layer, so that power supply of each chip pad unit 3 can be realized without additionally welding an external lead, and when performing integrated packaging, the light emitting chip 8 can be welded with the chip pad unit 3 to supply power, and an external lead is also not needed, so that the distance between each chip pad unit 3 and the distance between the light emitting chips 8 can be set smaller and tighter, thereby realizing an integrated packaging device with higher pixels, and the size structure after packaging is smaller.
Specifically, referring to fig. 3 to 5, the top conductive layer 11 includes a plurality of first edge pads 111 and a plurality of first pattern leads 112, one end of each first pattern lead 112 is connected to the corresponding first edge pad 111, and the other end is connected to the corresponding die pad unit 3, and the first edge pads 111 are connected to the bottom conductive layer 13 through the via holes. With the above structure, the first edge pad 111 and the underlying conductive layer 13 are connected together. A plurality of die pad units 3 corresponding to the top conductive layer 11 are provided, and each die pad unit 3 is provided with a first edge pad 111 and a first pattern lead 112. In the present embodiment, the chips corresponding to the top conductive layer 11 are divided into 2 rows, which are the 1 st row and the 6 th row, each row has 7 chip pad units 3, and 14, and correspondingly, 14 first edge pads 111 are provided, and 14 first pattern leads 112 are also provided. Each of the first edge pads 111 is disposed at an outer edge of the top insulating structure layer 21.
Similarly, referring to fig. 7 to 10, the conductive layer 1 between the top conductive layer 11 and the bottom conductive layer 13 is an inner conductive layer, each of the inner conductive layers includes a plurality of second edge pads 1201, a plurality of second pattern leads 1202, and a plurality of second connection pads 1203, the second connection pads 1203 are connected to the second edge pads 1201 through the second pattern leads 1202, the second connection pads 1203 are connected to the corresponding chip pad units 3 through the communication holes 5, and the second edge pads 1201 are connected to the bottom conductive layer 13 through the via holes. The second edge bonding pad 1201 and the first edge bonding pad 111 are staggered up and down to cause short circuit due to mutual contact when the via hole penetrates through, and the second connection welding is opposite to the corresponding chip bonding pad unit 3 up and down so as to be conveniently connected with the via hole without additionally arranging a lead. That is, with the above configuration, the chip pad unit 3 corresponding to the inner conductive layer is connected to the underlying conductive layer 13.
In this embodiment, referring to fig. 7 and 8, the inner conductive layer has 2 layers, i.e., a first inner conductive layer 121 and a second inner conductive layer 122, and the via hole 5 is divided into a first via hole 51 and a second via hole 52. The chip pad units 3 in the 2 nd and 5 th rows are the same and correspond to the first inner conductive layer 121, so that the total number of the chip pad units 3 in the 2 nd and 5 th rows is 14, the number of the second connection pads 1203 of the first inner conductive layer 121, the number of the second pattern leads 1202 and the number of the second edge pads 1201 are 17, the second connection pads 1203 are connected with the corresponding chip pad units 3 through the first communication holes 51, and the second edge pads 1201 are connected with the bottom conductive layer 13 through the second communication holes 42.
Referring to fig. 9 and 10, the die pad units 3 in the 3 rd and 4 th rows are similar and correspond to the second inner conductive layer 122, so that the total number of the die pad units 3 in the 3 rd and 4 th rows is 14, the second connection pads 1203 of the second inner conductive layer 122, the second pattern leads 1202 and the second edge pads 1201 are 17, the second connection pads 1203 are connected to the corresponding die pad units 3 through the second via holes 52, and the second edge pads 1201 are connected to the bottom conductive layer 13 through the third via holes 43.
It will be appreciated that each conductive layer 1 is a patterned conductive layer 1, and thus each edge pad, pattern lead, is also a patterned structure, occupying less volume and space than an external lead, and is attached to the base layer 201, embedded in the insulating layer, or attached to the insulating layer.
Specifically, referring to fig. 4, 8, 10 and 11, the bottom conductive layer 13 includes a plurality of third edge pads 131, and the third edge pads 131 are connected to the first edge pads 111 or the second edge pads 1201 through the via holes; the third edge pad is opposite to the first edge pad 111 or the second edge pad 1201 connected to itself up and down. The bottom conductive layer 13 is connected with other conductive layers 1 through via holes, so that the top and bottom need to be aligned, and lead connection is avoided. In the present embodiment, since the number of the die pad units 3 is 42, the total number of the first edge pads 111 and the second edge pads 1201 is also 42, and thus the number of the third edge pads 131 is also 42.
In some embodiments, referring to fig. 3, the row of chip pad cells 3 corresponding to the top conductive layer 11 is located in the outermost row of the matrix. Because the top layer conducting layer 11 and the chip pad units 3 are both located on the top layer isolation structure layer 21 and are not connected by the via holes, the rows of the chip pad units 3 corresponding to the top layer conducting layer 11 are arranged on the outermost rows of the matrix and can be directly connected with the top layer conducting layer 11 on the outermost side, so that the interference of other chip pad units 3 on the connection of the top layer conducting layer and the chip pad units is avoided, and the distance between the chip pad units 3 is increased. In the present embodiment, even if the chip pad units 3 of the 1 st and 6 th rows correspond to the top conductive layer 11.
Preferably, referring to fig. 4 and 11, the substrate of the present invention further includes a solder resist layer 211 and a heat conductive layer 231; the solder mask layer 211 is arranged on the top insulating structure layer 2 and covers the top insulating structure layer 2 except for the top conductive layer 11 and the chip pad unit 3; the heat conducting layer 231 is disposed on the underlying insulating structure layer 2. The solder resist layer 211 is provided to avoid short circuit caused by subsequent soldering. The heat conductive layer 231 is a metal layer to quickly discharge heat generated during operation of the substrate, and the heat conductive layer 231 is a metal layer.
The material of the substrate layer 201 is a ceramic material including Al2O3Ceramics, AlN ceramics, Si3N4Ceramic or BeO ceramic. The conducting layer 1 is made of one or more of Cu, Ni, Pd, W, Ag and Au.
Specifically, referring to fig. 3 and 6, each of the die pad units 3 includes a positive pad 31 and a negative pad 32, the matrix is divided into a plurality of rectangular functional regions, in the same functional region, the plurality of die pad units 3 are sequentially arranged, and the positive pad 31 of one of the adjacent two die pad units 3 is connected to the negative pad 32 of the other one. In the same functional area, because of the positive electrode pad 31 of one of the two adjacent die pad units 3, the light-emitting units in the same area are connected in series after welding. Each of the light emitting chips 8 can be independently lighted or a functional region can be lighted together by connecting an external circuit for input through each edge pad. For example, in fig. 3, each row is a functional area, and each light emitting chip 8 of the row can be independently lighted or a functional area can be lighted together. It is also possible to divide several rows adjacent up and down into one functional area, and the positive electrode pad 31 or the negative electrode pad 32 at the end of each row is connected with the pad of the opposite electrode of the next row.
Example 2:
referring to fig. 1 to 11, an integrated package device includes the substrate according to embodiment 1, and further includes a plurality of light emitting chips 8, light conversion layers 9 corresponding to the light emitting chips 8 one to one, a connection glue layer 10, a filling glue 6, and a dam 7.
Referring to fig. 1 and 2, each of the light emitting chips 8 is connected to each of the die pad units 3, respectively; in the same functional region, each of the light emitting chips 8 is sequentially and adjacently arranged without a vacancy, so that the light emitting chips 8 in the functional region are connected in series. The edge bonding pads are connected with an external circuit for input, and each sending-to chip can be independently lightened or a functional area can be lightened together.
The light conversion layer 9 is fixed on the light emitting chip 8 through the connecting adhesive layer 10, and the dam 7 is fixed on the isolation structure layer 2 on the top layer and surrounds the matrix; the filling adhesive 6 fills the dam 7 and fills gaps among the light emitting chips 8, the light conversion layers 9 and the connection adhesive layer 10.
In the integrated packaging device, the substrate of embodiment 1 is adopted, the matrix of the chip pad unit 3 is divided into a plurality of rectangular functional areas, a plurality of chip pad units 3 are sequentially arranged in the same functional area, and each light-emitting chip 8 is sequentially and adjacently arranged without a vacancy, so that the pixel packaging of small-space and irregular matrixes can be realized; the packaging size is reduced, the circuit arrangement is simplified, and the downstream mounting is facilitated.
Example 3
Referring to fig. 1 to 12, a method for manufacturing an integrated package device using the substrate according to embodiment 1 includes the following steps:
s1, referring to fig. 12, a plurality of light emitting chips 8 are soldered to each of the die pad units 3, and in the same functional region, each of the light emitting chips 8 is sequentially and adjacently disposed without a vacant site;
s2, referring to fig. 12, the light conversion layers 9 are fixed to the light emitting chips 8 by the adhesive layer 10;
s3, referring to fig. 12, forming a dam 7 surrounding the matrix on the top insulating structure layer 2 by using a glue;
s4, referring to fig. 12, filling adhesive 6 is filled in the dam 7, and the filling adhesive 6 fills the dam 7 and fills the gaps between the light emitting chips 8, the light conversion layers 9, and the connection adhesive layer 10.
Wherein, the box dam 7, the connecting glue layer 10 and the filling glue 6 are all silica gel.
The manufacturing method of the invention adopts the substrate of the embodiment 1, and the light-emitting chip 8 is not required to be welded by an external lead in the manufacturing process, so that the operation is simpler, the distance between the light-emitting chips 8 is smaller, the pixel of the manufactured integrated packaging device is higher, and the size structure after packaging is smaller.
Other contents of the substrate, the integrated package device and the manufacturing method of the integrated package device described in the present invention refer to the prior art, and are not described herein again.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way, so that any modification, equivalent change and modification made to the above embodiment according to the technical spirit of the present invention are within the scope of the technical solution of the present invention.
Claims (10)
1. A substrate is used for integrated packaging of devices and is characterized by comprising a patterned conductive layer, an isolation structure layer and a chip pad unit;
the conducting layer is provided with at least three layers which are arranged in a laminated manner;
the isolation structure layer is provided with a plurality of layers, is respectively inserted between two adjacent conductive layers and is fixedly connected with the conductive layers, and comprises a base body layer and at least one insulating layer;
the chip bonding pad unit is used for connecting a light-emitting chip, is provided with a plurality of insulating structure layers on the top layer and is arranged in a matrix; each conducting layer of the non-bottom layer corresponds to at least one row of chip pad units respectively, and each row of chip pad units only corresponds to one conducting layer;
the chip pad units are provided with a plurality of types and respectively correspond to the conductive layers, and the chip pad units are arranged on the isolation structure layer on the top layer;
the bottom conducting layer is connected with each non-bottom conducting layer above the bottom conducting layer through a via hole respectively; the top conductive layer is connected with the corresponding chip bonding pad unit; the non-top conductive layers are respectively connected with the corresponding chip pad units through the communication holes.
2. The substrate of claim 1, wherein the top conductive layer comprises a plurality of first edge pads and a plurality of first pattern leads, one end of each first pattern lead is connected to the corresponding first edge pad, the other end of each first pattern lead is connected to the corresponding chip pad unit, and the first edge pads are connected to the bottom conductive layer through the via holes.
3. The substrate according to claim 2, wherein the conductive layers between the top conductive layer and the bottom conductive layer are inner conductive layers, each inner conductive layer comprises a plurality of second edge pads, a plurality of second pattern leads and a plurality of second connection pads, the second connection pads are connected with the second edge pads through the second pattern leads, the second connection pads are connected with the corresponding chip pad units through communication holes, and the second edge pads are connected with the bottom conductive layer through the via holes;
the positions of the second edge bonding pad and the first edge bonding pad are staggered up and down, and the second connecting welding is opposite to the corresponding chip bonding pad unit up and down.
4. The substrate of claim 3, wherein the bottom conductive layer comprises a plurality of third edge pads, the third edge pads being connected to the first edge pads or the second edge pads through the vias; the third edge pad is opposite to the first edge pad or the second edge pad connected to the third edge pad.
5. The substrate of claim 1, wherein a row of the chip-pad cells corresponding to the top conductive layer is located in an outermost row of the matrix.
6. The substrate of claim 1, further comprising a solder resist layer and a thermally conductive layer; the solder mask layer is arranged on the isolation structure layer of the top layer and covers the area of the isolation structure layer except the top layer conducting layer and the chip bonding pad unit; the heat conducting layer is arranged on the isolation structure layer of the bottom layer.
7. The substrate of claim 1 wherein said base layer is a ceramic material comprising Al2O3Ceramics, AlN ceramics, Si3N4Ceramic or BeO ceramic.
8. The substrate according to claim 1-7, wherein each of the die pad units comprises a positive pad and a negative pad, the matrix is divided into a plurality of rectangular functional areas, a plurality of the die pad units are sequentially arranged in the same functional area, and the positive pad of one of two adjacent die pad units is connected to the negative pad of the other one.
9. An integrated package device, comprising the substrate of claim 8, further comprising a plurality of light emitting chips, light conversion layers corresponding to the light emitting chips one to one, connection glue layers, filling glue and dam bars;
each light-emitting chip is connected with each chip bonding pad unit respectively; in the same functional region, all the light-emitting chips are sequentially and adjacently arranged without vacant positions;
the light conversion layer is fixed on the light emitting chip through the connecting adhesive layer, and the dam is fixed on the isolation structure layer on the top layer and surrounds the matrix; the filling glue is filled in the dam and filled in gaps among the light-emitting chips, the light conversion layers and the connecting glue layers.
10. A method of manufacturing an integrated package device, using the substrate of claim 8, comprising the steps of:
s1, welding a plurality of light-emitting chips with the chip pad units, wherein in the same functional region, the light-emitting chips are sequentially and adjacently arranged without vacant positions;
s2, fixing the light conversion layers on the light emitting chips respectively through the connecting glue layer;
s3, forming a box dam surrounding the matrix on the isolation structure layer on the top layer by using colloid;
and S4, filling glue in the dam, so that the filling glue is filled in the dam and is filled in gaps among the light-emitting chips, the light conversion layers and the connecting glue layers.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116111033A (en) * | 2023-03-03 | 2023-05-12 | 佛山市国星半导体技术有限公司 | LED car light source and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116111033A (en) * | 2023-03-03 | 2023-05-12 | 佛山市国星半导体技术有限公司 | LED car light source and manufacturing method thereof |
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