CN114361112A

CN114361112A - Method for manufacturing semiconductor structure

Info

Publication number: CN114361112A
Application number: CN202210036749.6A
Authority: CN
Inventors: 锁浩; 纪刚; 巩金峰
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-01-13
Filing date: 2022-01-13
Publication date: 2022-04-15

Abstract

The present disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a plurality of adjacent bit line structures with contact holes formed between the adjacent bit line structures; forming an initial contact layer in the contact hole, wherein the initial contact layer comprises a gap; etching the initial contact layer, and removing part of the initial contact layer to form a first contact layer; etching the first contact layer to remove part of the gap, and forming a second contact layer by the reserved first contact layer; and etching the second contact layer, wherein the etching rate of the side wall of the concave shape is greater than that of the bottom of the concave shape, so as to remove the residual gap and form a third contact layer. According to the method, the initial contact layer is etched for multiple times, the etching speed of the side position of the second contact layer is controlled to be higher than the etching speed of the middle position of the second contact layer, so that the contact layer with the flattened top appearance is formed, and the yield and the conductivity of the semiconductor structure are improved.

Description

Method for manufacturing semiconductor structure

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor structure.

Background

With the continuous development of Dynamic Random Access Memory (DRAM) process technology, the spacing between adjacent bit line structures is getting smaller and smaller. As the distance between adjacent bit line structures becomes smaller, the difficulty in manufacturing the contact hole formed between the bit line structures becomes greater and greater, and particularly when a contact hole with a high aspect ratio is formed, a gap exists in the contact hole filled with a material for forming a contact layer, and the top morphology of the contact layer in the contact hole is difficult to control, so that the conductivity and yield of the semiconductor structure are reduced.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The present disclosure provides a method of fabricating a semiconductor structure.

The embodiment of the disclosure provides a manufacturing method of a semiconductor structure, which comprises the following steps:

providing a substrate, wherein the substrate comprises a plurality of mutually-separated bit line structures, and contact holes are formed between adjacent bit line structures;

forming an initial contact layer in the contact hole, wherein the initial contact layer fills the contact hole and extends out of the contact hole, and the top surface of the initial contact layer is higher than the top surface of the bit line structure, wherein a gap is included in the initial contact layer, and the top surface of the gap is lower than the top surface of the bit line structure;

etching the initial contact layer to remove part of the initial contact layer, exposing the top surface of the bit line structure, and forming a first contact layer by the retained initial contact layer;

etching the first contact layer to remove part of the gap, wherein the remained first contact layer forms a second contact layer, and the top of the second contact layer is concave;

and etching the second contact layer, wherein the etching rate of the side wall of the concave shape is greater than that of the bottom of the concave shape, so as to remove the residual gap and form a third contact layer.

According to some embodiments of the present disclosure, the etching the first contact layer to remove a portion of the gap includes:

and carrying out first over-etching treatment on the first contact layer for a first time length so as to remove part of the gap.

According to some embodiments of the present disclosure, the performing the first over-etching process on the first contact layer for the first duration includes:

and etching the first contact layer by using a first etching gas with a high selection ratio under the conditions that the source power is 300-500W, the bias power is 50-80W and the pressure is 5-20 mTorr.

According to some embodiments of the present disclosure, the etching the second contact layer, wherein the etching rate of the sidewall of the recess shape is greater than the etching rate of the bottom of the recess shape, so as to remove the remaining gap and form a third contact layer, includes:

and performing second over-etching treatment on the top of the second contact layer for a second time, wherein in the second over-etching treatment, the etching rate of the side wall of the concave shape is greater than that of the bottom of the concave shape, so as to remove part of the second contact layer, and the remained second contact layer forms the third contact layer.

According to some embodiments of the disclosure, the second length of time comprises a first period of time; and performing second over-etching treatment on the top of the second contact layer for a second time period, wherein the second over-etching treatment comprises the following steps:

and carrying out second over-etching treatment on the top of the second contact layer for a first period of time to remove part of the second contact layer and form a first recess with a first appearance on the top of the second contact layer which is remained.

According to some embodiments of the disclosure, the second time period comprises a second time period, wherein the second time period has a duration greater than the duration of the first time period;

and performing second over-etching treatment on the top of the second contact layer for a second time period, wherein the second over-etching treatment comprises the following steps:

performing second over-etching treatment on the top of the second contact layer for a second time period to remove part of the second contact layer and form a second recess with a second appearance on the top of the second contact layer which is remained;

wherein, in the first direction, a difference between a top of the second recess and a bottom thereof is smaller than a difference between a top of the first recess and a bottom thereof.

According to some embodiments of the present disclosure, the performing a second over-etching process on the top of the second contact layer for a second duration includes:

determining a second duration;

and etching the second contact layer by using the second over-etching treatment within the second time length.

According to some embodiments of the disclosure, the determining the second duration comprises:

and determining the second time length according to the proportional range relation between the first time length and the second time length.

According to some embodiments of the present disclosure, the determining the second duration according to the proportional range relationship between the first duration and the second duration includes:

determining that the ratio range of the first duration to the second duration is 1: (0 to 0.33);

determining a topography of the first or second depression;

and determining the second time length according to the proportion range and the appearance of the first recess or the second recess.

According to some embodiments of the disclosure, etching the second contact layer with the second over-etching process within the second duration includes:

and etching the second contact layer by using a second etching gas under the conditions that the source power is 400-600W, the bias power is 50-80W and the pressure is 5-10 mTorr.

According to some embodiments of the present disclosure, the etching the initial contact layer to remove a portion of the initial contact layer to expose a top surface of the bit line structure, the remaining initial contact layer forming a first contact layer, includes:

and etching the initial contact layer by using a first etching gas under the conditions that the source power is 300-500W, the bias power is 50-80W and the pressure is 5-20 mTorr.

According to some embodiments of the present disclosure, the etching the initial contact layer using a first etching gas includes:

and etching the initial contact layer by using a first etching gas with a high selection ratio, and taking the top surface of the bit line structure as an etching end point.

According to some embodiments of the present disclosure, the providing a substrate including a plurality of bit line structures separated from each other on the substrate, a contact hole being formed between adjacent bit line structures includes:

forming a plurality of bit lines arranged at intervals on the substrate, wherein a first groove is formed between every two adjacent bit lines;

forming an insulating layer in the first groove, wherein the insulating layer extends out of the first groove and covers the top surface of the bit line;

removing the insulating layer at the bottom of the first trench, wherein the insulating layer remained in the first trench forms the contact hole;

wherein the bit line and the insulating layer formed on the sidewalls and the top surface of the bit line constitute the bit line structure.

According to some embodiments of the present disclosure, the forming a plurality of bit lines arranged at intervals on the substrate, adjacent bit lines constituting a first trench therebetween, includes:

sequentially forming a bit line contact layer, a first dielectric layer, a conductive layer and a second dielectric layer which are arranged in a stacked mode on the substrate;

forming a mask layer with a mask pattern on the second dielectric layer, and removing part of the second dielectric layer, part of the conductive layer, part of the first dielectric layer and part of the bit line contact layer according to the mask pattern, wherein the reserved bit line contact layer, the first dielectric layer, the conductive layer and the second dielectric layer form a plurality of bit lines;

along a second direction, a plurality of the bit lines form a plurality of the first trenches arranged at intervals.

According to some embodiments of the present disclosure, the forming an insulating layer in the first trench, the insulating layer extending to outside the first trench and covering on a top surface of the bit line structure, includes:

and forming the insulating layer in the first groove by utilizing an atomic layer deposition process.

In the manufacturing method of the semiconductor structure provided by the embodiment of the disclosure, the initial contact layer in the contact hole is etched for multiple times, so that the gap is removed for multiple times, and meanwhile, the etching speed of the side position of the second contact layer is controlled to be higher than the etching speed of the middle position of the second contact layer, so that the contact layers with different top appearances are formed; when the top of the formed contact layer is in a U-shaped shape, the resistance of a subsequently formed contact structure can be reduced, so that the conductivity of the semiconductor structure is improved; when the top of the formed contact layer is in a flattened shape, the depth-to-width ratio of the contact hole is effectively reduced, so that gaps are not formed when other structures are formed subsequently, and the yield and the conductivity of the semiconductor structure are improved.

Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. For a person skilled in the art, other figures can be derived from these figures without inventive effort.

FIG. 1 is a flow chart illustrating a method of fabricating a semiconductor structure according to an exemplary embodiment.

FIG. 2 is a schematic diagram illustrating the formation of bit lines in a method of fabricating a semiconductor structure according to an example embodiment.

Fig. 3 is a schematic diagram illustrating a method of forming a bitline structure in a method of fabricating a semiconductor structure according to an example embodiment.

FIG. 4 is a schematic diagram illustrating the formation of an initial contact layer in a method of fabricating a semiconductor structure according to an example embodiment.

Fig. 5 is a schematic diagram illustrating the formation of a first contact layer in a method of fabricating a semiconductor structure according to an example embodiment.

Fig. 6 is a schematic diagram illustrating the formation of a second contact layer in a method of fabricating a semiconductor structure according to an example embodiment.

Fig. 7 is a schematic diagram illustrating formation of a third contact layer in a method of fabricating a semiconductor structure according to an example embodiment.

FIG. 8 is a schematic diagram illustrating a method of forming a third contact layer having a first recess topography in accordance with one exemplary embodiment.

FIG. 9 is a schematic diagram illustrating a method of fabricating a semiconductor structure in which a third contact layer having a second recessed topography is formed, according to an example embodiment.

Reference numerals:

10. a substrate; 20. a bit line structure;

30. a contact hole; 40. a bit line;

50. a first trench; 60. an insulating layer;

70. an initial insulating layer; 80. a gap;

90. a first contact layer; 100. a second contact layer;

110. a concave shape; 120. a third contact layer;

130. a first recess; 140. a second recess;

410. a bit line contact layer; 420. a first dielectric layer;

430. a conductive layer; 440. a second dielectric layer;

710. a first groove; 910. a second groove.

X, a first direction; y, second direction.

Detailed Description

To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

In an exemplary embodiment of the present disclosure, a flow chart of a method for fabricating a semiconductor structure is provided as shown in fig. 1, and the method for fabricating a semiconductor structure is described below with reference to fig. 1-9.

The semiconductor structure is not limited in this embodiment, and the semiconductor structure is a Dynamic Random Access Memory (DRAM) as an example, but the present embodiment is not limited thereto, and the semiconductor structure in the present embodiment may be other structures.

As shown in fig. 1, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including the following steps:

step S100: a substrate is provided, the substrate comprises a plurality of bit line structures which are separated from each other, and contact holes are formed between adjacent bit line structures.

Step S200: and forming an initial contact layer in the contact hole, wherein the initial contact layer fills the contact hole and extends out of the contact hole, and the top surface of the initial contact layer is higher than that of the bit line structure, a gap is formed in the initial contact layer, and the top surface of the gap is lower than that of the bit line structure.

Step S300: and etching the initial contact layer to remove part of the initial contact layer, exposing the top surface of the bit line structure, and forming a first contact layer by the remained initial contact layer.

Step S400: and etching the first contact layer to remove part of the gap, wherein the remained first contact layer forms a second contact layer, and the top of the second contact layer is concave.

Step S500: and etching the second contact layer, wherein the etching rate of the side wall of the concave shape is greater than that of the bottom of the concave shape, so as to remove the residual gap and form a third contact layer.

Exemplarily, as shown in fig. 1 to 3, in step S100, a substrate 10 is provided. The substrate 10 may be made of a semiconductor material, which may be one or more of silicon, germanium, a silicon germanium compound, and a silicon carbon compound. It is noted that, in some embodiments, the substrate 10 may further include a buried word line, a shallow trench isolation structure, an active region, and the like.

The substrate 10 includes a plurality of bit line structures 20 separated from each other, and contact holes 30 are formed between adjacent bit line structures 20.

In some embodiments, a plurality of mutually separated bit line structures 20 are formed on the substrate 10, and the following method may be adopted:

a plurality of bit lines 40 are formed on a substrate 10 at intervals, wherein first trenches 50 are formed between adjacent bit lines 40.

In some embodiments, first, the bit line contact layer 410, the first dielectric layer 420, the conductive layer 430, and the second dielectric layer 440 may be sequentially formed on the substrate 10 by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process. Then, a mask layer having a mask pattern is formed on the second dielectric layer 440, and a direction from the top surface of the substrate 10 to the bottom surface of the substrate 10 is taken as an extending direction, and along the extending direction, a portion of the second dielectric layer 440, a portion of the conductive layer 430, a portion of the first dielectric layer 420, and a portion of the bit line contact layer 410 are sequentially removed according to the mask pattern. The remaining bit line contact layer 410, first dielectric layer 420, conductive layer 430, and second dielectric layer 440 form a plurality of bit lines 40. At this time, a plurality of first trenches 50 are formed in the plurality of bit lines 40 at intervals along a second direction Y, which is a direction extending along the longitudinal direction of the substrate 10 as shown in fig. 2.

Note that the material of the bit line contact layer 410 includes tungsten or polysilicon. The materials of the first dielectric layer 420 and the second dielectric layer 440 may be the same or different, wherein the materials of the first dielectric layer 420 and the second dielectric layer 440 include silicon nitride, silicon dioxide, silicon oxynitride, or the like. The conductive layer 430 may be made of a conductive material or conductive materials, such as doped polysilicon, titanium nitride, and tungsten compounds.

After the first trench 50 is formed, an insulating layer 60 may be formed within the first trench 50 using an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process. In one example, the insulating layer 60 can be formed using an atomic layer deposition process, which has the characteristics of slow deposition rate, high compactness of the deposited film, and good step coverage. The insulating layer 60 formed by the atomic layer deposition process can effectively protect the bit line 40 from being isolated under a condition of a small thickness, so as to avoid occupying a large space in the first trench 50, and facilitate subsequent filling or formation of other structural layers.

Wherein the insulating layer 60 extends to the outside of the first trench 50 and covers the top surface of the bit line 40. The insulating layer 60 serves to protect and isolate the adjacent bit lines 40. The material of the insulating layer 60 includes silicon nitride or silicon oxynitride.

After the insulating layer 60 is formed, the insulating layer 60 at the bottom of the first trench 50 may be removed by an etching process. At this time, the contact hole 30 is formed between the adjacent insulating layers 60 remaining in the first trench 50 and located on the sidewalls of the bit line 40. The bit line 40 and the insulating layer 60 formed on the sidewall and the top surface of the bit line 40 form the bit line structure 20, that is, the contact hole 30 is formed between two adjacent bit line structures 20.

The bit line forming method in the present embodiment is simple and easy to operate. The bit line can be connected with a drain electrode in a transistor formed subsequently, a grid electrode of the transistor is connected with a word line, a source electrode of the transistor is connected with the capacitor structure, a voltage signal on the word line can control the transistor to be turned on or turned off, and then data information stored in the capacitor structure is read through the bit line or written into the capacitor structure through the bit line for storage.

Illustratively, as shown in fig. 4, in step S200, the initial contact layer 70 may be formed within the contact hole 30 by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process. The initial contact layer 70 may be a silicon material layer having a doping element, the material of the silicon material layer includes monocrystalline silicon, polycrystalline silicon, amorphous silicon, or the like, and the doping element includes boron element, phosphorus element, or the like. In some embodiments, the initial contact layer 70 may also be a heavily doped layer for reducing the contact resistance between the doped layer and the substrate 10.

The initial contact layer 70 fills the contact hole 30 and extends out of the contact hole 30, and the top surface of the initial contact layer 70 is higher than the top surface of the bit line structure 20. In the case that the height of the bit line structures 20 is not changed in a direction perpendicular to the top surface of the substrate 10 due to the continuous shrinkage of the process, the distance between adjacent bit line structures 20 tends to become smaller, which may result in an increase in the aspect ratio of the contact hole 30, for example, when the aspect ratio of the contact hole 30 is greater than 6:1, and when the initial contact layer 70 is deposited in the contact hole 30, the initial contact layer 70 may be sealed in advance at the top of the contact hole 30, so that the gap 80 may occur in the formed initial contact layer 70, and the top surface of the gap 80 may be lower than the top surface of the bit line structure 20. Meanwhile, a first recess 710 is formed on the top of the initial contact layer 70 at a position aligned with each contact hole 30. In the process of manufacturing the semiconductor structure, the gap 80 in the contact hole 30 and the first recess 710 on the top of the initial contact layer 70 are not favorable for improving the conductivity of the semiconductor structure, so that the gap 80 and the first recess 710 can be removed in the subsequent process.

It should be noted that, since the top of the initial contact layer 70 is formed higher than the top of the bit line structure 20, the thickness of the initial contact layer 70 is larger along the first direction X, i.e., along the direction perpendicular to the top surface of the substrate 10. Therefore, the formation of the initial contact layer 70 by the chemical vapor deposition process with a faster deposition rate is advantageous for shortening the process cycle of the semiconductor structure.

Illustratively, as shown in fig. 4 and 5, in step S300, the initial contact layer 70 is etched to remove a portion of the initial contact layer 70 and the first recess 710 and expose the top surface of the bit line structure 20, and at this time, the remaining initial contact layer 70 forms the first contact layer 90.

The initial contact layer 70 may be removed by the following method:

the initial contact layer 70 is etched by using a first etching gas under the conditions of a source power of 300-500W, a bias power of 50-80W and a pressure of 5-20 mTorr. Wherein, in some embodiments, the first etching gas may include a high selectivity ratio of chlorine, hydrobromic acid, and the like. By using the first etching gas with high selectivity ratio, part of the initial contact layer 70 can be removed quickly, which is beneficial to saving the period of the process of the semiconductor structure and improving the etching precision and the yield of the subsequent process. In the present embodiment, the etching of a portion of the initial contact layer 70 is a main etching step, and in this step, the etching end point of the initial contact layer 70 may be stopped on the top surface of the bit line structure 20 by an etching end point detection technique. It should be noted that, in the main etching step, as the etching end point is on the top surface of the bit line structure 20, the remained initial contact layer 70 in the contact hole 30 forms the first contact layer 90, and the second recess 910 may be formed on the top surface of the first contact layer 90. Wherein the bottom of the second groove 910 is close to the top of the gap 80, and two sides of the second groove 910 are flush with the top surface of the insulating layer 60 adjacent thereto, in some embodiments, the longitudinal cross-sectional shape of the second groove 910 may include a semi-circle or a semi-ellipse, so as to facilitate subsequent selective etching of the first contact layer 90, thereby increasing the etching rate.

Illustratively, as shown in fig. 6, in step S400, the first contact layer 90 is etched to remove a portion of the gap 80, and the remaining first contact layer 90 forms the second contact layer 100. In this step, the portions of the slits 80 that are not removed may cause the top of the second contact layer 100 to be recessed 110 due to the removal of portions of the slits 80. It should be noted that, in some steps, the entire gap 80 in the contact hole 30 may be removed by etching the first contact layer 90.

Note that, as shown in fig. 6, when a part of the slit 80 is removed, the top of the slit 80 is opened so that the lower half of the slit 80 is exposed. In one of the processes, a contact material may be directly filled in the lower half of the gap 80 to form a filling layer, etc., but in this process, since only the upper half of the gap 80 is removed during the etching process of the gap 80, the lower half of the gap 80 still has a high aspect ratio, and therefore, other gaps may be formed again inside the filling layer formed in the gap 80, resulting in a reduction in the performance of the semiconductor structure.

Therefore, in the present embodiment, the entire gap 80 can be removed multiple times in the subsequent process steps, thereby improving the performance and yield of the semiconductor structure.

Wherein, in some embodiments, the following method may be adopted for the first removal of the slit 80:

a portion of the gap 80 is removed by performing a first over-etch process for a first duration on the first contact layer 90. The etching process of the first over-etching treatment comprises the following steps: the first contact layer 90 is etched by using a first etching gas with a high selectivity ratio under the conditions of a source power of 300-500W, a bias power of 50-80W and a pressure of 5-20 mTorr.

In some embodiments, the first etching gas can be, for example, hydrobromic acid (HBr), chlorine (Cl), or combinations thereof₂) And etching the first contact layer 90 for a first time under the etching conditions of the isotropic gas with the source power of 300-500W, the bias power of 50-80W and the pressure of 5-20 mTorr to quickly and uniformly consume the filling materials in the first contact layer, such as monocrystalline silicon, polycrystalline silicon or amorphous silicon, and eliminate the reserved gap 80, so that the conductivity of a subsequent semiconductor structure is effectively improved, and the yield of the semiconductor structure is improved.

For example, as shown in fig. 7 to 9, in step S500, the second contact layer 100 is etched, and in the etching step, the second over-etching process may be performed on the top of the second contact layer 100 for a second time period. In the second over-etching process, the etching rate of the sidewalls of the two sides of the recess 110 is greater than the etching rate of the bottom of the recess 110 along the first direction X, i.e., along the direction perpendicular to the top surface of the substrate 10, so as to remove a portion of the second contact layer 100 and the remaining gap 80, and the remaining second contact layer 100 forms the third contact layer 120. The etching rate of the second contact layer 100 is increased by etching the recess 110 at different positions with different etching rates, so that the top of the third contact layer 120 forms a top profile with different shapes, such as a deep V-shaped top profile, a U-shaped top profile or a planar top profile, for forming other structures later. In some embodiments, since the top of the second contact layer 100 is the recess 110 and a part of the gap 80 still exists in the second contact layer 100, if the etching rate of the bottom of the recess 110 is greater than that of the sidewall, the gap 80 still exists in the second contact layer 100, that is, when the second contact layer 100 is etched, only a part of the gap 80 can be removed, and the gap 80 cannot be completely removed.

Therefore, in the above embodiment, by controlling the etching time with different durations, the whole gap 80 is removed for multiple times, and different etching processes are used, so that the third contact layer 120 with a relatively flat top topography can be obtained, the aspect ratio of the contact hole is effectively reduced, and the gap is not formed when other structures are formed subsequently.

In some embodiments, the etching process of the second over-etching treatment is: under the conditions of source power of 400-600W, bias power of 50-80W and pressure of 5-10 mTorr, the second etching gas is used to etch the second contact layer 100. The second etching gas comprises inert gas Ar and anisotropic gas sulfur hexafluoride SF₆In this embodiment, the flow rate of the inert gas Ar is 100-₆The amount of the catalyst is 15-30 sccm. By setting the etching condition of the second over-etching treatment, the second contact layer 100 is etched within the second time period, so that the etching rate can be increased, the etching precision can be ensured, and the yield of subsequent processes can be increased.

It should be noted that, referring to fig. 7, in some embodiments, after the second over-etching process is performed on the second contact layer 100 for a predetermined time, the top profile of the second contact layer 100 may form a deep V-shaped top profile as shown in fig. 7, and then, after the second over-etching process is performed on the second contact layer 100, the top profile of the second contact layer 100 may be changed from the deep V-shaped top profile to a U-shaped or flat top profile. The second duration over-etching process for different periods of time is described as an example.

Referring to FIG. 7, in some embodiments, the second length of time comprises the first period of time. In the second over-etching process for the second duration performed on the top of the second contact layer 100, the etching process of the second over-etching process is used to perform the etching process for the first duration on the second contact layer 100, so as to remove a portion of the second contact layer 100, and at this time, the first recess 130 having the first profile is formed on the top of the second contact layer 100 that is remained. Note that, along the first direction X, the longitudinal sectional shape of the first recess 130 includes a deep V-shape.

In other embodiments, referring to fig. 8 and 9, the second time period comprises a second time period, wherein the second time period has a duration greater than the duration of the first time period. In the second over-etching process for the second time duration performed on the top of the second contact layer 100, the etching process of the second over-etching process is used to perform the etching process for the second time duration on the second contact layer 100, so as to continuously remove a part of the second contact layer 100. At this time, the remaining top of the second contact layer 100 forms the second recess 140 having the second profile along the first direction X, and a difference between the top of the second recess 140 and the bottom thereof is smaller than a difference between the top of the first recess 130 and the bottom thereof. Wherein a plane perpendicular to the first direction X is taken as a cross section, a cross-sectional shape of a top surface of the second recess 140 may include a U-shape or a planar shape.

It should be noted that after the second over-etching process is performed on the second contact layer 100 for the second time period, the etched second contact layer 100 is changed from the top profile of the deep V shape to the top profile of the U shape. Then, the etching of the second contact layer 100 is continued, and at this time, the top profile of the U-shape is continuously transformed into the top profile of the planar shape. Therefore, by controlling the duration of the second time period, the top profile of the third contact layer 120 can be formed into a relatively flat profile, thereby facilitating the subsequent formation of other structures of the semiconductor structure.

In this embodiment, the second contact layer 100 is subjected to the second over-etching treatment in the first time period or the second over-etching treatment in the second time period, so that the duration of the second time period is limited to be greater than the duration of the first time period, and the shape of the top of the third contact layer 120 is accurately controlled according to the setting of the etching rate in the second over-etching treatment, thereby effectively improving the yield of the subsequent semiconductor structure.

Referring to fig. 8 and 9, in some embodiments, for a second contact layer 100, during a second over-etching process for a second time period, the second time period may be determined first, so that the second contact layer 100 is etched by the second over-etching process during the second time period.

The second duration may be determined by the following method:

determining the proportion range of the first time length and the second time length as 1: (0 to 0.33).

The topography of the first recesses 130 or the second recesses 140 is determined.

And determining the second time length according to the proportion range and the appearance of the first recess or the appearance of the second recess.

For example, in one embodiment, it is desirable to form the third contact layer 120 with a top profile having a U-shaped cross section in the contact hole 30 on the substrate 10, and according to the proportional relationship, when the ratio of the second duration to the first duration is 1:9, the third contact layer 120 with a top profile having a U-shaped longitudinal cross section can be obtained, so as to determine the second duration according to the first duration. Therefore, in a second time period, the second contact layer 100 is subjected to a second over-etching process, and then a portion of the second contact layer 100 is removed, at this time, the remaining top of the second contact layer 100 forms a first recess 130 with a first profile. Wherein the remaining second contact layer 100 forms the third contact layer 120. In this embodiment, the second time period includes the first time period.

In another embodiment, it is desirable to form the third contact layer 120 having the top profile with the planar profile in the contact hole 30 on the substrate 10, and according to the proportional relationship, when the ratio of the second duration to the first duration is 1:3, the third contact layer 120 having the top profile with the planar profile can be obtained, so as to determine the second duration according to the first duration. Thus, in a second period of time, the second contact layer 100 is subjected to a second over-etching process, and then a portion of the second contact layer 100 is removed, at which time, the remaining top of the second contact layer 100 forms a second recess 140 with a second topography. Wherein the remaining second contact layer 100 forms the third contact layer 120. Wherein, in the present embodiment, the second duration includes the second time period.

In still another embodiment, when the ratio between the first duration and the second duration is 1:0, the processing for the second duration may not be required, and only the processing for the first duration may be required.

In the above embodiment, the first contact layer 90 is subjected to two over-etching steps, so as to precisely control the top profile of the third contact layer 120 in the contact hole 30, thereby improving the yield of the subsequent semiconductor structure and improving the conductivity of the semiconductor structure.

Wherein, in the step of performing the first over-etching treatment, hydrobromic acid (HBr) and chlorine (Cl) are selected₂) When the isotropic gas is used to rapidly remove a portion of the first contact layer 90, the remaining first contact layer 90 forms the second contact layer 100, and the top profile of the second contact layer 100 may have a V-shaped longitudinal cross-section.

Then under the etching condition of the second over-etching treatment, a second etching gas such as inert gas Ar and anisotropic gas sulfur hexafluoride SF are used₆The second contact layer is etched to rapidly remove a portion of the second contact layer 100, and the remaining second contact layer 100 forms a third contact layer 120. Referring to fig. 7 to 9, the vertical cross-sectional shape of the top profile of the third contact layer 120 may increase according to the second duration such that the vertical cross-sectional shape of the top profile of the third contact layer 120 transitions from a V-shaped profile to a U-shaped profile until transitioning to a flattened planar profile. It should be noted that, with the increase of the second duration, a plurality of bottom features of the contact hole 30, that is, top features of the third contact layer 120 in the contact hole 30, can be obtained, and the yield of the semiconductor structure can be effectively improved while the gap 80 is removed to improve the conductivity of the semiconductor structure. It should be noted that, when the top of the third contact layer 120 has a U-shaped profile or a V-shaped profile, the area of the third contact layer 120 and the subsequent storage node contact structure can be reduced, so that the contact resistance can be reduced. Meanwhile, the third contact layer is formed by etching the initial contact layer for many times, and the influence of the etching process on the bit line structure can be prevented.

The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

In the description herein, references to the terms "embodiment," "exemplary embodiment," "some embodiments," "illustrative embodiments," "example" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing and simplifying the present disclosure, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present disclosure.

It will be understood that the terms "first," "second," and the like as used in this disclosure may be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

Like elements in one or more of the drawings are referred to by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Numerous specific details of the present disclosure, such as structure, materials, dimensions, processing techniques and techniques of the devices, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; while the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims

1. A method for fabricating a semiconductor structure, the method comprising:

2. The method for fabricating the semiconductor structure according to claim 1, wherein the etching the first contact layer to remove a portion of the gap comprises:

3. The method for fabricating the semiconductor structure according to claim 2, wherein the performing the first over-etching process on the first contact layer for the first duration comprises:

4. The method for manufacturing a semiconductor structure according to claim 2, wherein the etching the second contact layer at a rate greater than that of the sidewall of the recess than that of the bottom of the recess to remove the remaining gap and form a third contact layer comprises:

5. The method of claim 4, wherein the second duration comprises a first time period;

6. The method of claim 5, wherein the second time period comprises a second time period, wherein the second time period has a duration greater than the duration of the first time period;

7. The method for fabricating the semiconductor structure according to claim 6, wherein the performing the second over-etching process on the top of the second contact layer for the second duration comprises:

determining a second duration;

8. The method of claim 7, wherein said determining a second duration comprises:

9. The method as claimed in claim 8, wherein said determining the second duration according to the proportional range relationship between the first duration and the second duration comprises:

determining a topography of the first or second depression;

10. The method of claim 7, wherein etching the second contact layer with the second over-etch process for the second duration comprises:

11. The method as claimed in any one of claims 1 to 10, wherein the etching the initial contact layer to remove a portion of the initial contact layer to expose a top surface of the bit line structure, the remaining initial contact layer forming a first contact layer comprises:

12. The method of claim 11, wherein etching the initial contact layer with a first etching gas comprises:

13. The method of claim 1, wherein the providing a substrate including a plurality of bit line structures separated from each other on the substrate, and forming contact holes between adjacent bit line structures comprises:

14. The method as claimed in claim 13, wherein forming a plurality of bit lines on the substrate at intervals, a first trench being formed between adjacent bit lines, comprises:

15. The method as claimed in claim 13, wherein forming an insulating layer in the first trench, the insulating layer extending outside the first trench and covering a top surface of the bit line structure comprises: