CN114356681A - Fault processing method and device in chip verification process and electronic equipment - Google Patents

Abstract

The application provides a fault processing method and device in a chip verification process and electronic equipment, and the method comprises the following steps: fault identification is carried out in the chip verification process, and fault information of the fault is obtained in response to the fault identification; determining a target fault debugging strategy matched with the fault information; executing a target fault debugging strategy, and performing fault debugging on the fault; and responding to the end of the fault debugging, and continuing the chip verification process from the fault position point. In the method and the device, the fault debugging in the chip verification process is realized, the modification of the source code corresponding to the chip verification and the re-simulation of the modified source code are avoided, the fault repairing time in the chip verification process is effectively shortened, and the chip verification efficiency is further improved.

Description

Fault processing method and device in chip verification process and electronic equipment

Technical Field

The present disclosure relates to the field of chip verification, and in particular, to a method and an apparatus for processing a fault in a chip verification process, and an electronic device.

Background

With the development of society, the verification of chips is increasingly important. Along with the increase of the complexity of chip design, the verification time of each module of the chip is increased, so that the repair time of faults in the chip verification process is increased, and the chip verification efficiency is influenced.

Therefore, how to improve the efficiency of chip verification becomes a problem to be solved at present.

Disclosure of Invention

The object of the present application is to solve at least to some extent one of the technical problems in the above-mentioned technology.

A first aspect of the present application provides a method for handling a fault in a chip verification process, including: fault identification is carried out in the chip verification process, and fault information of the fault is obtained in response to the fault identification; determining a target fault debugging strategy matched with the fault information; executing the target fault debugging strategy, and performing fault debugging on the fault; and responding to the end of fault debugging, and continuing the chip verification process from the position point of the fault.

The method for processing the fault in the chip verification process provided by the first aspect of the present application further has the following technical features, including:

according to an embodiment of the present application, the determining a target fault debugging policy that matches the fault information includes: determining a fault object and a corresponding fault type in the chip verification process from the fault information; and determining the target fault debugging strategy according to the fault object and the fault type.

According to an embodiment of the present application, the determining the target fault debugging policy according to the fault object and the fault type includes: responding to the fault type as the configuration fault of the fault object in the chip verification process, modifying the configuration parameters of the fault object, and using the configuration parameters as the target fault debugging strategy; responding to the fault type as the operation fault of the fault object in the chip verification process, calling a matched debugging test sequence, debugging the operation fault of the fault object according to the operation result of the debugging test sequence, and taking the operation fault as the target fault debugging strategy; and responding to the fault type as the verification missing fault of the fault object in the chip verification process, calling a corresponding function test sequence, supplementing the missing function to be verified of the fault object according to the running result of the function test sequence, and using the function to be verified as the target fault debugging strategy.

According to an embodiment of the present application, the executing the target fault debugging policy and performing fault debugging on the fault include: in response to identifying the fault, starting a general debugging library, wherein the general debugging library is connected with the chip verification platform; and receiving a target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the universal debugging library, and executing the target fault debugging strategy according to the target fault debugging instruction.

According to an embodiment of the present application, the starting a universal debug library includes: triggering a starting code to run, and starting the universal debugging library, wherein the starting code is compiled in a code of a chip verification platform; or executing a script and starting the universal debugging library.

According to an embodiment of the present application, after executing the target debugging processing policy and performing fault debugging on the fault, the method further includes: receiving a debugging detection instruction transmitted by the universal debugging library; and operating the debugging detection instruction, and determining that the fault debugging in the chip verification process is finished according to the operation result of the debugging detection instruction.

A second aspect of the present application provides a device for handling a fault in a chip verification process, including: the identification module is used for identifying faults in the chip verification process and acquiring fault information of the faults in response to identifying the faults; the determining module is used for determining a target fault debugging strategy matched with the fault information; the debugging module is used for executing the target fault debugging strategy and carrying out fault debugging on the fault; and the verification module is used for responding to the end of the fault debugging and continuing the chip verification process from the position point of the fault.

The fault handling apparatus in the chip verification process provided by the second aspect of the present application further has the following technical features, including:

according to an embodiment of the present application, the determining module is further configured to: determining a fault object and a corresponding fault type in the chip verification process from the fault information; and determining the target fault debugging strategy according to the fault object and the fault type.

According to an embodiment of the present application, the determining module is further configured to: responding to the fault type as the configuration fault of the fault object in the chip verification process, modifying the configuration parameters of the fault object, and using the configuration parameters as the target fault debugging strategy; responding to the fault type as the operation fault of the fault object in the chip verification process, calling a matched debugging test sequence, debugging the operation fault of the fault object according to the operation result of the debugging test sequence, and taking the operation fault as the target fault debugging strategy; and responding to the fault type as the verification missing fault of the fault object in the chip verification process, calling a corresponding function test sequence, supplementing the missing function to be verified of the fault object according to the running result of the function test sequence, and using the function to be verified as the target fault debugging strategy.

According to an embodiment of the present application, the debugging module is further configured to: in response to identifying the fault, starting a general debugging library, wherein the general debugging library is connected with the chip verification platform; and receiving a target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the universal debugging library, and executing the target fault debugging strategy according to the target fault debugging instruction.

According to an embodiment of the present application, the debugging module is further configured to: triggering a starting code to run, and starting the universal debugging library, wherein the starting code is compiled in a code of a chip verification platform; or executing a script and starting the universal debugging library.

According to an embodiment of the present application, the debugging module is further configured to: receiving a debugging detection instruction transmitted by the universal debugging library; and operating the debugging detection instruction, and determining that the fault debugging in the chip verification process is finished according to the operation result of the debugging detection instruction.

An embodiment of a third aspect of the present application provides an electronic device, including: at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor, so that the at least one processor can execute the fault handling method in the chip verification process provided by the first aspect of the present application.

A fourth aspect of the present application provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the fault handling method in the chip verification process provided in the first aspect of the present application.

In an embodiment of the fifth aspect of the present application, a computer program product is provided, and when an instruction processor in the computer program product is executed, the method for processing a fault in a chip verification process provided in the first aspect of the present application is performed.

According to the fault processing method and device in the chip verification process, fault identification is carried out in the chip verification process, and corresponding fault information is obtained after the fault is identified. And determining a matched target fault debugging strategy according to the acquired fault information. And further, executing a target fault debugging strategy, and after the fault debugging is finished, continuing to perform chip verification from the fault position. In the method and the device, the fault debugging in the chip verification process is realized, the modification of the source code corresponding to the chip verification and the re-simulation of the modified source code are avoided, the fault repairing time in the chip verification process is effectively shortened, and the chip verification efficiency is further improved.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic flowchart illustrating a fault handling method in a chip verification process according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of a fault handling method in a chip verification process according to another embodiment of the present application;

fig. 3 is a schematic flowchart of a fault handling method in a chip verification process according to another embodiment of the present application;

fig. 4 is a schematic flowchart of a fault handling method in a chip verification process according to another embodiment of the present application;

fig. 5 is a schematic structural diagram of a fault handling apparatus in a chip verification process according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a fault handling apparatus in a chip verification process according to another embodiment of the present application;

fig. 7 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application and should not be construed as limiting the present application.

A method, an apparatus, an electronic device, and a storage medium for handling a failure in a chip verification process according to embodiments of the present application are described below with reference to the drawings.

Fig. 1 is a schematic flow chart of a fault handling method in a chip verification process according to an embodiment of the present application, and as shown in fig. 1, the method includes:

s101, fault identification is carried out in the chip verification process, and fault information of the faults is obtained in response to the identification of the faults.

In the implementation, the chip verification can be realized through a built chip verification platform, and the monitoring of the verification process of the chip can be realized through the operation monitoring of the chip verification platform.

In the embodiment of the application, the corresponding codes can exist through the chip and the chip verification platform, and the verification process of the chip can be monitored through the printing information in the codes.

Wherein, the fault occurring in the chip verification process can be identified through the printing information.

Further, after the fault is identified, the verification process of the chip can be suspended, and the relevant information of the fault occurring in the current chip verification process can be obtained according to the printing information.

The fault occurring in the chip verification process may include partial loss of the function to be verified of the chip, operation jam in the chip verification process, and the like.

And S102, determining a target fault debugging strategy matched with the fault information.

In the implementation, each step in the verification process of the chip has the possibility of failure, so that a debugging method which can effectively debug the chip and solve the failure problem needs to be determined according to detailed contents included in the failure information, and a matched target failure debugging strategy is further generated.

For example, if a fault occurs in the chip verification process, and the code to be verified corresponding to the function to be verified of the chip cannot call the required parameter, the parameter calling process can be debugged, and then a matched target fault debugging strategy is generated.

For another example, if the fault occurring in the chip verification process is an operation stuck, the step of the operation stuck can be adjusted, the cause of the operation stuck can be analyzed, and a matched target fault debugging strategy can be generated.

S103, executing a target fault debugging strategy and carrying out fault debugging on the fault.

In the embodiment of the application, the chip verification platform can perform related operations according to the information carried in the target fault debugging strategy, so that the debugging of faults occurring in the chip verification process is realized.

For example, the relevant parameters are called according to the target fault debugging strategy. As another example, the stuck may be adjusted according to a target bug debugging policy.

It can be understood that the debugging of the fault occurring in the chip verification process is realized by executing the steps carried in the target fault debugging strategy.

And S104, responding to the end of the fault debugging, and continuing the chip verification process from the fault position point.

In an implementation, whether the current fault debugging is finished or not may be determined based on the correlation setting.

Further, according to the fault debugging result after the debugging is finished, the verification process of the chip can be continuously executed.

It can be understood that the operation result after debugging is a correct result corresponding to the position where the fault occurs in the chip verification process, and therefore, the verification of the chip can be continuously executed from the position where the fault occurs based on the correct result.

According to the fault processing method in the chip verification process, fault identification is carried out in the chip verification process, and corresponding fault information is obtained after the fault is identified. And determining a matched target fault debugging strategy according to the acquired fault information. And further, executing a target fault debugging strategy, and after the fault debugging is finished, continuing to perform chip verification from the fault position. In the method and the device, the fault debugging in the chip verification process is realized, the modification of the source code corresponding to the chip verification and the re-simulation of the modified source code are avoided, the fault repairing time in the chip verification process is effectively shortened, and the chip verification efficiency is further improved.

In the foregoing embodiment, regarding the determination of the target fault debugging policy, it can be further understood by referring to fig. 2, where fig. 2 is a schematic flow chart of a fault processing method in a chip verification process according to another embodiment of the present application, and as shown in fig. 2, the method includes:

s201, determining a fault object and a corresponding fault type in the chip verification process from the fault information.

In the embodiment of the application, a fault object which has a fault in the chip verification process can be determined from the fault information, for example, a certain operation step in the chip verification process, and further, a certain parameter configured in the chip verification process, and the like.

Further, a fault type corresponding to the fault object is obtained.

Alternatively, the relevant information of the fault object and the corresponding fault type may be acquired from the print information of the chip verification.

When a fault occurs in the chip verification process, the text information and/or the return code information of the fault object and the corresponding text information and/or the return code information of the fault type can be presented in the printing information, and then the information of the fault object and the corresponding information of the fault type can be determined.

S202, determining a target fault debugging strategy according to the fault object and the fault type.

Further, after the fault object and the corresponding fault type are obtained, the corresponding target fault debugging strategy can be determined according to the corresponding solution method.

Optionally, in response to that the fault type is a configuration fault of a fault object in a chip verification process, modifying a configuration parameter of the fault object, and using the configuration parameter as a target fault debugging policy.

In the embodiment of the application, in order to enable the test case to normally operate, the chip verification platform needs to configure corresponding operation support for the test case. In the configuration process of the relevant operation support, there may be a case where a parameter configuration is wrong or an object configuration is wrong, and it may be determined as a configuration failure of a failed object.

Further, in a fault scenario in which a fault object cannot operate or operates incorrectly due to a configuration fault in the chip verification process, relevant configuration parameters may be modified and used as a target fault debugging policy in the fault scenario.

For example, for a register configured for a test case by a test verification platform, if the register has a parameter configuration error, a code to be verified may have a condition that required information cannot be obtained from the register, or an intermediate operation result of the code to be verified cannot be stored in the register, so that the code to be verified in the test case cannot normally operate.

In the fault scenario, the fault object is a register configured by the chip verification platform for the test case, and the fault type is a configuration fault corresponding to the parameter configuration error, so that the debugging method for modifying the register parameter can be determined as a target fault debugging strategy in the fault scenario.

Optionally, in response to the fault type being an operation fault of the fault object in the chip verification process, calling the matched debugging test sequence, debugging the operation fault of the fault object according to an operation result of the debugging test sequence, and using the operation fault as a target fault debugging strategy.

In the embodiment of the application, for verifying a certain function to be verified of a chip, all operation steps for realizing the function need to be simulated, wherein operation of a certain step may fail.

In the implementation, a plurality of test sequences exist in the test case corresponding to a certain function to be verified, and each test sequence can simulate at least one operation step, so that when a certain operation step fails, it can be understood that the corresponding test sequence fails.

Optionally, the test sequence with the operation fault may be adjusted by calling another test sequence, and is used as a corresponding repair test sequence. The test sequence with the operation fault can be debugged by repairing the operation result of the test sequence.

As a possible implementation manner, the test sequence with the operation fault has a possibility that the operation result after the operation of the test sequence is finished is wrong, in the fault scenario, the repair operation result of the repair test sequence can be used to replace the fault result of the test sequence with the operation fault, and the repair operation result is used as the correct operation result of the step to be operated corresponding to the test sequence with the operation fault. And further debugging the test sequence with the operation fault based on the repair operation result.

As another possible implementation manner, a test sequence with an operation fault has a possibility that the test sequence cannot continue to operate due to the fault in the operation process of the test sequence, and in the fault scenario, the test sequence with the fault has an intermediate result of already operating.

Optionally, in the fault sub-scenario in which the intermediate result is the correct result, the repair operation result of the repair test sequence and the intermediate result may be integrated, and the integrated operation result is used as the correct operation result corresponding to the to-be-operated step corresponding to the test sequence in which the operation fault occurs. And further debugging the test sequence with the operation fault based on the integrated operation result.

Optionally, in the fault scenario in which the intermediate result is the error result, the test sequence with the operation fault may be replaced based on the repair operation result of the repair test sequence, and the repair operation result of the repair test sequence may be used as the correct operation result of the to-be-operated step corresponding to the test sequence with the operation fault. And further debugging the test sequence with the operation fault based on the repair operation result.

And further, responding to the verification missing fault of the fault object in the chip verification process as the fault type, calling a corresponding function test sequence, supplementing the missing function to be verified of the fault object according to the operation result of the function test sequence, and using the function to be verified as a target fault debugging strategy.

In the embodiment of the application, the chip has a plurality of functions to be verified, wherein a possibility that a verification missing fault occurs in part of the functions to be verified may exist.

In some implementations, there is a possibility that the function to be verified is not verified.

In the fault scenario, the chip verification platform may construct a corresponding test case based on the function to be verified, and determine the test case as a corresponding target fault debugging policy. Based on the simulation of the test case in the target fault debugging strategy, the verification of the function to be verified can be realized.

In other implementations, there is a possibility that the function to be verified may only be partially verified.

In the fault scenario, the chip verification platform may construct a corresponding test sequence based on the missing verification portion, and determine it as a corresponding target fault debugging policy. Based on the simulation of the test sequence in the target fault debugging strategy, the verification of the function to be verified can be realized.

According to the fault processing method in the chip verification process, the fault object and the corresponding fault type are determined from the fault information, and then the corresponding target fault debugging strategy is determined. Based on detailed fault information, the accuracy and effectiveness of a target fault debugging strategy are improved, the time consumed by fault debugging is shortened, and the efficiency of chip verification fault debugging and the efficiency of chip verification are effectively improved.

In the above embodiment, the obtaining of the fault information and the executing of the target fault debugging policy may also be implemented by a general debugging library, which can be further understood by referring to fig. 3, where fig. 3 is a schematic flow diagram of a fault processing method in a chip verification process according to another embodiment of the present application, and as shown in fig. 3, the method includes:

s301, responding to the identification of the fault, starting a universal debugging library, wherein the universal debugging library is connected with the chip verification platform.

In the implementation, the chip verification platform has a matched universal debugging library, and after the chip verification platform starts to simulate, information interaction between the chip verification platform and other devices can be realized through the universal debugging library.

As a possible implementation manner, the boot code may be triggered to run, and the universal debug library is started, where the boot code is compiled in the code of the chip verification platform.

In the embodiment of the application, the boot code corresponding to the universal debugging library can be compiled in the chip verification platform.

For example, a code of a chip verification platform is written based on an SV language (System Verilog), a boot code corresponding to the universal debug library is compiled into the code, and the universal debug library is booted based on the operation of the boot code.

The corresponding trigger event can be set for the starting code corresponding to the universal debugging library. When a corresponding trigger event occurs, the operation of the start code can be triggered, and then the universal debugging library is started.

Optionally, the corresponding trigger event may be set to a failure in the chip verification process. It can be understood that, when a fault occurs in the chip verification process, the start code of the general debug library may obtain a corresponding enable instruction, and based on the enable instruction, the start code is run to start the general debug library.

Alternatively, the corresponding trigger event may be set to a pause in the chip verification process. It can be understood that, when the chip verification process fails, the chip verification process may be suspended, and when the chip verification process is suspended, the start code of the general debug library may obtain the corresponding enable instruction, and based on the enable instruction, the start code is run to start the general debug library.

As another possible implementation, a script may be executed to launch a universal debug library.

In the embodiment of the application, the universal debugging inventory is in the corresponding starting script, and the starting of the universal debugging inventory can be realized through the execution of the starting script.

For example, a Tool Command Language (TCL) may be used to write a start script corresponding to the universal debug library, and the start of the universal debug library may be implemented based on the execution of the TCL script.

Alternatively, a start script of the general debugging library may be preset and stored in a set position. Furthermore, a corresponding trigger event is set for the start script of the universal debugging library. When the trigger event occurs, the execution of the start script can be automatically triggered, and further the start of the universal debugging library is realized.

The corresponding trigger event may be set as a fault occurring in the chip verification process, or may be set as a pause of the chip verification process.

Optionally, when a fault is identified in the chip verification process, a corresponding script input window may be obtained, and a start script of the universal debug library is input in the window, so that the universal debug library is started by executing the start script.

The script input window can be popped up by triggering through a fault in the chip verification process, or by triggering through a pause in the chip verification process.

Further, the universal debugging library can provide a relevant operation interface, and the chip verification platform can have data interaction with other devices based on the starting of the universal debugging library.

S302, receiving a target fault debugging command corresponding to the target fault debugging strategy transmitted by the universal debugging library, and executing the target fault debugging strategy according to the target fault debugging command.

In the embodiment of the application, the transmission of the target fault debugging strategy to the chip verification platform can be realized through data interaction between the universal debugging library and the chip verification platform.

Optionally, the universal debugging library is in a set input format, so that the target fault debugging strategy can be converted based on the input format set by the universal debugging library to generate a corresponding target fault debugging instruction, and the target fault debugging instruction is transmitted to the chip verification platform through the universal debugging library.

Optionally, the general debugging library is in a set instruction, the set instruction is combined based on the target fault debugging strategy, a corresponding target fault debugging instruction is further generated, and the target fault debugging instruction is transmitted to the chip verification platform through the general debugging library.

The target fault debugging instruction carries a debugging method for faults occurring in the chip verification process, and the chip verification platform can read and execute the debugging method carried in the target fault debugging instruction based on the received target fault debugging instruction, so that the faults occurring in the chip verification process are debugged.

According to the fault processing method in the chip verification process, data interaction with the chip verification platform is achieved through starting of the universal debugging library, and then the target fault debugging strategy is transmitted to the chip verification platform. Further, the chip verification platform debugs the fault occurring in the chip verification process based on the received target fault debugging instruction corresponding to the target fault debugging strategy. In the application, the debugging of the faults occurring in the chip verification process is realized by starting the universal debugging library, and the efficiency of debugging the chip verification faults is improved.

Further, to debug the fault in the chip verification process, further detection is required to obtain the result of the fault debugging. As can be understood by referring to fig. 4, fig. 4 is a schematic flowchart of a fault handling method in a chip verification process according to another embodiment of the present application, and as shown in fig. 4, the method includes:

s401, receiving a debugging detection instruction transmitted by the universal debugging library.

In the embodiment of the application, in order to ensure the accuracy of chip verification, the fault debugging in the chip verification process needs to be detected.

Alternatively, detection may be performed by debugging a detection instruction. Wherein the debug detect instruction may be set based on a target debug policy.

Further, after the set debugging detection instruction is transmitted to the chip verification platform through the universal debugging library, the chip verification platform can detect the result of the fault debugging based on the received instruction.

The debugging detection instruction may be detection after debugging the running step, or detection after debugging a parameter with a configuration error.

S402, running a debugging detection instruction, and determining that the fault debugging in the chip verification process is completed according to the running result of the debugging detection instruction.

In the embodiment of the application, the result of the fault debugging can be detected based on the operation of the debugging detection instruction, wherein the corresponding detection time length can be set, and the fault debugging result is judged according to the operation result in the detection time length.

Optionally, the debug detect instruction may detect debugging of the running step failure.

The fault operation step can be debugged by calling the matched repair test sequence, so that the repair operation result of the repair test sequence can be detected. The subsequent steps of chip verification can be continuously operated from the debugged fault position, the operation is suspended when the operation time length reaches the set detection time length, and the operation result in the detection time length is obtained.

Optionally, the debug detect instruction may detect a faulty debug of the configuration parameter error.

The configuration parameter error can be debugged by modifying the configuration parameter, so that the debugged parameter can be detected. The chip verification can be operated based on the debugged configuration parameters, the operation is suspended when the operation duration reaches the set detection duration, and the operation result in the detection duration is obtained.

Further, if the operation result within the detection duration is correct, it may be determined that the fault debugging is successful. Correspondingly, if the operation result within the detection duration is abnormal, it can be judged that the debugging of the current fault is unsuccessful, and the target fault debugging strategy needs to be adjusted until the debugging is successful, and the adjustment is finished.

According to the fault processing method in the chip verification process, the result of fault debugging is detected through the debugging detection instruction, and therefore the fault occurring in the chip verification process is accurately debugged.

Corresponding to the failure processing methods in the chip verification process provided in the foregoing embodiments, an embodiment of the present application further provides a failure processing apparatus in the chip verification process, and since the failure processing apparatus in the chip verification process provided in the embodiment of the present application corresponds to the failure processing methods in the chip verification process provided in the foregoing embodiments, the implementation of the failure processing method in the chip verification process is also applicable to the failure processing apparatus in the chip verification process provided in the embodiment of the present application, and will not be described in detail in the following embodiments.

Fig. 5 is a schematic structural diagram of a fault handling apparatus in a chip verification process according to an embodiment of the present application, and as shown in fig. 5, the fault handling apparatus 500 in the chip verification process includes an identification module 51, a determination module 52, a debugging module 53, and a verification module 54, where:

the identification module 51 is used for identifying faults in the chip verification process and acquiring fault information of the faults in response to identifying the faults;

a determining module 52, configured to determine a target fault debugging policy that matches the fault information;

the debugging module 53 is used for executing a target fault debugging strategy and performing fault debugging on the fault;

and the verification module 54 is used for responding to the end of the fault debugging and continuing the chip verification process from the fault position point.

Fig. 6 is a schematic structural diagram of a fault handling apparatus in a chip verification process according to another embodiment of the present application, and as shown in fig. 6, the fault handling apparatus 600 in the chip verification process includes an identification module 61, a determination module 62, a debugging module 63, and a verification module 64, where:

the identification module 51, the determination module 52, the debugging module 53, the verification module 54, and the identification module 61, the determination module 62, the debugging module 63, and the verification module 64 have the same configuration and function.

In this embodiment of the application, the determining module 62 is further configured to: determining a fault object and a corresponding fault type in the chip verification process from the fault information; and determining a target fault debugging strategy according to the fault object and the fault type.

In this embodiment of the application, the determining module 62 is further configured to: responding to the fault type as the configuration fault of the fault object in the chip verification process, modifying the configuration parameters of the fault object, and using the configuration parameters as a target fault debugging strategy; responding to the fault type as the operation fault of the fault object in the chip verification process, calling a matched debugging test sequence, debugging the operation fault of the fault object according to the operation result of the debugging test sequence, and taking the operation fault as a target fault debugging strategy; and responding to the verification missing fault of the fault object in the chip verification process as the fault type, calling a corresponding function test sequence, supplementing the missing function to be verified of the fault object according to the operation result of the function test sequence, and using the function to be verified as a target fault debugging strategy.

In this embodiment of the present application, the debugging module 63 is further configured to: in response to identifying the fault, starting a universal debugging library, wherein the universal debugging library is connected with the chip verification platform; and receiving a target fault debugging command corresponding to the target fault debugging strategy transmitted by the general debugging library, and executing the target fault debugging strategy according to the target fault debugging command.

In this embodiment of the present application, the debugging module 63 is further configured to: triggering a starting code to run, and starting a universal debugging library, wherein the starting code is compiled in a code of a chip verification platform; or executing the script and starting the universal debugging library.

In this embodiment of the present application, the debugging module 63 is further configured to: receiving a debugging detection instruction transmitted by a general debugging library;

and running the debugging detection instruction, and determining that the fault debugging in the chip verification process is finished according to the running result of the debugging detection instruction.

The fault processing device in the chip verification process carries out fault identification in the chip verification process and acquires corresponding fault information after identifying the fault. And determining a matched target fault debugging strategy according to the acquired fault information. And further, executing a target fault debugging strategy, and after the fault debugging is finished, continuing to perform chip verification from the fault position. In the method and the device, the fault debugging in the chip verification process is realized, the modification of the source code corresponding to the chip verification and the re-simulation of the modified source code are avoided, the fault repairing time in the chip verification process is effectively shortened, and the chip verification efficiency is further improved.

To achieve the above embodiments, the present application also provides an electronic device, a computer readable storage medium and a computer program product.

Fig. 7 is a block diagram of an electronic device according to an embodiment of the present application, and a fault handling method in the chip verification process according to the embodiment of fig. 1 to 4 may be implemented by the electronic device shown in fig. 7.

In order to implement the foregoing embodiments, the present application further provides a readable storage medium storing computer instructions for causing a computer to execute the fault handling method in the chip verification process of the embodiments of fig. 1 to 4.

In order to implement the foregoing embodiments, the present application further provides a computer program product, which when executed by an instruction processor in the computer program product, executes the fault handling method in the chip verification process of the embodiments of fig. 1 to 4.

In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present application.

The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present application may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims (14)

1. A fault processing method in a chip verification process is characterized by comprising the following steps:

fault identification is carried out in the chip verification process, and fault information of the fault is obtained in response to the fault identification;

determining a target fault debugging strategy matched with the fault information;

executing the target fault debugging strategy, and performing fault debugging on the fault;

and responding to the end of fault debugging, and continuing the chip verification process from the position point of the fault.

2. The method of claim 1, wherein determining the target fault debugging policy that matches the fault information comprises:

determining a fault object and a corresponding fault type in the chip verification process from the fault information;

and determining the target fault debugging strategy according to the fault object and the fault type.

3. The method of claim 2, wherein determining the target fault debugging policy based on the fault object and the fault type comprises:

responding to the fault type as the configuration fault of the fault object in the chip verification process, modifying the configuration parameters of the fault object, and using the configuration parameters as the target fault debugging strategy;

responding to the fault type as the operation fault of the fault object in the chip verification process, calling a matched debugging test sequence, debugging the operation fault of the fault object according to the operation result of the debugging test sequence, and taking the operation fault as the target fault debugging strategy;

and responding to the fault type as the verification missing fault of the fault object in the chip verification process, calling a corresponding function test sequence, supplementing the missing function to be verified of the fault object according to the running result of the function test sequence, and using the function to be verified as the target fault debugging strategy.

4. The method of claim 1, wherein the executing the target troubleshooting policy to troubleshoot the fault comprises:

in response to identifying the fault, starting a general debugging library, wherein the general debugging library is connected with the chip verification platform;

and receiving a target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the universal debugging library, and executing the target fault debugging strategy according to the target fault debugging instruction.

5. The method of claim 4, wherein the launching the universal debug library comprises:

triggering a starting code to run, and starting the universal debugging library, wherein the starting code is compiled in a code of a chip verification platform; alternatively, the first and second electrodes may be,

and executing the script and starting the universal debugging library.

6. The method according to claim 4 or 5, wherein the executing the target debugging processing policy further comprises, after performing fault debugging on the fault:

receiving a debugging detection instruction transmitted by the universal debugging library;

and operating the debugging detection instruction, and determining that the fault debugging in the chip verification process is finished according to the operation result of the debugging detection instruction.

7. A fault handling device in a chip verification process is characterized by comprising:

the identification module is used for identifying faults in the chip verification process and acquiring fault information of the faults in response to identifying the faults;

the determining module is used for determining a target fault debugging strategy matched with the fault information;

the debugging module is used for executing the target fault debugging strategy and carrying out fault debugging on the fault;

and the verification module is used for responding to the end of the fault debugging and continuing the chip verification process from the position point of the fault.

8. The apparatus of claim 7, wherein the determining module is further configured to:

determining a fault object and a corresponding fault type in the chip verification process from the fault information;

and determining the target fault debugging strategy according to the fault object and the fault type.

9. The apparatus of claim 8, wherein the determining module is further configured to:

responding to the fault type as the configuration fault of the fault object in the chip verification process, modifying the configuration parameters of the fault object, and using the configuration parameters as the target fault debugging strategy;

responding to the fault type as the operation fault of the fault object in the chip verification process, calling a matched debugging test sequence, debugging the operation fault of the fault object according to the operation result of the debugging test sequence, and taking the operation fault as the target fault debugging strategy;

and responding to the fault type as the verification missing fault of the fault object in the chip verification process, calling a corresponding function test sequence, supplementing the missing function to be verified of the fault object according to the running result of the function test sequence, and using the function to be verified as the target fault debugging strategy.

10. The apparatus of claim 7, wherein the debugging module is further configured to:

in response to identifying the fault, starting a general debugging library, wherein the general debugging library is connected with the chip verification platform;

and receiving a target fault debugging instruction corresponding to the target fault debugging strategy transmitted by the universal debugging library, and executing the target fault debugging strategy according to the target fault debugging instruction.

11. The apparatus of claim 10, wherein the debugging module is further configured to:

triggering a starting code to run, and starting the universal debugging library, wherein the starting code is compiled in a code of a chip verification platform; alternatively, the first and second electrodes may be,

and executing the script and starting the universal debugging library.

12. The apparatus of claim 10 or 11, wherein the debugging module is further configured to:

receiving a debugging detection instruction transmitted by the universal debugging library;

and operating the debugging detection instruction, and determining that the fault debugging in the chip verification process is finished according to the operation result of the debugging detection instruction.

13. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

14. A readable storage medium having stored thereon computer instructions for causing a computer to perform the method of any one of claims 1-6.

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