CN114355148B - Inverter power tube open-circuit fault diagnosis method and device and electronic equipment - Google Patents
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Abstract
The invention provides an inverter power tube open-circuit fault diagnosis method, an inverter power tube open-circuit fault diagnosis device and electronic equipment, wherein the method comprises the following steps: detecting, for any phase in the inverter, a first line voltage state and a second line voltage state associated with the any phase; determining whether the first line voltage state is a fault phase based on the first line voltage state and the second line voltage state; determining a level sequence of the first line voltage state in the fault phase, and acquiring a fault mark; and determining a fault power tube in the fault phase according to the fault mark. The method can accurately diagnose the open-circuit fault, has better robustness, and is not influenced by carrier frequency and load fluctuation.
Description
Technical Field
The invention belongs to the technical field of fault detection, and particularly relates to an open-circuit fault diagnosis method and device for an inverter power tube and electronic equipment.
Background
When the inverter fails, physical quantities such as voltage and current in the three-phase circuit change relative to normal conditions, and information or phenomena of the changes can be regarded as characteristic signals of the failure. And detecting and identifying the characteristic signals in real time, namely detecting and diagnosing the inverter fault. Due to the consensus on the serious consequences caused by inverter faults, research on fault diagnosis methods has been carried out early. Through the development of many years, the research of fault diagnosis technology obtains abundant research results, and mainly comprises a current detection method, a voltage detection method and the like.
In order to overcome the above-mentioned disadvantages, a voltage detection method is proposed, which requires at least one fundamental period of time between the occurrence of a fault and the detection of the fault, based on the fault identification of the current mode. When no driving fault occurs at the base electrode of the inverter power switch, the voltage of each phase of the inverter has deviation compared with the voltage in normal operation. Such a fault can be diagnosed from the voltage deviation. The existing voltage detection method needs to add hardware equipment, has redundant hardware and increases cost, and is easily influenced by carrier frequency and load fluctuation.
Disclosure of Invention
The invention provides a method and a device for diagnosing open-circuit faults of an inverter power tube and electronic equipment, and aims to solve the problem that the existing voltage detection method is redundant in hardware and is easily influenced by carrier frequency and load fluctuation.
In view of the above, an embodiment of the present invention provides an open-circuit fault diagnosis circuit for an inverter power tube, including: detecting, for any phase in the inverter, a first line voltage state and a second line voltage state associated with the any phase; determining whether the one phase is a failed phase according to the first line voltage state and the second line voltage state; determining a level sequence of the first line voltage state in the fault phase, and acquiring a fault mark; and determining a fault power tube in the fault phase according to the fault mark.
Optionally, the identifying whether any one of the phases is a fault phase according to the first line voltage status and the second line voltage status includes: performing logical AND operation according to the first line voltage state and the second line voltage state to obtain a logical operation result; and determining whether any phase is a fault phase according to the logical operation result.
Optionally, the detecting a first line voltage state and a second line voltage state associated with the either one includes: detecting a first line voltage and a second line voltage associated with the either; determining a first line voltage state corresponding to the first line voltage and a second line voltage state corresponding to the second line voltage according to the first line voltage and the second line voltage, respectively.
Optionally, the determining a first line voltage state corresponding to the first line voltage and a second line voltage state corresponding to the second line voltage according to the first line voltage and the second line voltage, respectively, includes: determining a first positive level state and a first negative level state associated with the first line voltage from the first line voltage; determining a second positive level state and a second negative level state associated with the second line voltage from the second line voltage; performing a logical OR operation according to the first positive level state and the first negative level state to determine the first line voltage state, and performing a logical OR operation according to the second positive level state and the second negative level state to determine the second line voltage state.
Optionally, the determining a first positive level state and a first negative level state associated with the first line voltage according to the first line voltage includes: determining that the first positive level state is a first state flag if the first line voltage is within a preset range of a first reference voltage, otherwise determining that the first positive level state is a second state flag; determining that the first negative level state is the first state flag if the first line voltage is within a preset range of a second reference voltage, otherwise determining that the first negative level state is the second state flag; the determining a second positive level state and a second negative level state associated with the second line voltage from the second line voltage includes: determining that the second line voltage state is the first state flag if the second line voltage is within the preset range of the first reference voltage, otherwise determining that the second line voltage state is the second state flag; determining the second negative level state as the first state flag if the second line voltage is within the preset range of the second reference voltage, otherwise determining the second negative level state as the second state flag.
Optionally, the determining a level sequence of the first line voltage state in the fault phase and acquiring a fault flag includes: determining the level order according to a temporal order of occurrence of the first positive level state as a first state flag and the first negative level state as the first state flag in the first line voltage state; setting the fault flag to a first flag value if the level sequence is that the first positive level state is that the first state flag occurs first; setting the fault flag to a second flag value if the level sequence is that the first negative level state is that the first state flag occurs first.
Optionally, the determining a faulty power tube in the faulty phase according to the fault flag includes: if the fault mark is a first mark value, determining that a fault power tube in the fault phase is a power tube of an upper bridge arm; and if the fault mark is a second mark value, determining that the fault power tube in the fault phase is the power tube of the lower bridge arm.
Based on the same inventive concept, the embodiment of the invention also provides an inverter power tube open-circuit fault diagnosis device, which comprises: a voltage state determination unit for detecting, for any phase in the inverter, a first line voltage state and a second line voltage state associated with the any phase; a faulty phase determination unit for determining whether the any one phase is a faulty phase according to the first line voltage state and the second line voltage state; a fault flag acquiring unit configured to determine a level sequence of the first line voltage state in the fault phase and acquire a fault flag; and the fault diagnosis unit is used for determining a fault power tube in the fault phase according to the fault mark.
Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the foregoing method when executing the computer program.
Based on the same inventive concept, the embodiment of the present invention further provides a computer storage medium, in which at least one executable instruction is stored, and the executable instruction causes a processor to execute the foregoing method.
The technical effect of the present invention is that, as can be seen from the above, the method, the apparatus and the electronic device for diagnosing the open-circuit fault of the inverter power tube provided in the embodiments of the present invention include: detecting, for any phase in the inverter, a first line voltage state and a second line voltage state associated with the any phase; determining whether the one phase is a failed phase according to the first line voltage state and the second line voltage state; determining a level sequence of the first line voltage state in the fault phase, and acquiring a fault mark; and determining a fault power tube in the fault phase according to the fault mark, accurately diagnosing the open-circuit fault, having better robustness and being not influenced by carrier frequency and load fluctuation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart of an open-circuit fault diagnosis method for an inverter power tube in an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of an inverter according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an open-circuit fault diagnosis device for an inverter power tube in an embodiment of the invention;
fig. 4 is a schematic structural diagram of an electronic device in an embodiment of the present invention.
Detailed Description
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
It is to be noted that technical terms or scientific terms used in the embodiments of the present invention should have the ordinary meanings as understood by those having ordinary skill in the art to which the present disclosure belongs, unless otherwise defined. The use of "first," "second," and the like in the embodiments of the present invention does not denote any order, quantity, or importance, but rather the terms "first," "second," and the like are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item preceding the word comprises the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
The embodiment of the invention provides an open-circuit fault diagnosis method for an inverter power tube, which is applied to electronic equipment for detecting open-circuit faults of an inverter. As shown in fig. 1, the method for diagnosing open-circuit fault of inverter power tube includes:
step S11: for any phase in the inverter, a first line voltage state and a second line voltage state associated with the any phase are detected.
In the embodiment of the present invention, the inverter has a structure as shown in fig. 2, including A, B, C three phases, wherein
Is a power tube, x =1, 2, 3, 4, 5, 6,
and
in the form of a line voltage,
is a dc voltage. The phase A comprises a power tube VT1 of an upper bridge arm and a power tube VT2 of a lower bridge arm, the phase B comprises a power tube VT3 of the upper bridge arm and a power tube VT4 of the lower bridge arm, and the phase C comprises a power tube VT5 of the upper bridge arm and a power tube VT6 of the lower bridge arm. The inverter further includes: inductor L1, resistors R1, R2, R3, R4, switches KM1 and KM2, and capacitors C1 and C2.
In step S11, optionally, a first line voltage and a second line voltage associated with either one are detected. According to the inverter shown in fig. 2, the first line voltage and the second line voltage associated with a are respectively
And
. The first line voltage and the second line voltage associated with B are respectively
And
. The first line voltage and the second line voltage associated with C are respectively
And
. In an embodiment of the invention, a line voltage
And line voltage
Obeying kirchhoff's law:
assume that the control signal is
，
And
wherein, 1 is that the upper bridge arm is conducted and the lower bridge arm is turned off, and 0 is that the lower bridge arm is conducted and the upper bridge arm is turned off. When VT1 fails, there are:
when in use
Then, then
。
When in use
Then, then
。
When in use
Then, then
。
When in use
Then, then
。
When in use
Then, then
。
The same method can be used for the condition of other power tubes when the power tubes fail.
After obtaining the first line voltage and the second line voltage associated with each line, a first line voltage state corresponding to the first line voltage and a second line voltage state corresponding to the second line voltage are determined according to the first line voltage and the second line voltage respectively. Specifically, first determining a first positive level state and a first negative level state associated with the first line voltage from the first line voltage; determining a second positive level state and a second negative level state associated with the second line voltage from the second line voltage. I.e. if the first line voltage is within a first reference voltage range, determining the first positive level stateIs a first status flag, otherwise the first positive level status is determined to be a second status flag; determining the first negative level state as the first state flag if the first line voltage is within a second reference voltage range, otherwise determining the first negative level state as the second state flag. Determining the second line voltage status as the first status flag if the second line voltage is within the first reference voltage range, otherwise determining the second line voltage status as the second status flag; determining the second negative level state as the first state flag if the second line voltage is within the second reference range, otherwise determining the second negative level state as the second state flag. Wherein the first reference voltage range is preferably from delta to
A voltage range of-delta, the second reference voltage range preferably being delta-
The first status flag is preferably 1 and the second status flag is preferably 0 in the voltage range of- δ.
As a reference voltage, can be set as desired. The concrete expression is as follows:
and
are respectively line voltage
Positive level state and negative level state.
Where δ is a reference threshold, which is related to noise, operating environment and interference of the voltage, and can be set as required.
And then performing a logical or operation according to the first positive level state and the first negative level state to determine the first line voltage state, and performing a logical or operation according to the second positive level state and the second negative level state to determine the second line voltage state. In the embodiment of the invention, the line voltage is used
Line voltage
And line voltage
For monitoring quantities, the line voltage state is defined
，
，
Is composed of
. Wherein,
and
are respectively line voltage
Positive level state and negative level state.
In the embodiment of the invention, taking phase B as an example, the first line voltage and the second line voltage are respectively
And
first according to the first line voltage
The voltage range determines a first positive level state
And a first negative level state
According to the second line voltage
The voltage range determines the second positive level state
And a second negative level state
. Then for the first positive level state
And a first negative level state
Performing logical OR operation to obtain the first line voltage state
(ii) a For the second positive level state
And a second negative level state
Performing logical OR operation to obtain the second line voltage state
。
Step S12: whether the any phase is a failed phase according to the first line voltage state and the second line voltage state.
Optionally, performing a logical and operation according to the first line voltage state and the second line voltage state to obtain a logical operation result; and determining whether any phase is a fault phase according to the logical operation result.
In the embodiment of the invention, the fault phase state of A, B, C three phases is determined according to the following logical and operation result:
wherein "0" is normal and "1" is fault. That is, if the logical and operation result of any phase is the first status flag 1, the phase is determined to be faulty. If the logical AND operation result of any phase is the first status flag 0, the phase is determined to be normal.
Step S13: and determining the level sequence of the first line voltage state in the fault phase and acquiring a fault mark.
Optionally, the level sequence is determined according to a time sequence of occurrence of the first positive level state as a first state flag and the first negative level state as the first state flag in the first line voltage state; setting the fault flag to a first flag value if the level sequence is that the first positive level state is that the first state flag occurs first; setting the fault flag to a second flag value if the level sequence is that the first negative level state is that the first state flag occurs first. The first flag value is preferably 10, and the second flag value is preferably 1.
Fault tube is composed of line voltage
Positive level state of
And negative level state
Fault flag determined by appearance sequence of
And (6) determining.
Step S14: and determining a fault power tube in the fault phase according to the fault mark.
If the fault mark is a first mark value, determining that a fault power tube in the fault phase is a power tube of an upper bridge arm; and if the fault mark is a second mark value, determining that the fault power tube in the fault phase is the power tube of the lower bridge arm.
The embodiment of the invention adopts the following program to determine the level sequence of the voltage state of the first line, and determines the value of the fault mark according to the level sequence, thereby determining the fault power tube in the fault phase.
Wherein,
=10 or 1 respectively represents
And
the two different occurrence sequences are used for judging the upper bridge arm fault or the lower bridge arm fault. The fault determination table for 6 power transistors in the inverter obtained by applying the method in this way is shown in table 1, where "-" indicates that the term does not need to be considered.
TABLE 1 Fault diagnosis Table
The method for diagnosing the open-circuit fault of the power tube of the inverter is simple in algorithm, low in hardware requirement, good in robustness, free of influences of carrier frequency, load fluctuation and interphase short circuit at a load end, and still good in diagnosis performance under various control strategies.
The inverter power tube open-circuit fault diagnosis method of the embodiment of the invention detects a first line voltage state and a second line voltage state associated with any phase of the inverter; determining whether the first line voltage state is a fault phase based on the first line voltage state and the second line voltage state; determining a level sequence of the first line voltage state in the fault phase, and acquiring a fault mark; and determining a fault power tube in the fault phase according to the fault mark, accurately diagnosing the open-circuit fault, having better robustness and being not influenced by carrier frequency and load fluctuation.
The foregoing description of specific embodiments of the present invention has been presented. In some cases, acts or steps recited in the present application may be performed in an order different than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Based on the same inventive concept, an embodiment of the present invention further provides an inverter power tube open-circuit fault diagnosis apparatus, as shown in fig. 3, the inverter power tube open-circuit fault diagnosis apparatus includes: the device comprises a voltage state determining unit, a fault phase determining unit, a fault sign acquiring unit and a fault diagnosis unit. Wherein,
a voltage state determination unit for detecting, for any phase in the inverter, a first line voltage state and a second line voltage state associated with the any phase;
a faulty phase determination unit for determining whether the any one phase is a faulty phase according to the first line voltage state and the second line voltage state;
a fault flag acquiring unit configured to determine a level sequence of the first line voltage state in the fault phase and acquire a fault flag;
and the fault diagnosis unit is used for determining a fault power tube in the fault phase according to the fault mark.
For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, the functionality of the various modules may be implemented in the same one or more pieces of software and/or hardware in practicing embodiments of the present invention.
The inverter power tube open-circuit fault diagnosis device in the foregoing embodiment is a corresponding device embodiment in the foregoing embodiment, and has the beneficial effects of a corresponding method embodiment, which are not described again here.
Based on the same inventive concept, embodiments of the present invention further provide an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the method according to any of the above embodiments is implemented.
An embodiment of the present invention provides a non-volatile computer storage medium, where at least one executable instruction is stored in the computer storage medium, and the computer executable instruction may execute the method described in any of the above embodiments.
Fig. 4 is a schematic diagram illustrating a more specific hardware structure of an electronic device according to this embodiment, where the electronic device may include: a processor 401, a memory 402, an input/output interface 403, a communication interface 404, and a bus 405. Wherein the processor 401, the memory 402, the input/output interface 403 and the communication interface 404 are communicatively connected to each other within the device by a bus 405.
The processor 401 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an Application Specific Integrated Circuit (ASIC), or one or more Integrated circuits, and is configured to execute related programs to implement the technical solution provided by the embodiment of the present invention.
The Memory 402 may be implemented in the form of a ROM (Read Only Memory), a RAM (Random access Memory), a static Memory device, a dynamic Memory device, or the like. The memory 402 may store an operating system and other application programs, and when the technical solution provided by the method embodiment of the present invention is implemented by software or firmware, the relevant program codes are stored in the memory 402 and called to be executed by the processor 401.
The input/output interface 403 is used for connecting an input/output module to realize information input and output. The i/o module may be configured as a component in a device (not shown) or may be external to the device to provide a corresponding function. The input devices may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output devices may include a display, a speaker, a vibrator, an indicator light, etc.
The communication interface 404 is used to connect a communication module (not shown in the figure) to implement communication interaction between the present device and other devices. The communication module can realize communication in a wired mode (such as USB, network cable and the like) and also can realize communication in a wireless mode (such as mobile network, WIFI, Bluetooth and the like).
The bus 405 includes a path that transfers information between the various components of the device, such as the processor 401, memory 402, input/output interface 403, and communication interface 404.
It should be noted that although the above-mentioned device only shows the processor 401, the memory 402, the input/output interface 403, the communication interface 404 and the bus 405, in a specific implementation, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will appreciate that the above-described apparatus may also include only those components necessary to implement embodiments of the present invention, and need not include all of the components shown in the figures.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the concept of the present disclosure, also technical features between the above embodiments or different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity.
The present invention is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made within the spirit and principles of the invention are intended to be included within the scope of the disclosure.
Claims (7)
1. An open-circuit fault diagnosis method for an inverter power tube is characterized by comprising the following steps:
detecting, for any phase in the inverter, a first line voltage state and a second line voltage state associated with the any phase;
identifying whether the any phase is a failed phase based on the first line voltage state and the second line voltage state;
determining a level sequence of the first line voltage state in the fault phase, and acquiring a fault mark;
determining a fault power tube in the fault phase according to the fault mark;
wherein said detecting a first line voltage state and a second line voltage state associated with said either comprises: detecting a first line voltage and a second line voltage associated with the either; determining a first positive level state and a first negative level state associated with the first line voltage from the first line voltage; determining a second positive level state and a second negative level state associated with the second line voltage from the second line voltage; performing a logical OR operation according to the first positive level state and the first negative level state to determine the first line voltage state, and performing a logical OR operation according to the second positive level state and the second negative level state to determine the second line voltage state;
determining that the first positive level state is a first state flag if the first line voltage is within a preset range of a first reference voltage, otherwise determining that the first positive level state is a second state flag; determining that the first negative level state is the first state flag if the first line voltage is within a preset range of a second reference voltage, otherwise determining that the first negative level state is the second state flag;
the determining a level sequence of the first line voltage state in the fault phase and obtaining a fault flag includes: determining the level order according to a temporal order of occurrence of the first positive level state as a first state flag and the first negative level state as the first state flag in the first line voltage state; setting the fault flag to a first flag value if the level sequence is that the first positive level state is that the first state flag occurs first; setting the fault flag to a second flag value if the level sequence is that the first negative level state is that the first state flag occurs first.
2. The open circuit fault diagnosis method according to claim 1, wherein said identifying whether any one of the phases is a faulty phase based on the first line voltage status and the second line voltage status includes:
performing logical AND operation according to the first line voltage state and the second line voltage state to obtain a logical operation result;
and determining whether any phase is a fault phase according to the logical operation result.
3. The open circuit fault diagnosis method according to claim 1,
the determining a second positive level state and a second negative level state associated with the second line voltage from the second line voltage includes: determining the second positive level state as the first state flag if the second line voltage is within the preset range of the first reference voltage, otherwise determining the second positive level state as the second state flag; determining the second negative level state as the first state flag if the second line voltage is within the preset range of the second reference voltage, otherwise determining the second negative level state as the second state flag.
4. The open circuit fault diagnostic method of claim 1, the determining a faulty power tube in the faulty phase from the fault signature, comprising:
if the fault mark is a first mark value, determining that a fault power tube in the fault phase is a power tube of an upper bridge arm;
and if the fault mark is a second mark value, determining that the fault power tube in the fault phase is the power tube of the lower bridge arm.
5. An open-circuit fault diagnosis device for an inverter power tube, the device comprising:
a voltage state determination unit for detecting, for any phase in the inverter, a first line voltage state and a second line voltage state associated with the any phase; detecting a first line voltage and a second line voltage associated with the either; determining a first positive level state and a first negative level state associated with the first line voltage from the first line voltage; determining a second positive level state and a second negative level state associated with the second line voltage from the second line voltage; performing a logical OR operation according to the first positive level state and the first negative level state to determine the first line voltage state, and performing a logical OR operation according to the second positive level state and the second negative level state to determine the second line voltage state; determining that the first positive level state is a first state flag if the first line voltage is within a preset range of a first reference voltage, otherwise determining that the first positive level state is a second state flag; determining that the first negative level state is the first state flag if the first line voltage is within a preset range of a second reference voltage, otherwise determining that the first negative level state is the second state flag;
a faulty phase determination unit configured to identify whether or not the any phase is a faulty phase based on the first line voltage state and the second line voltage state;
a fault flag acquiring unit configured to determine a level sequence of the first line voltage state in the fault phase and acquire a fault flag; the method comprises the following steps: determining the level order according to a temporal order of occurrence of the first positive level state as a first state flag and the first negative level state as the first state flag in the first line voltage state; setting the fault flag to a first flag value if the level sequence is that the first positive level state is that the first state flag occurs first; setting the fault flag to a second flag value if the level sequence is that the first negative level state is that the first state flag occurs first;
and the fault diagnosis unit is used for determining a fault power tube in the fault phase according to the fault mark.
6. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1 to 4 when executing the program.
7. A computer storage medium having stored therein at least one executable instruction for causing a processor to perform the method of any one of claims 1-4.
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