CN114339106A - Ultrahigh-definition SDI (Serial digital interface) and IP (Internet protocol) multi-picture signal processor - Google Patents
Ultrahigh-definition SDI (Serial digital interface) and IP (Internet protocol) multi-picture signal processor Download PDFInfo
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- CN114339106A CN114339106A CN202210015791.XA CN202210015791A CN114339106A CN 114339106 A CN114339106 A CN 114339106A CN 202210015791 A CN202210015791 A CN 202210015791A CN 114339106 A CN114339106 A CN 114339106A
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Abstract
The invention discloses an ultra-high definition SDI and IP multi-picture signal processor, which comprises: the SDI signal input interface, the SDI signal output interface and the IP signal input/output module are used for inputting SDI signals and IP signals and outputting display pictures; the scheduling matrix module is used for scheduling different signals to different display picture windows and scheduling display pictures to corresponding output interfaces; the main FPGA is used for converting the serial SDI signals into parallel data and carrying out unified clock synchronization processing; synthesizing an output picture according to the first zooming data returned from the FPGA; and superposing the output picture and the second display element returned from the FPGA to obtain a display picture. The invention can be directly accessed to the ultra-high definition signal, reduces the intermediate processing link, and simplifies the design of the system scheme and the construction cost.
Description
Technical Field
The invention relates to the technical field of multi-picture display processors, in particular to an ultra-high definition SDI (serial digital interface) and IP (Internet protocol) multi-picture signal processor.
Background
With the rapid development of the ultra-high-definition video industry, the 4K/8K ultra-high-definition signal has higher requirements on transmission bandwidth; aiming at the problems of multiple cables, difficult maintenance, limited transmission distance and the like existing in an ultra-high definition signal SDI transmission mode, the characteristics of high bandwidth, high concurrency and bidirectional transmission of an IP technology become the technical evolution direction of an ultra-high definition signal technical solution.
At present, the domestic radio and television system is in a transition stage from an SDI framework to an IP framework, and the coexistence of an SDI signal and an IP signal in the system is a normal state for building a broadcast television system. The multi-picture display processor is used for carrying out scaling processing on the multi-channel signals through a compression technology, then synthesizing a combined picture and outputting the combined picture to a monitor, and the effect of simultaneously monitoring the multi-channel pictures is achieved; besides displaying multiple pictures simultaneously, there is usually a need for displaying characters such as a signal name per channel (UMD), Tally, and a sound post (Audio Bar).
The traditional multi-picture signal processor has poor signal format compatibility, only SDI signals or IP signals can be accessed, and when the IP signals are accessed, IP gateways are needed to complete the monitoring of the IP signals; the direct access of 4K ultra-high-definition video signals is not supported, the picture display layout is not flexible enough, and the size and the position of the window zooming can not be controlled randomly.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an ultra-high definition SDI and IP multi-picture signal processor.
The invention discloses an ultra-high definition SDI and IP multi-picture signal processor, which comprises:
the SDI signal input interface and the SDI signal output interface are used for inputting SDI signals and outputting display pictures;
an IP signal input/output module for inputting IP signals and outputting display pictures;
the scheduling matrix module is connected with the SDI signal input interface, the SDI signal output interface and the IP signal input/output module and is used for scheduling different signals to different display picture windows and scheduling display pictures to corresponding output interfaces;
the master FPGA is connected with the scheduling matrix module and is used for converting serial SDI signals into parallel data and carrying out unified clock synchronization processing; synthesizing an output picture according to the first zooming data returned from the FPGA; superposing the output picture and the display elements to obtain the display picture;
all the first slave FPGAs are connected with the master FPGA through an I2C module and used for scaling data subjected to synchronous processing of a unified clock at different resolutions and returning the scaled data to the master FPGA;
and the second slave FPGA is connected with the master FPGA and used for converting the audio data synchronously processed by the unified clock and returning the converted display elements to the master FPGA.
As a further improvement of the invention, the method also comprises the following steps: ARM and single-chip microcomputer;
the ARM is connected with the scheduling matrix module, the main FPGA and the I2C module through the single chip microcomputer, and is connected with the second slave FPGA and used for:
the user controls the scheduling matrix module through the ARM, selects signals needing to be displayed and schedules different signals to different display picture windows;
the scheduling matrix module schedules the picture to a corresponding output interface according to the output format instruction sent by the ARM;
the first slave FPGA carries out scaling of different resolutions according to the control instruction transmitted by the ARM;
and the second slave FPGA converts the characters input by the user through the ARM into key signals and filling signals, forms dynamic sound column images and texts by audio according to the PCM volume and the number of audio channels, and finally converts the dynamic sound column images and texts into display elements.
As a further improvement of the invention, an HTTP protocol stack is established in the ARM, WEBserver is configured, and the control equipment completes the configuration of the positions, sizes and characters required to be superposed of different channel pictures through a WEB page.
As a further improvement of the present invention, the first slave FPGA writes the received data into the DDR to perform the picture scaling processing.
As a further improvement of the present invention, the main FPGA includes:
a serial-to-parallel conversion module for converting an input serial SDI signal into 20-bit parallel data;
the synthesis module is used for synthesizing an output picture according to the first zooming data returned from the FPGA;
and the superposition module is used for superposing the output picture and the display elements to obtain the display picture.
As a further improvement of the present invention, the number of the first slave FPGAs is 4, and the 4 slave FPGAs can implement processing of a maximum of 8 channels of 4K ultra high definition signals.
Compared with the prior art, the invention has the beneficial effects that:
the invention can directly access the ultra-high definition signal by configuring different interface modules, reduces intermediate processing links, and simplifies system scheme design and construction cost.
Drawings
Fig. 1 is a block diagram of an ultra-high definition SDI, IP multi-picture signal processor according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
The invention is described in further detail below with reference to the attached drawing figures:
as shown in fig. 1, the present invention provides an ultra high definition SDI, IP multi-picture signal processor, comprising: the SDI signal input interface, the SDI signal output interface, the IP signal input/output module, the scheduling matrix module, the main FPGA, the I2C module, 4 first slave FPGAs, 1 second slave FPGA, a DDR, an ARM and the single chip microcomputer;
the connection relationship of each module is as follows:
the SDI signal input interface, the SDI signal output interface and the IP signal input/output module are connected with a scheduling matrix module, the scheduling matrix module is connected with a master FPGA, the master FPGA is connected with an I2C module, the I2C module is connected with 4 first slave FPGAs and 1 second slave FPGA, and the 4 first slave FPGAs and the 1 second slave FPGA are connected with DDR; the ARM is connected with the scheduling matrix module, the main FPGA and the I2C module through the single chip microcomputer, and the ARM is connected with the second slave FPGA.
The functions of each module are as follows:
the SDI signal input interface and the SDI signal output interface are used for inputting SDI signals and outputting display pictures;
the IP signal input/output module is used for inputting a 4K ultra-high definition IP signal and outputting a display picture;
the scheduling matrix module is used for controlling the scheduling matrix module through the ARM by a user, selecting signals needing to be displayed and scheduling different signals to different display picture windows; the picture is dispatched to the corresponding SDI signal output interface and the IP signal input/output module according to the output format command transmitted by the ARM;
a master FPGA to: an internal serial-parallel conversion module converts an input serial SDI signal into 20-bit parallel data and realizes unified clock synchronization processing; the internal synthesis module synthesizes an output picture according to the first zooming data returned from the FPGA; the internal superposition module is used for finishing superposition of the output picture and the display element and then sending the superposed output picture and display element to the scheduling matrix module;
the first slave FPGA is used for writing data content into the DDR to finish picture scaling processing, scaling with different resolutions is realized according to a control instruction transmitted by the ARM, and then the scaled data is returned to a synthesis module in the master FPGA through I2C;
the second slave FPGA is used for realizing image-text processing and converting the image-text processing into a key signal and a filling signal according to characters input by a user through an ARM; forming dynamic sound column pictures and texts by the audio according to the PCM volume and the number of audio channels; and the converted display elements are uniformly sent to a main FPGA character superposition module.
Further, an HTTP protocol stack is established in the ARM, WEBserver is configured, and the control equipment completes the configuration of the positions, the sizes and the characters needing to be superposed of different channel pictures through a WEB page.
Further, 4 slave FPGAs can process the maximum 8-path 4K ultra-high-definition signals.
The invention relates to a using method of an ultra-high definition SDI and IP multi-picture signal processor, which comprises the following steps:
step 1, accessing signals through an SDI input interface and an IP input interface into a scheduling matrix module; the user can control the scheduling matrix module through the ARM, select signals needing to be displayed and schedule different signals to different display picture windows;
step 2, the signals after passing through the scheduling matrix module enter a main FPGA after being balanced, a serial-parallel conversion module in the main FPGA converts the input serial SDI signals into parallel data with 20 bits, and unified clock synchronization processing is realized;
step 3, the master FPGA sends the video and audio data processed by the unified clock to 4 first slave FPGAs and 1 second slave FPGA through an I2C module;
step 4, writing data contents into the DDR from the FPGA for picture scaling processing, and realizing scaling of different resolutions according to control instructions transmitted by the ARM; then, the zoomed data is returned to a synthesis module in the main FPGA through an I2C module, and the main FPGA synthesizes an output picture;
and 5, writing the data content into the DDR from the FPGA for image-text processing: converting the characters input by the user through the ARM into key signals and filling signals; forming dynamic sound column pictures and texts by the audio according to the PCM volume and the number of audio channels; the graphic and text information is uniformly sent to a main FPGA character superposition module, and is sent to a scheduling matrix module after superposition of an output picture and a display element is completed;
and 6, scheduling the picture to a corresponding output interface by the scheduling matrix module according to the output format instruction transmitted by the ARM.
The invention has the advantages that:
the multi-picture signal processor is in modular design, provides an interface for accessing a 4K ultra-high definition IP signal, and can also be optionally matched with an SDI interface; the interface can be replaced as required, and can be directly accessed to a non-compressed IP signal, so that mixed access of SDI and IP signals is realized;
the multi-picture signal processor reduces the intermediate processing link, simplifies the design of the system scheme and the construction cost; the single machine can process the display processing of 4K ultra-high-definition pictures with 8 channels, the position and the size of the pictures can be adjusted at will, characters can be input at will, and the overlapping position can be adjusted.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and various modifications and changes will occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. An ultra high definition SDI, IP multi-picture signal processor, comprising:
the SDI signal input interface and the SDI signal output interface are used for inputting SDI signals and outputting display pictures;
an IP signal input/output module for inputting IP signals and outputting display pictures;
the scheduling matrix module is connected with the SDI signal input interface, the SDI signal output interface and the IP signal input/output module and is used for scheduling different signals to different display picture windows and scheduling display pictures to corresponding output interfaces;
the master FPGA is connected with the scheduling matrix module and is used for converting serial SDI signals into parallel data and carrying out unified clock synchronization processing; synthesizing an output picture according to the first zooming data returned from the FPGA; superposing the output picture and the display elements to obtain the display picture;
all the first slave FPGAs are connected with the master FPGA through an I2C module and used for scaling data subjected to synchronous processing of a unified clock at different resolutions and returning the scaled data to the master FPGA;
and the second slave FPGA is connected with the master FPGA and used for converting the audio data synchronously processed by the unified clock and returning the converted display elements to the master FPGA.
2. The ultra high definition SDI, IP multipicture signal processor of claim 1, further comprising: ARM and single-chip microcomputer;
the ARM is connected with the scheduling matrix module, the main FPGA and the I2C module through the single chip microcomputer, and is connected with the second slave FPGA and used for:
the user controls the scheduling matrix module through the ARM, selects signals needing to be displayed and schedules different signals to different display picture windows;
the scheduling matrix module schedules the picture to a corresponding output interface according to the output format instruction sent by the ARM;
the first slave FPGA carries out scaling of different resolutions according to the control instruction transmitted by the ARM;
and the second slave FPGA converts the characters input by the user through the ARM into key signals and filling signals, forms dynamic sound column images and texts by audio according to the PCM volume and the number of audio channels, and finally converts the dynamic sound column images and texts into display elements.
3. The ultra-high definition SDI, IP multi-picture signal processor of claim 2 wherein an HTTP protocol stack is built in the ARM, a WEBserver is configured, and the control device completes the configuration of the position, size, and character to be superimposed of the different channel pictures through a WEB page.
4. The ultra-high definition SDI, IP multipicture signal processor of claim 1, wherein the first slave FPGA writes the received data into the DDR to perform the picture scaling process.
5. The ultra high definition SDI, IP multipicture signal processor of claim 1, wherein the master FPGA comprises:
a serial-to-parallel conversion module for converting an input serial SDI signal into 20-bit parallel data;
the synthesis module is used for synthesizing an output picture according to the first zooming data returned from the FPGA;
and the superposition module is used for superposing the output picture and the display elements to obtain the display picture.
6. The ultra-high definition SDI, IP multi-picture signal processor of claim 2 wherein the number of the first slave FPGAs is 4, and the 4 slave FPGAs can process a maximum of 8-way 4K ultra-high definition signals.
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Cited By (1)
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| CN114567712A (en) * | 2022-04-27 | 2022-05-31 | 成都卓元科技有限公司 | Multi-node net signal scheduling method based on SDI video and audio signals |
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